CN213690363U

CN213690363U - Current limiting point setting circuit

Info

Publication number: CN213690363U
Application number: CN202022738333.8U
Authority: CN
Inventors: 陈翀
Original assignee: Shenzhen H&T Intelligent Control Co Ltd
Current assignee: Shenzhen H&T Intelligent Control Co Ltd
Priority date: 2020-11-23
Filing date: 2020-11-23
Publication date: 2021-07-13
Anticipated expiration: 2030-11-23

Abstract

The embodiment of the utility model provides a relate to current detection technical field, disclose a current-limiting point sets up circuit, include: the transistor comprises a transistor, a controller, a first resistor, a second resistor and a third resistor, wherein the first end of the transistor is connected with the controller, the second end of the transistor is connected with the first resistor, the second end of the transistor is connected with an IC (integrated circuit) as a current limiting point, the third end of the transistor is grounded through the second resistor, one end of the third resistor is grounded, and the other end of the third resistor is connected with the first resistor. In this way, the embodiment of the utility model provides a can realize IC low cost, low temperature drift, nimble convenient different current-limiting point's configuration.

Description

Current limiting point setting circuit

Technical Field

The embodiment of the utility model provides a relate to current detection technical field, concretely relates to current limiting point sets up circuit.

Background

Along with the diversification of the requirements of people on the types of household electrical appliances, different design requirements are provided for the electric control board in the household electrical appliances. In order to reduce the cost, each home appliance brand supplier usually selects a design mode in which a plurality of similar models share one Circuit board, and when designing the Circuit boards of the same type and different models, it is often necessary to configure the current limiting point of an Integrated Circuit (IC) through software, so that it is very necessary to research a current limiting point configuration Circuit which is low in cost, low in temperature drift, flexible and convenient.

For the requirement that the current limiting points of the IC are configured by software, if the IC has no specific functional pin, the configuration of different current limiting points can be realized only by configuring the sampling resistor outside the IC. The existing circuit usually adopts a power MOS tube to select a sampling resistor combination mode, so as to realize the configuration of different current limiting points. Therefore, the conduction internal resistance of the power MOS tube is far lower than the sampling resistance, and the requirement on the temperature drift coefficient of the conduction internal resistance is extremely low, so that when the type of the power MOS tube is selected, the type with large through-current capacity (small conduction internal resistance) and small temperature drift coefficient must be selected, the size of the device is increased, and the cost is increased. Because different current limiting points require different sampling resistor combinations, and conventional parameter values of the high-power resistor are limited, in order to configure the corresponding sampling resistor values, custom resistors must be selected sometimes, and the purchase cost and period of materials are increased.

SUMMERY OF THE UTILITY MODEL

In view of the above, embodiments of the present invention provide a current limiting point setting circuit, which overcomes or at least partially solves the above problems.

According to the utility model discloses an aspect of the embodiment provides a current-limiting point sets up circuit, include: the transistor comprises a transistor, a controller, a first resistor, a second resistor and a third resistor, wherein the first end of the transistor is connected with the controller, the second end of the transistor is connected with the first resistor, the second end of the transistor is connected with an IC (integrated circuit) as a current limiting point, the third end of the transistor is grounded through the second resistor, one end of the third resistor is grounded, and the other end of the third resistor is connected with the first resistor.

In an alternative form, the first resistor and the second resistor are in the form of a 0603 package.

In an optional manner, the current limit point setting circuit further includes a fourth resistor and a fifth resistor, and the first end of the transistor is connected to the controller through the fourth resistor and is grounded through the fifth resistor.

In an optional mode, the transistor is an NMOS transistor, the first terminal is a gate, the second terminal is a drain, and the third terminal is a source.

In an optional manner, the resistance values of the first resistor and the second resistor are more than 1000 times of the resistance value of the third resistor.

In an optional manner, the resistance values of the first resistor and the second resistor are more than 100 times of the on-state resistance value of the transistor.

In an alternative, the first resistor and the second resistor are chip resistors.

In an optional manner, the current limit point setting circuit further includes a sixth resistor, one end of the sixth resistor is connected to the IC, and the other end of the sixth resistor is connected to the second end of the transistor.

In an optional manner, the current limit point setting circuit further includes a first capacitor, one end of the first capacitor is connected to the IC, and the other end of the first capacitor is grounded.

In an optional mode, the IC includes a voltage comparator, an inverting input terminal of the voltage comparator is connected to the sixth resistor, and a non-inverting input terminal of the voltage comparator is connected to the reference voltage.

The utility model discloses electric current-limiting point sets up circuit includes: the transistor comprises a first end connected with the controller, a second end connected with the first resistor, a second end serving as a current limiting point and connected with an IC (integrated circuit), a third end of the transistor is grounded through the second resistor, one end of the third resistor is grounded, and the other end of the third resistor is connected with the first resistor, so that the current value of the current limiting point is related to the resistance ratio of the first resistor to the second resistor when the transistor is switched on, the relation with the switching-on internal resistance of the transistor is not large, the parameter requirement of an MOS (metal oxide semiconductor) tube used for configuring the current limiting point can be reduced, the circuit size and the cost are reduced, the temperature drift of the current limiting point is reduced, and the configuration of different current limiting points of the IC with low cost, low temperature drift, flexibility and convenience is realized.

The foregoing is only an overview of the embodiments of the present invention, and in order to make the technical means of the embodiments of the present invention more clearly understood, the embodiments of the present invention may be implemented according to the content of the description, and in order to make the above and other objects, features and advantages of the embodiments of the present invention more obvious and understandable, the following detailed description of the embodiments of the present invention is given.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

fig. 1 shows a circuit schematic diagram of a current limiting point setting circuit provided by an embodiment of the present invention.

Detailed Description

Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

Fig. 1 shows a circuit schematic diagram of a current limiting point setting circuit provided by an embodiment of the present invention. As shown in fig. 1, the current limit point setting circuit includes: the circuit comprises a transistor Q1, a controller, a first resistor R1, a second resistor R2 and a third resistor R3, wherein a first end of the transistor Q1 is connected with the controller, a second end of the transistor Q1 is connected with the first resistor R1, a second end of the transistor Q1 is used as a current limiting point and is connected with an IC, a third end of the transistor Q1 is grounded GND through the second resistor R2, one end of the third resistor R3 is grounded GND, and the other end of the third resistor R3 is connected with the first resistor R1. Therefore, when the transistor Q1 is conducted, the current-limiting point value is related to the resistance ratio of the first resistor R1 and the second resistor R2, and the relation with the conduction internal resistance of the transistor Q1 is not large, so that the parameter requirement of an MOS (metal oxide semiconductor) tube used for configuring the current-limiting point can be reduced, the circuit size is reduced, the cost is reduced, the temperature drift of the current-limiting point is reduced, and the current-limiting configuration of different points of IC (integrated circuit) with low cost, low temperature drift, flexibility and convenience is realized. The controller can be any one of the existing single chip microcomputer, processor or one of the existing single chip microcomputers. And will not be described in detail herein.

In the embodiment of the present invention, the current limiting point setting circuit further includes a fourth resistor R4 and a fifth resistor R5, the first end of the transistor Q1 passes through the fourth resistor R4 and the controller are connected, and pass through the fifth resistor R5 and the ground GND. The current limiting point setting circuit further comprises a sixth resistor R6 and a first capacitor C1, wherein one end of the sixth resistor R6 is connected with the IC, and the other end of the sixth resistor R6 is connected with the second end of the transistor Q1. One end of the first capacitor C1 is connected to the IC, and the other end is grounded to GND. The fourth resistor is a driving resistor of the transistor Q1, and the sixth resistor and the first capacitor C1 are used for filtering out stray waves and spike pulse signals in signals transmitted to the IC. The IC comprises a voltage comparator, the inverting input end of the voltage comparator is connected with the sixth resistor, and the non-inverting input end of the voltage comparator is connected with a reference voltage VREF.

In the embodiment of the present invention, the resistances of the first resistor R1 and the second resistor R2 are more than 1000 times the resistance of the third resistor R3, for example, the resistances of the first resistor R1 and the second resistor R2 are both 100 ohms, and the resistance of the third resistor R3 is 10 milliohms, so the resistances of the first resistor R1 and the second resistor R2 are much larger than the resistance of the third resistor R3. The resistances of the first resistor R1 and the second resistor R2 are more than 100 times the on-state internal resistance of the transistor Q1, for example, the resistances of the first resistor R1 and the second resistor R2 are both 100 ohms, and the on-state internal resistance of the transistor Q1 is 1 ohm, so that the on-state internal resistance of the transistor Q1 is much smaller than the resistances of the first resistor R1 and the second resistor R2. The first resistor R1 and the second resistor R2 are 0603 packaged chip resistors. The third resistor R3 is determined based on the particular sampled current. The transistor Q1 is an NMOS transistor, and has a first terminal as a gate, a second terminal as a drain, and a third terminal as a source. When a low level is input to the first terminal of the transistor Q1, the transistor Q1 is turned off, and when a high level is input to the first terminal, the transistor Q1 is turned on.

Use transistor Q1 as the NMOS pipe for the example, the utility model discloses the specific theory of operation of current limiting point setting circuit of embodiment is as follows:

the current I flows through the third resistor R3 and the controller controls the sampling by the IC. When the transistor Q1 is turned off and the controller inputs a low level signal to the first terminal of the transistor Q1, the IC sampling voltage is the voltage across the third resistor R3. The sampled voltage is transmitted to the inverting input terminal of the voltage comparator in the IC through the sixth resistor R6, and compared with the reference voltage VREF of the non-inverting input terminal, thereby achieving current limiting. When the controller inputs a high-level signal to the first terminal of the transistor Q1 to control the transistor Q1 to be turned on, the IC sampling voltage is (R2+ Rds _ on)/(R1+ R2+ Rds _ on) times of the voltage across the third resistor R3. Where Rds _ on is the on internal resistance of transistor Q1. Since the first resistor R1 and the second resistor R2 are much larger than the on-resistance Rds _ on of the transistor Q1, the sampling voltage of the IC can be approximately R2/(R1+ R2) times of the voltage across the third resistor R3, so that the current-limiting point can be set to (R1+ R2)/R2 times of the original value, and different current-limiting points can be configured. By selecting different resistance value configurations of the first resistor R1 and the second resistor R2, different proportions of current limiting point configurations can be realized.

Because the on-resistance Rds _ on of the transistor Q1 is much smaller than the first resistor R1 and the second resistor R2, the influence of the on-resistance Rds _ on of the transistor Q1 on the sampling voltage is small, so that the influence of the on-resistance Rds _ on of the transistor Q1 along with the change of the temperature on the precision of the current limiting point configuration is small, the parameter requirement of the MOS transistor can be greatly reduced, the cost, the precision and the volume of the current limiting point setting circuit are optimized, and the temperature drift of the current limiting point is reduced. In addition, the first resistor R1 and the second resistor R2 are common 0603 packaged chip resistors and are complete in variety, so that the current limiting points are convenient and flexible to configure, configuration of different IC current limiting points can be achieved under the condition of increasing extremely low cost, and flexibility of circuit design is greatly improved.

The utility model discloses electric current-limiting point sets up circuit includes: the transistor comprises a first end connected with the controller, a second end connected with the first resistor, a second end serving as a current limiting point and connected with an IC (integrated circuit), a third end of the transistor is grounded through the second resistor, one end of the third resistor is grounded, and the other end of the third resistor is connected with the first resistor, so that the current collected when the transistor is switched on is related to the resistance ratio of the first resistor and the second resistor, the relation with the on-state internal resistance of the transistor is not large, the parameter requirement of an MOS (metal oxide semiconductor) tube adopted for configuring the current limiting point can be reduced, the circuit size and the cost are reduced, the temperature drift of the current limiting point is reduced, and the configuration of different current limiting points of the IC, which is low in cost, low in temperature drift and flexible and convenient, is realized.

In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the embodiments of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be interpreted as reflecting an intention that: rather, the invention as claimed requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

Moreover, those skilled in the art will appreciate that while some embodiments herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the following claims, any of the claimed embodiments may be used in any combination.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names. The steps in the above embodiments should not be construed as limiting the order of execution unless specified otherwise.

Claims

1. A current limit point setting circuit, comprising: the transistor comprises a transistor, a controller, a first resistor, a second resistor and a third resistor, wherein the first end of the transistor is connected with the controller, the second end of the transistor is connected with the first resistor, the second end of the transistor is connected with an IC (integrated circuit) as a current limiting point, the third end of the transistor is grounded through the second resistor, one end of the third resistor is grounded, and the other end of the third resistor is connected with the first resistor.

2. The current limit point setting circuit of claim 1, wherein the first resistor and the second resistor are in a 0603 package.

3. The current limit point setting circuit of claim 1, further comprising a fourth resistor and a fifth resistor, wherein the first terminal of the transistor is connected to the controller through the fourth resistor and to ground through the fifth resistor.

4. The current limit point setting circuit of claim 1, wherein the transistor is an NMOS transistor, the first terminal is a gate, the second terminal is a drain, and the third terminal is a source.

5. The current limit point setting circuit of claim 1, wherein the first resistor and the second resistor have a resistance value that is more than 1000 times a resistance value of the third resistor.

6. The current limit point setting circuit according to claim 1, wherein the first resistor and the second resistor have a resistance value more than 100 times a resistance value of an on-state resistance of the transistor.

7. The current limit point setting circuit of claim 1, wherein the first resistor and the second resistor are chip resistors.

8. The current limit point setting circuit of claim 1, further comprising a sixth resistor having one end connected to the IC and another end connected to the second end of the transistor.

9. The current limit point setting circuit of claim 8, further comprising a first capacitor having one end connected to the IC and the other end grounded.

10. The current limit point setting circuit of claim 8, wherein the IC includes a voltage comparator, an inverting input of the voltage comparator is connected to the sixth resistor, and a non-inverting input of the voltage comparator is connected to the reference voltage.