CN213637687U - Circuit enabling oscillator to start rapid oscillation and to be stable and flash chip - Google Patents

Abstract

The utility model provides an oscillator starts stable circuit of quick oscillation and flash chip, including odd number phase inverter, through connecting first mos pipe between odd number phase inverter and even number phase inverter, connect the second mos pipe between even number phase inverter and odd number phase inverter; when the enable signal is 0, the first mos tube and the second mos tube are both turned on, the clock pulse of the oscillator is always kept at a low level, but the current of the oscillator is not turned off, so that the whole oscillator circuit can rapidly oscillate to a stable state when the enable signal returns to a high level again.

Description

Circuit enabling oscillator to start rapid oscillation and to be stable and flash chip

Technical Field

The utility model belongs to the technical field of semiconductor integrated circuit technique and specifically relates to a circuit and flash chip that oscillator launched fast oscillation stability are related to.

Background

A relatively common method of shutting down an oscillator when it is not in use is to directly turn off the current. However, when the oscillator is re-enabled, there is a settling process as shown in fig. 1, since current is re-flowed through the oscillator, during which time the frequency of the oscillator is not desirable.

Therefore, the prior art has yet to be improved.

Disclosure of Invention

An object of the utility model is to provide an oscillator launches stable circuit of rapid oscillation and flash chip can reduce oscillator frequency stability and establish time, makes the oscillator can rapid oscillation to stable state when launching.

The technical scheme of the utility model as follows: a circuit enabling fast oscillation stabilization of an oscillator comprises an odd number of inverters, wherein the number of the inverters is at least 3, the input end of a first inverter is connected with the output end of a last inverter, and the output end of a previous inverter is connected with the input end of a next inverter between the first inverter and the last inverter; the current input end of each phase inverter is connected with one end of a second current source I0, the other end of the second current source I0 is connected with one end of a first current source Itot, the other end of the second current source I0 is connected with a power supply voltage VCC, the other end of the first current source Itot is connected with the power supply voltage VCC, the current output end of each phase inverter is connected with one end of a third current source I1, the other end of the third current source I1 is grounded GND, and the output end of the last phase inverter outputs oscillator clock pulse OSC _ CLK; a mos tube is connected between every two adjacent inverters, a first mos tube nm0 is connected between the odd inverters and the even inverters, the drain electrode of the first mos tube nm0 is connected with the output end of the odd inverters, the source electrode of the first mos tube nm0 is grounded, the gate electrode of the first mos tube nm0 is connected with an enable signal enb, a second mos tube pm0 is connected between the even inverters and the odd inverters, the drain electrode of the second mos tube pm0 is connected with a power supply voltage VCC, the source electrode of the second mos tube pm0 is connected with the output end of the even inverters, the gate electrode of the second mos tube pm0 is connected with an enable signal en, and the enable signal enb is the opposite phase of the enable signal en.

The oscillator enables a circuit with rapid oscillation stability, wherein the first mos transistor nm0 is an nmos transistor.

The oscillator enables a fast oscillation stable circuit, wherein the second mos transistor pm0 is a pmos transistor.

The oscillator enables a circuit with fast oscillation stabilization, wherein 5 inverters are arranged.

The oscillator enables a circuit with rapid oscillation stabilization, wherein a first mos transistor nm0 is arranged between a first inverter and a second inverter, a second mos transistor pm0 is arranged between the second inverter and a third inverter, a first mos transistor nm0 is arranged between the third inverter and a fourth inverter, and a second mos transistor pm0 is arranged between the fourth inverter and a fifth inverter.

A flash chip comprises a circuit which enables fast oscillation and stabilization of an oscillator.

The utility model has the advantages that: the utility model discloses a circuit and flash chip that the oscillator started fast oscillation stability is provided, including odd number phase inverter, through connecting first mos pipe between odd number phase inverter and even number phase inverter, connect the second mos pipe between even number phase inverter and odd number phase inverter; when the enable signal is 0, the first mos tube and the second mos tube are both turned on, the clock pulse of the oscillator is always kept at a low level, but the current of the oscillator is not turned off, so that the whole oscillator circuit can rapidly oscillate to a stable state when the enable signal returns to a high level again.

Drawings

Fig. 1 is a signal waveform diagram of an enable en and an oscillator clock OSC _ CLK in the related art.

Fig. 2 is a schematic circuit diagram of the present invention, in which the oscillator enables fast oscillation stabilization.

Fig. 3 is a signal waveform diagram of the enable en and the oscillator clock OSC _ CLK according to the present invention.

Fig. 4 is a schematic circuit diagram of the inverter of the present invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are exemplary only for the purpose of explaining the present invention, and should not be construed as limiting the present invention.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and to simplify the description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.

In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.

In the present disclosure, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact between the first and second features, or may comprise contact between the first and second features not directly. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

The following disclosure provides many different embodiments or examples for implementing different features of the invention. In order to simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or reference letters in the various examples, which have been repeated for purposes of simplicity and clarity and do not in themselves dictate a relationship between the various embodiments and/or arrangements discussed. In addition, the present disclosure provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.

As shown in fig. 2, a circuit for enabling fast oscillation stabilization of an oscillator includes an odd number of inverters 1, where the number of the inverters 1 is at least 3, an input terminal of a first inverter 1 is connected to an output terminal of a last inverter 1, and an output terminal of a previous inverter 1 is connected to an input terminal of a next inverter 1 between the first inverter 1 and the last inverter 1; the current input end of each inverter 1 is connected with one end of a second current source I0, the other end of the second current source I0 is connected with one end of a first current source Itot, the other end of the second current source I0 is connected with a power supply voltage VCC, the other end of the first current source Itot is connected with the power supply voltage VCC, the current output end of each inverter 1 is connected with one end of a third current source I1, the other end of the third current source I1 is grounded GND, and the output end of the last inverter 1 outputs oscillator clock pulse OSC _ CLK; a mos tube is connected between every two adjacent inverters 1, a first mos tube nm0 is connected between the odd inverters 1 and the even inverters 1, the drain electrode of the first mos tube nm0 is connected with the output end of the odd inverters 1, the source electrode of the first mos tube nm0 is grounded GND, the gate electrode of the first mos tube nm0 is connected with an enable signal enb, a second mos tube pm0 is connected between the even inverters 1 and the odd inverters 1, the drain electrode of the second mos tube pm0 is connected with a power supply voltage VCC, the source electrode of the second mos tube pm0 is connected with the output end of the even inverters 1, the gate electrode of the second mos tube pm0 is connected with an enable signal en, and the enable signal enb is the opposite phase of the enable signal en.

In certain embodiments, the first mos tube nm0 is an nmos tube and the second mos tube pm0 is a pmos tube.

In some embodiments, as shown in fig. 4, the second current source I0 is a third mos tube pm1, the inverter 1 includes a fourth mos tube pm2 and a fifth mos tube nm1, the third current source I1 is a sixth mos tube nm2, the circuit enabling fast oscillation stabilization further includes a seventh mos tube nm3, an eighth mos tube nm4, and a ninth mos tube pm3, the drain and the gate of the seventh mos tube nm3 are connected together and then connected to the other end of the first current source itz, the source of the seventh mos tube nm3 is grounded, the gate and the drain of the eighth mos tube nm4 are connected together and then connected to the gate of the seventh mos tube nm3, the source of the eighth mos tube nm4 is grounded, the drain and the drain of the eighth mos tube nm 84 are connected to the source of the ninth mos tube 3, the drain of the ninth mos tube 3 and the drain of the third mos tube 1 are connected together and then connected to the drain of the ninth mos tube 4624 and the ninth mos tube 465 are connected together and the drain of the ninth mos tube 1, a source electrode of a fourth mos tube pm2 is connected with a drain electrode of a fifth mos tube nm1, a source electrode of a fifth mos tube nm1 is connected with a drain electrode of a sixth mos tube nm2, a source electrode of the sixth mos tube nm2 is grounded, a grid electrode of the fourth mos tube pm2 and a grid electrode of a fifth mos tube nm1 are connected together and then output an oscillator clock pulse OSC _ CLK, and a source electrode of the fourth mos tube pm2 and a drain electrode of the fifth mos tube nm1 are connected together and then are connected with a drain electrode of the first mos tube nm 0/a source electrode of the second mos tube pm 0; the grid electrode and the drain electrode of the sixth mos transistor nm2 are connected together and then connected with the grid electrode of the eighth mos transistor nm 4.

In certain embodiments, the third mos tube pm1, fourth mos tube pm2 are pmos tubes, and fifth mos tube nm1, sixth mos tube nm2 are nmos tubes.

In certain embodiments, the seventh mos tube nm3, eighth mos tube nm4 are nmos tubes, and ninth mos tube pm3 is a pmos tube.

Wherein, the inverter 1 can be provided with 3, 5, 7, etc. according to the requirement. In this embodiment, the number of the inverters 1 is 5, namely, a first inverter, a second inverter, a third inverter, a fourth inverter and a fifth inverter, a first mos transistor nm0 is arranged between the first inverter and the second inverter, a second mos transistor pm0 is arranged between the second inverter and the third inverter, a first mos transistor nm0 is arranged between the third inverter and the fourth inverter, and a second mos transistor pm0 is arranged between the fourth inverter and the fifth inverter.

The working principle of the circuit which enables the oscillator to rapidly oscillate and stabilize is as follows: when the enable signal en =1, enabling the fast oscillation stable circuit to work normally by the whole oscillator; when the enable signal en =0, enb =1, the first mos transistor nm0 and the second mos transistor pm0 are both turned on, points a and c are respectively pulled down to GND, points b and d are respectively pulled up to the power supply voltage VCC, the oscillator clock pulse OSC _ CLK is always kept at a low level, but the current is not turned off; therefore, when the enable signal en returns to the high level again, the entire circuit in which the oscillator enables the fast oscillation stabilization can oscillate fast to the stable state, wherein the signal waveforms of the enable signal en and the oscillator clock pulse OSC _ CLK are as shown in fig. 3.

The technical scheme also protects a flash chip which comprises the circuit that the oscillator enables the rapid oscillation to be stable.

In the description herein, references to the description of the terms "one embodiment," "certain embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

It is to be understood that the invention is not limited to the above-described embodiments, and that modifications and variations may be made by those skilled in the art in light of the above teachings, and all such modifications and variations are intended to be included within the scope of the invention as defined in the appended claims.

Claims (6)

1. A circuit for enabling rapid oscillation stabilization of an oscillator comprises an odd number of inverters, wherein the number of the inverters is at least 3, the input end of a first inverter is connected with the output end of a last inverter, and the output end of a previous inverter is connected with the input end of a next inverter between the first inverter and the last inverter; the current input end of each phase inverter is connected with one end of a second current source I0, the other end of the second current source I0 is connected with one end of a first current source Itot, the other end of the second current source I0 is connected with a power supply voltage VCC, the other end of the first current source Itot is connected with the power supply voltage VCC, the current output end of each phase inverter is connected with one end of a third current source I1, the other end of the third current source I1 is grounded GND, and the output end of the last phase inverter outputs oscillator clock pulse OSC _ CLK; a mos tube is connected between every two adjacent inverters, a first mos tube nm0 is connected between the odd inverters and the even inverters, the drain electrode of the first mos tube nm0 is connected with the output end of the odd inverters, the source electrode of the first mos tube nm0 is grounded, the gate electrode of the first mos tube nm0 is connected with an enable signal enb, a second mos tube pm0 is connected between the even inverters and the odd inverters, the drain electrode of the second mos tube pm0 is connected with a power supply voltage VCC, the source electrode of the second mos tube pm0 is connected with the output end of the even inverters, the gate electrode of the second mos tube pm0 is connected with an enable signal en, and the enable signal enb is the opposite phase of the enable signal en.

2. The circuit for enabling fast oscillation stabilization of an oscillator according to claim 1, wherein the first mos transistor nm0 is an nmos transistor.

3. The circuit for enabling fast oscillation stabilization of an oscillator according to any one of claims 1 or 2, wherein the second mos transistor pm0 is a pmos transistor.

4. The circuit of claim 1, wherein the number of inverters is 5.

5. The circuit of claim 4, wherein a first mos transistor nm0 is disposed between the first inverter and the second inverter, a second mos transistor pm0 is disposed between the second inverter and the third inverter, a first mos transistor nm0 is disposed between the third inverter and the fourth inverter, and a second mos transistor pm0 is disposed between the fourth inverter and the fifth inverter.

6. A flash chip comprising the oscillator according to any one of claims 1 to 5 enabling fast oscillation stabilization.

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