CN213581884U

CN213581884U - Load current switching quick response LDO circuit

Info

Publication number: CN213581884U
Application number: CN202023180440.XU
Authority: CN
Inventors: 唐生霞; 康等连; 唐太平
Original assignee: Individual
Current assignee: Individual
Priority date: 2020-12-25
Filing date: 2020-12-25
Publication date: 2021-06-29
Anticipated expiration: 2030-12-25

Abstract

The utility model discloses a load current switches quick response LDO circuit mainly includes error amplifier, first output drive tube, first resistance, second resistance, output voltage detection circuitry and load current detection circuitry, and load current detection circuitry includes second output drive tube, fourth output drive tube and fifth output drive tube, and output voltage detection circuitry includes third output drive tube, sixth output drive tube and comparator. The utility model discloses output voltage detection circuitry and load current detection circuitry have been added in traditional LDO circuit framework to feed back error amplifier with its testing result, through the biasing current who changes error amplifier, realize the dynamic quick response to the load change.

Description

Load current switching quick response LDO circuit

Technical Field

The utility model belongs to the technical field of the circuit, concretely relates to load current switches quick response LDO circuit.

Background

At present, portable electronic products powered by batteries are widely popularized, and people hope to prolong the single use time of the batteries and the service life of the batteries. The trend of the future development of the power management chip is that the required performance index can be quickly reached when the load current changes with low power consumption in no load. However, the low power consumption means that the dynamic characteristics of the circuit will be deteriorated, so that the output voltage will fluctuate greatly when the load current is switched, and the circuit cannot be used normally.

SUMMERY OF THE UTILITY MODEL

The utility model aims at solving the technical problem who exists among the prior art, provide one kind and can its electric current of real-time dynamic adjustment to reach the switching of quick tracking load current, realize stabilizing output voltage's load current switching quick response LDO circuit.

In order to achieve the above purpose, the utility model adopts the following technical scheme: a load current switching fast response LDO circuit comprises an error amplifier, a first output driving tube, a first resistor, a second resistor, an output voltage detection circuit and a load current detection circuit, wherein the load current detection circuit comprises a second output driving tube, a fourth output driving tube and a fifth output driving tube, the output voltage detection circuit comprises a third output driving tube, a sixth output driving tube and a comparator, the output end of the error amplifier is respectively connected with the grid electrode of the first output driving tube and the grid electrode of the second output driving tube, the source electrode of the first output driving tube is connected with the source electrode of the second output driving tube, the drain electrode of the first output driving tube is respectively connected with the output end of a voltage stabilizer and one end of the first resistor, the other end of the first resistor is respectively connected with the in-phase input end of the error amplifier and one end of the second resistor, the other end of the second resistor is grounded, the drain electrode of the second output driving tube is connected with the drain electrode of the fourth output driving tube, the grid electrode of the fourth output driving tube is respectively connected with the grid electrode of the fifth output driving tube and the drain electrode of the fourth output driving tube, the source electrode of the fourth output driving tube is respectively connected with the source electrode of the third output driving tube and the source electrode of the fifth output driving tube and grounded, the grid electrode of the third output driving tube is a bias voltage input end, the drain electrode of the third output driving tube is connected with the drain electrode of the sixth output driving tube, the grid electrode of the sixth output driving tube is connected with the output end of a comparator, the inverting input end of the comparator is connected with the output end of a voltage stabilizer, and the source electrode of the sixth output driving tube is respectively connected with the drain electrode of the fifth output driving tube, the source electrode of the fifth output driving tube and the current end of the error amplifier.

Further, the first output driving tube and the second output driving tube are PMOS tubes.

Further, the third output driving tube, the fourth output driving tube, the fifth output driving tube and the sixth output driving tube are NMOS tubes.

The utility model discloses relative prior art has following beneficial effect: the utility model discloses a load current switches quick response LDO circuit mainly includes error amplifier, first output drive tube, first resistance, second resistance, output voltage detection circuitry and load current detection circuitry, and load current detection circuitry includes second output drive tube, fourth output drive tube and fifth output drive tube, and output voltage detection circuitry includes third output drive tube, sixth output drive tube and comparator. The utility model discloses output voltage detection circuitry and load current detection circuitry have been added in traditional LDO circuit framework to feed back error amplifier with its testing result, through the biasing current who changes error amplifier, realize the dynamic quick response to the load change. Specifically, the current of the first output driving tube is mirrored by the second output driving tube in proportion, and the current is fed back to the error amplifier through the fourth output driving tube and the fifth output driving tube, and the current feedback can better track the load current change to adjust the bandwidth and the slew rate of the error amplifier in real time. The third output driving tube generates another path of current through the bias voltage and acts together with the sixth output driving tube and the comparator, when the output voltage is smaller than the set voltage, the sixth output driving tube is opened, the current generated by the third output driving tube is fed back to the error amplifier, and the bandwidth and the slew rate of the error amplifier are also improved. In summary, through the two paths, an extra current is provided for the bias current of the error amplifier in addition to the bias current of the conventional architecture, so as to dynamically adjust the total current in real time, thereby achieving the purposes of quickly tracking the load current switching and stabilizing the output voltage.

Drawings

Fig. 1 is a schematic circuit diagram of the present invention.

The utility model discloses the reference sign is as follows: EA. An error amplifier; p1, a first output drive tube; p2, a second output drive tube; n1, a third output driving tube, N2 and a fourth output driving tube; n3, a fifth output drive tube; n4, a sixth output drive tube; CMP, comparator; r1, a first resistor; r2, a second resistor; vfb, non-inverting input; VO, output voltage; vb1, bias voltage; VP and set voltage; iea, bias current; ib. Except for the traditional framework bias current; iext, extra current; vdd, supply voltage.

Detailed Description

The present invention will be further described with reference to the accompanying drawings and the following detailed description.

As shown in FIG. 1, a LDO circuit with fast response to load current switching comprises an error amplifier EA, a first output driving tube P1, a first resistor R1, a second resistor R2, an output voltage detection circuit and a load current detection circuit, wherein the load current detection circuit comprises a second output driving tube P2, a fourth output driving tube N2 and a fifth output driving tube N3, the output voltage detection circuit comprises a third output driving tube N1, a sixth output driving tube N4 and a comparator CMP, the first output driving tube P1 and the second output driving tube P2 are PMOS tubes, the third output driving tube N1, the fourth output driving tube N2, the fifth output driving tube N3 and the sixth output driving tube N4 are NMOS tubes, the output ends of the error amplifier EA are respectively connected with the grid of the first output driving tube P1 and the grid of the second output driving tube P2, the source electrode of the first output driving tube P1 is connected with the source electrode of the second output driving tube P2 and is connected with the power supply voltage (Vdd voltage), the drain of the first output driving tube P1 is connected to the output end of the voltage stabilizer and one end of the first resistor R1, the other end of the first resistor R1 is connected to the non-inverting input end of the error amplifier EA and one end of the second resistor R2, the other end of the second resistor R2 is grounded, the drain of the second output driving tube P2 is connected to the drain of the fourth output driving tube N2, the gate of the fourth output driving tube N2 is connected to the gate of the fifth output driving tube N3 and the drain of the fourth output driving tube N2, the source of the fourth output driving tube N2 is connected to the source of the third output driving tube N1 and the source of the fifth output driving tube N3 and grounded, the gate of the third output driving tube N1 is the bias voltage input end, the drain of the third output driving tube N1 is connected to the drain of the sixth output driving tube N4, and the gate of the sixth output driving tube N4 is connected to the output end of the comparator CMP, the inverting input end of the comparator CMP is connected with the output end of the voltage regulator, and the source electrode of the sixth output driving tube N4 is respectively connected with the drain electrode of the fifth output driving tube N3, the source electrode of the fifth output driving tube N3 and the current end of the error amplifier EA.

In fig. 1, the dotted line frame is traditional LDO circuit architecture outward, does in the dotted line frame the utility model discloses the circuit structure that increases, first resistance R1, second resistance R2 carry out the partial pressure through carrying out output voltage VO and input error amplifier EA in-phase input end, through the feedback mechanism for Vfb = Vbg, accomplishes final output voltage VO's control. The second output driving tube P2 mirrors the current of the first output driving tube P1 in proportion, and feeds the current back to the current end of the error amplifier EA through the fourth output driving tube N2 and the fifth output driving tube N3, and the current feedback can better track the load current change to adjust the bandwidth and the slew rate of the error amplifier EA in real time. The third output driving tube N1 generates another current by the bias voltage Vb1, and operates together with the sixth output driving tube N4 and the comparator CMP, when the output voltage VO is smaller than the set voltage VP, the sixth output driving tube N4 is turned on, and the current generated by the third output driving tube N1 is fed back to the current end of the error amplifier EA, thereby similarly improving the bandwidth and slew rate thereof. Through the two paths, an extra current Iext except the bias current Ib of the traditional framework is provided for the bias current Iea of the error amplifier EA, and then the total current of the error amplifier EA is dynamically adjusted in real time, so that the purposes of quickly tracking load current switching and stabilizing output voltage are achieved.

The utility model discloses well first output drive tube P1, second output drive tube P2, third output drive tube N1, fourth output drive tube N2, fifth output drive tube N3, sixth output drive tube N4 can be replaced with corresponding BJT and other devices.

Claims

1. A load current switching (LDO) circuit with fast response, characterized in that: the voltage stabilizer comprises an Error Amplifier (EA), a first output driving tube (P1), a first resistor (R1), a second resistor (R2), an output voltage detection circuit and a load current detection circuit, wherein the load current detection circuit comprises a second output driving tube (P2), a fourth output driving tube (N2) and a fifth output driving tube (N3), the output voltage detection circuit comprises a third output driving tube (N1), a sixth output driving tube (N4) and a Comparator (CMP), the output end of the Error Amplifier (EA) is respectively connected with the grid electrode of the first output driving tube (P1) and the grid electrode of the second output driving tube (P2), the source electrode of the first output driving tube (P1) is connected with the source electrode of the second output driving tube (P2), the drain electrode of the first output driving tube (P1) is respectively connected with the output end and one end of the first resistor (R1), the other end of the first resistor (R1) is respectively connected with a non-inverting input end of an Error Amplifier (EA) and one end of a second resistor (R2), the other end of the second resistor (R2) is grounded, the drain of the second output drive tube (P2) is connected with the drain of a fourth output drive tube (N2), the grid of the fourth output drive tube (N2) is respectively connected with the grid of a fifth output drive tube (N3) and the drain of a fourth output drive tube (N2), the source of the fourth output drive tube (N2) is respectively connected with the source of a third output drive tube (N1) and the source of the fifth output drive tube (N3) and grounded, the grid of the third output drive tube (N1) is a bias voltage input end, the drain of the third output drive tube (N1) is connected with the drain of a sixth output drive tube (N4), and the grid of the sixth output drive tube (N4) is connected with a CMP output end, the inverting input end of the Comparator (CMP) is connected with the output end of the voltage stabilizer, and the source electrode of the sixth output driving tube (N4) is respectively connected with the drain electrode of the fifth output driving tube (N3), the source electrode of the fifth output driving tube (N3) and the current end of the Error Amplifier (EA).

2. The LDO circuit of claim 1, wherein: the first output driving pipe (P1) and the second output driving pipe (P2) are PMOS pipes.

3. The LDO circuit of claim 1, wherein: the third output driving tube (N1), the fourth output driving tube (N2), the fifth output driving tube (N3) and the sixth output driving tube (N4) are NMOS tubes.