CN213518223U - On-missile navigation data acquisition system - Google Patents
On-missile navigation data acquisition system Download PDFInfo
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- CN213518223U CN213518223U CN202022555760.2U CN202022555760U CN213518223U CN 213518223 U CN213518223 U CN 213518223U CN 202022555760 U CN202022555760 U CN 202022555760U CN 213518223 U CN213518223 U CN 213518223U
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Abstract
The utility model relates to a missile-borne navigation data acquisition system, which comprises a singlechip unit, a flash unit and an interface unit; the interface unit is connected with the singlechip unit; the device comprises a first external interface, a second external interface and a third external interface; the first external interface is connected with the wireless filler and used for filling the navigation auxiliary information into the single chip microcomputer unit; the second external interface is connected with the upper computer and used for data interaction between the single chip microcomputer unit and the upper computer; the third external interface is connected with the missile-borne navigation receiver and is used for navigation data interaction between the single chip microcomputer unit and the missile-borne navigation receiver; the flash unit is connected with the single chip microcomputer unit and used for storing navigation data output by the single chip microcomputer unit. The utility model discloses an at bullet flight in-process data collection, go up the electricity again after the bullet lands, read navigation data and preserve the host computer to and the write protect function of data on the bullet.
Description
Technical Field
The utility model relates to a data acquisition technical field especially relates to a navigation data acquisition system on bullet.
Background
The acquisition of the on-missile navigation data is different from the acquisition of common navigation data, the data needs to be acquired in the missile flight process, after the missile falls to the ground, the on-missile navigation data acquisition system is dug out, the power is supplied again, the navigation data is read and stored in an upper computer, the on-missile data needs to be written and protected, and the requirements on power consumption and reliability are high, so that the acquisition of the on-missile navigation data by the on-missile navigation data acquisition system is needed.
SUMMERY OF THE UTILITY MODEL
In view of the foregoing analysis, the present invention is directed to a system for collecting navigation data on a projectile, which solves the problem of collecting navigation data on a projectile.
The purpose of the utility model is mainly realized through the following technical scheme:
a system for acquiring missile-borne navigation data comprises a single chip microcomputer unit, a flash unit and an interface unit;
the interface unit is connected with the single chip microcomputer unit; the device comprises a first external interface, a second external interface and a third external interface;
the first external interface is connected with the wireless filler and used for filling the navigation auxiliary information into the single chip microcomputer unit; the second external interface is connected with the upper computer and used for data interaction between the single chip microcomputer unit and the upper computer; the third external interface is connected with the missile-borne navigation receiver and is used for navigation data interaction between the single chip microcomputer unit and the missile-borne navigation receiver;
the flash unit is connected with the single chip microcomputer unit and used for storing navigation data output by the single chip microcomputer unit.
Further, the singlechip unit adopts an STM32L151C8T6 singlechip chip.
Furthermore, the FLASH unit selects a W25Q64 JVXGAQ serial FLASH NOR FLASH chip; the NOR FLASH chip is connected with the single chip microcomputer chip through an SPI interface.
Furthermore, the single chip microcomputer chip is also connected with a hardware write protection pin 3 of the NOR FLASH chip through an I/O pin and is used for outputting a signal NOWP to control the hardware write protection function of the NOR FLASH chip.
Further, the first external interface is an RS422 interface.
Further, the second external interface is an RS232 interface.
Further, the third external interface is an RS422 interface.
The power supply unit is used for supplying power to the single chip microcomputer unit, the flash unit and the interface unit and comprises a first power supply input end, a second power supply input end and a third power supply input end;
the first power supply input end is used for connecting a missile-borne 12V power supply; the second power supply input end is used for connecting a 12V analog pop-up power supply; and the third power supply input end is used for connecting a 5V debugging power supply.
Further, a diode D3 which is connected in the forward direction is connected between the anode of the first power supply input end and the anode of the second power supply input end; converting a direct current 12V power supply input by a first power supply input end or a second power supply input end into a direct current 5V power supply VCC _5V through a power supply chip TPS 562209; the VCC _5V is connected with pin 1 of BAS40-05-7, the anode of the third power supply input end is connected with pin 2 of BAS40-05-7, pin 3 of BAS40-05-7 is connected with the input end of a power supply chip TPS62237, and the output end of the power supply chip TPS62237 outputs 3.3V direct-current power supply to supply power to the single chip microcomputer unit, the flash unit and the interface unit.
Furthermore, a series circuit composed of resistors R11 and R18 is connected between the positive electrode and the negative electrode of the third power supply input end, and a signal WAKE is led out from the connection end of the resistors R11 and R18 and connected to the single chip microcomputer unit to serve as a trigger signal for judging whether the single chip microcomputer unit performs hardware write protection on the flash unit.
The utility model has the advantages as follows:
the utility model discloses an at bullet flight in-process data collection, go up the electricity again after the bullet lands, read navigation data and preserve the host computer to and the write protection of data on the bullet. The system of the embodiment has low power consumption, stability, reliability, real and accurate data acquisition and convenient data display and storage.
Drawings
The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention, wherein like reference numerals are used to designate like parts throughout the drawings.
Fig. 1 is a schematic view of a connection structure of a missile-borne navigation data acquisition system according to an embodiment of the present invention;
fig. 2 is a circuit diagram of a single chip microcomputer in the embodiment of the present invention;
fig. 3 is a circuit diagram of a flash unit according to an embodiment of the present invention;
fig. 4 is a circuit diagram of an RS422 interface in an embodiment of the present invention;
fig. 5 is a circuit diagram of an RS232 interface in an embodiment of the present invention;
fig. 6 is a circuit diagram of a power supply unit according to an embodiment of the present invention.
Detailed Description
The following detailed description of the preferred embodiments of the invention, which is to be read in connection with the accompanying drawings, forms a part of this application, and together with the embodiments of the invention, serve to explain the principles of the invention.
The utility model discloses a specific embodiment of the utility model discloses a missile-borne navigation data acquisition system, as shown in figure 1, comprising a singlechip unit, a flash unit, an interface unit and a power supply unit;
the interface unit is connected with the single chip microcomputer unit; the device comprises a first external interface, a second external interface and a third external interface;
the first external interface is connected with the wireless filler and used for filling the navigation auxiliary information into the single chip microcomputer unit; the second external interface is connected with the upper computer and used for data interaction between the single chip microcomputer unit and the upper computer; the third external interface is connected with the missile-borne navigation receiver and is used for navigation data interaction between the single chip microcomputer unit and the missile-borne navigation receiver;
the flash unit is connected with the single chip microcomputer unit and used for storing navigation data output by the single chip microcomputer unit.
Specifically, the single chip microcomputer unit adopts an STM32L151C8T6 single chip microcomputer chip; the single chip microcomputer chip comprises a high-performance ARM Cortex running at the frequency of 32MHzTMAn M332 bit RISC core, a high memory protection unit, a high speed embedded memory, and various enhanced I/O and peripherals connected to both APB buses. The single chip provides a 12-bit ADC, 2 DACs and 2 ultra-low power comparators, six general 16-bit timers and two basic timers, which can be used as time bases, including standard and advanced communication interfaces: up to two I2C and SPI, three USART and one USB.
As shown in fig. 2, is a single chip circuit.
The single chip microcomputer is connected with the flash unit through an STM _ F _ CS \ STM _ F _ CLK \ STM _ F _ MISO \ STM _ F _ MOSI four line.
The NOWP pin is a general GPIO port and controls the hardware write-protection function of the NOR FLASH chip; the WAKE pin is used for inputting a hardware write protection function trigger signal, and when the single chip microcomputer detects that the WAKE pin is at a high level of about 3V, NOWP is set high, and the hardware write protection function of the single chip microcomputer is released. Three USART pins of the single chip microcomputer are used, and BACKUP _ TX/BACKUP _ RX is connected with a first external interface and used for carrying out navigation auxiliary information filling with a wireless filling device; the STM _ TXD/STM _ RXD is connected with a second external interface and is used for being connected with a data acquisition interaction port of an upper computer; the JSJ _ TX/JSJ _ RX is connected with a third external interface and is used for connecting the missile-borne navigation receiver to carry out interaction of navigation data. The single chip microcomputer is also provided with a 5-pin JTAG debugging port which is matched with a crystal oscillator with 16MHz and 32.768KHz to be respectively used as a system clock and an RTC clock, and the power supply voltage is 3.3V.
Specifically, the FLASH unit selects a W25Q64 JVXGAQ serial FLASH NOR FLASH chip; the NOR FLASH chip is connected with the single chip microcomputer chip through an SPI interface.
A W25Q64JVXGIQ (64M bit) serial flash memory is selected to provide a storage solution for a system with limited storage space, pins and power supply. The W25Q64JVXGIQ provides flexibility and performance beyond that of a conventional serial flash device, and is well suited for mapping code to RAM, executing code directly from SPI, and storing voice, text, and data. The device is powered by a power supply of 2.7V to 3.6V, and the power consumption is as low as 1 muA. The W25Q64JV array is divided into 32,768 programmable pages of 256 bytes each. Up to 256 bytes can be programmed at a time. Pages may be erased in 16 groups (4KB sector erase), 128 groups (32KB block erase), 256 groups (64KB block erase) or whole chips (chip erase). W25Q64JV has 2,048 erasable sectors and 128 erasable blocks, respectively. The smaller 4KB sector provides greater flexibility for applications that require data and parameter storage. The W25Q64JV supports standard Serial Peripheral Interface (SPI), and the SPI clock frequency supporting the W25Q64JV is up to 133 MHz.
As shown in FIG. 3, the NOR FLASH chip W25Q64JVXGIQ is connected with the single chip microcomputer through four lines of STM _ F _ CS \ STM _ F _ CLK \ STM _ F _ MISO \ STM _ F _ MOSI. And performing operations such as reading, writing and erasing of data.
The single chip microcomputer chip is also connected with a hardware write protection pin 3 of the NOR FLASH chip through an I/O pin and is used for outputting a signal NOWP to control the hardware write protection function of the NOR FLASH chip; normally, NOWP is low, the write protection pin is pulled low, and the write protection can be released only when NOWP is given to high level. NOR FLASH chips also use 3.3V power.
Specifically, the first external interface is an RS422 interface, and the third external interface is also an RS422 interface.
As shown in fig. 4, westernized MAX3490E was selected for RS-422 communication with ± 15kVESD protection, +3.3V, low power transceivers, each device containing a driver and a receiver. MAX3483E and MAX3488E have slew rate limited drivers that minimize EMI and reduce reflections caused by improperly terminated cables, thereby enabling error free data transmission at data rates up to 250 kbps. The slew rate is limited in part, and the transmission rate of MAX3490E is up to 12 Mbps. This design uses two blocks of MAX 3490E.
Specifically, the second external interface is an RS232 interface.
As shown in FIG. 5, Max3225EETP + of Meixin is selected for RS-232 communication, which has + -15 kV ESD protection and +3.3V, and all devices utilize Maxim revolutionary AutoShutdown PlusTMThe function is to achieve a supply current of 1 mua. MAX3225E also has MegaBaudTMThe operating characteristics may guarantee a rate of 1Mbps for high speed applications, such as communication with ISDN modems. The transceiver has a proprietary low dropout transmitter output stage, and can achieve true RS-232 performance under a +3.0V to +5.5V power supply through a dual charge pump. The charge pump can work with 3.3V power supply by only four small 0.1 muF capacitors. The STM _ TXD \ STM _ RXD is converted into TP3_ RXD1 and TP4_ TXD1 in an RS232 format through an RS232 circuit and is used as a data acquisition interaction port with an upper computer. The TX2\ RX2 is a debugging LVTTL level from the on-board navigation device, and is converted into TP9_ RXD2 and TP10_ TXD2 in RS232 format through an RS232 circuit, and is used as a debugging port of the on-board navigation device, here, a debugging function realized by a data acquisition system is borrowed.
Specifically, the power supply unit is used for supplying power to the single chip microcomputer unit, the flash unit and the interface unit, and comprises a first power supply input end, a second power supply input end and a third power supply input end;
the first power supply input end is used for connecting a missile 12V power supply VCC _ BATTERY; the second power supply input end is used for connecting a 12V analog power supply VCC _12V _ EXD 2; the third power supply input end is used for connecting a 5V debugging power supply VCC _5V _ EXD 1.
The specific power connection diagram is shown in fig. 6, a diode D3 connected in the forward direction is connected between the positive pole of the first power input end and the positive pole of the second power input end; converting a direct current 12V power supply input by a first power supply input end or a second power supply input end into a direct current 5V power supply VCC _5V through a power supply chip TPS 562209; the VCC _5V is connected with pin 1 of BAS40-05-7, the anode of the third power supply input end is connected with pin 2 of BAS40-05-7, pin 3 of BAS40-05-7 is connected with the input end of a power supply chip TPS62237, and the output end of the power supply chip TPS62237 outputs 3.3V direct-current power supply to supply power to the singlechip unit, the flash unit and the interface unit; two schottky diodes are contained within the BAS 40-05-7.
And a series circuit consisting of resistors R11 and R18 is connected between the positive electrode and the negative electrode of the third power supply input end, and a signal WAKE is led out from the connecting end of the resistors R11 and R18 and is connected to the singlechip unit and used as a trigger signal for judging whether the singlechip unit outputs a signal NOWP.
The working modes of the three power input ends comprise: only when the data acquisition system is loaded onto the bomb can the first power input be used to connect VCC _ BATTERY, which supplies the voltage for the on-bomb thermal BATTERY. And during normal debugging, connecting the second power supply input end with VCC _12V _ EXD2 to simulate a power supply mode on the bomb. When VCC _12V _ EXD2 supplies 12V, a DCDC chip of TI company TPS562209 is selected and converted into VCC _ 5V; the 5V debugging power VCC _5V _ EXD1 connected with the third power input end is the voltage used when the data acquisition system is debugged alone, when VCC _5V _ EXD1 exists, the WAKE pin can input a high level to the single chip microcomputer, when the single chip microcomputer detects that the debugging voltage exists, the hardware write protection pin of the FLASH chip can not be removed, and in the embodiment, the hardware write protection can only be removed when a on-bomb thermal battery is used for supplying power or a power supply mode on a simulated bomb is used; otherwise, when a debug 5V voltage is used, only read operations can be performed. This also prevents the navigation data acquisition system from being recovered from the bomb, and the data is wrongly written into the NOR FLASH chip, so that the data in the FLASH is flushed.
In summary, the embodiment realizes data acquisition in the bullet flight process, power on again after the bullet lands, navigation data reading and storage in the upper computer, and write protection of the data on the bullet. The system of the embodiment has low power consumption, stability, reliability, real and accurate data acquisition and convenient data display and storage.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention should be covered by the present invention.
Claims (10)
1. A system for acquiring missile-borne navigation data is characterized by comprising a single chip microcomputer unit, a flash unit and an interface unit;
the interface unit is connected with the single chip microcomputer unit; the device comprises a first external interface, a second external interface and a third external interface;
the first external interface is connected with the wireless filler and used for filling the navigation auxiliary information into the single chip microcomputer unit; the second external interface is connected with the upper computer and used for data interaction between the single chip microcomputer unit and the upper computer; the third external interface is connected with the missile-borne navigation receiver and is used for navigation data interaction between the single chip microcomputer unit and the missile-borne navigation receiver;
the flash unit is connected with the single chip microcomputer unit and used for storing navigation data output by the single chip microcomputer unit.
2. The system for acquiring data of on-board navigation according to claim 1, wherein the single chip microcomputer unit is an STM32L151C8T6 single chip microcomputer chip.
3. The system of claim 2, wherein the FLASH unit is a W25Q64JVXGIQ serial FLASH NOR FLASH chip; the NOR FLASH chip is connected with the single chip microcomputer chip through an SPI interface.
4. The system of claim 3, wherein the single-chip microcomputer chip is further connected to a hardware write protect pin 3 of the NOR FLASH chip via an I/O pin, and is configured to output a NOWP control signal to control a hardware write protect function of the NOR FLASH chip.
5. The system according to claim 1, wherein the first external interface is an RS422 interface.
6. The system according to claim 1, wherein the second external interface is an RS232 interface.
7. The system according to claim 1, wherein the third external interface is an RS422 interface.
8. The system for acquiring the navigation data on the bullet according to any one of claims 1 to 7, further comprising a power supply unit, wherein the power supply unit is used for supplying power to the single chip microcomputer unit, the flash unit and the interface unit, and comprises a first power supply input end, a second power supply input end and a third power supply input end;
the first power supply input end is used for connecting a missile-borne 12V power supply; the second power supply input end is used for connecting a 12V analog pop-up power supply; and the third power supply input end is used for connecting a 5V debugging power supply.
9. The system according to claim 8, wherein a diode D3 connected in a forward direction is connected between the positive pole of the first power input terminal and the positive pole of the second power input terminal; converting a direct current 12V power supply input by a first power supply input end or a second power supply input end into a direct current 5V power supply VCC _5V through a power supply chip TPS 562209; the VCC _5V is connected with pin 1 of BAS40-05-7, the anode of the third power supply input end is connected with pin 2 of BAS40-05-7, pin 3 of BAS40-05-7 is connected with the input end of a power supply chip TPS62237, and the output end of the power supply chip TPS62237 outputs 3.3V direct-current power supply to supply power to the single chip microcomputer unit, the flash unit and the interface unit.
10. The system for acquiring navigation data on a bullet according to claim 9, wherein a series circuit composed of resistors R11 and R18 is connected between the positive and negative poles of the third power input terminal, and a signal WAKE is led out from the connection end of the resistors R11 and R18 and connected to the single chip microcomputer unit, so as to be used as a trigger signal for whether the single chip microcomputer unit performs hardware write protection on the flash unit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022555760.2U CN213518223U (en) | 2020-11-06 | 2020-11-06 | On-missile navigation data acquisition system |
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| CN202022555760.2U CN213518223U (en) | 2020-11-06 | 2020-11-06 | On-missile navigation data acquisition system |
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| CN213518223U true CN213518223U (en) | 2021-06-22 |
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