CN213458019U - Digital signal generating device based on FPGA - Google Patents

Abstract

The utility model provides a digital signal generating device based on FPGA, including wireless communication module, FPGA module, DA conversion module, filter module, emitter follower module, wireless communication module with the FPGA module links to each other, the FPGA module with the DA conversion module links to each other, the DA conversion module with the filter module links to each other, the filter module with the emitter follower module links to each other; the DA conversion module comprises a subtractor consisting of a DAC902 analog-to-digital converter and an OPA690 operational amplifier; the filter module comprises a resistor, a capacitor and an inductor; the emitter follower module includes an OPA228 operational amplifier, with the inverting input of the OPA228 connected to the output. The utility model discloses simple structure, the operation is simple and easy, and the user can remote operation the device for many places equipment when debugging personnel can debug simultaneously when many places equipment need debug, and need not frequently come and go in equipment adjustment parameter everywhere.

Description

Digital signal generating device based on FPGA

Technical Field

The utility model belongs to the technical field of signal processing, concretely relates to digital signal generation device based on FPGA.

Background

A signal generator is a device that can provide electrical signals of various frequencies, waveforms and output levels. The device is used as a signal source or an excitation source for testing when measuring amplitude characteristics, frequency characteristics, transmission characteristics and other electrical parameters of various telecommunication systems or telecommunication equipment and when measuring characteristics and parameters of components. In modern production, signal generators are widely used, including in the fields of communications, broadcasting, television systems, quenching, ultrasonic diagnosis, magnetic resonance imaging, and the like.

With the development of digital technology, digital signal generators currently occupy the vast majority of the market for signal generators. However, the operation of the present digital signal generator is complex, and in practical work, a plurality of devices far apart are often required to be debugged, and a debugging person is required to frequently go to and fro between the devices to debug, so that it is necessary to design a digital signal generator which has a simple structure, is easy to operate, and can be remotely operated.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a weak point to prior art, provide a simple structure, operation and simply just can remote operation's digital signal generating device.

In order to solve the technical problem, the utility model provides a digital signal generating device based on FPGA, including wireless communication module, FPGA module, DA conversion module, filter module, emitter follower module, wireless communication module with the FPGA module links to each other, the FPGA module with the DA conversion module links to each other, DA conversion module with the filter module links to each other, the filter module with the emitter follower module links to each other, the FPGA module includes FPGA and touch-control display screen, FPGA with the touch-control display screen links to each other; the DA conversion module comprises a subtractor consisting of a DAC902 analog-to-digital converter and an OPA690 operational amplifier; the filter module comprises a resistor, a capacitor and an inductor, wherein the input end of the first resistor is connected with the input end of the filter module, the output end of the first resistor is respectively connected with the input end of the first capacitor and the input end of the first inductor, the output end of the first inductor is respectively connected with the input end of the second capacitor and the input end of the second inductor, the output end of the second inductor is respectively connected with the input end of the third capacitor and the input end of the third inductor, the output end of the third inductor is respectively connected with the input end of the fourth capacitor and the input end of the fourth inductor, the output end of the fourth inductor is respectively connected with the input end of the fifth capacitor and the input end of the fifth inductor, the output end of the fifth inductor is respectively connected with the input end of the second resistor and the output end of the filter, the output end of the first capacitor, the output end of the second capacitor, the output end of, An output terminal of the third capacitor, an output terminal of the fourth capacitor, an output terminal of the fifth capacitor, and an output terminal of the second resistor are grounded, the first resistor and the second resistor are 50 ohms, inductance values of the first inductor, the second inductor, the third inductor, the fourth inductor, and the fifth inductor are 180.6nH, 354.5nH, 393nH, 281.3nH, and 62.24nH, respectively, and capacitance values of the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, and the fifth capacitor are 24.9pF, 112.5pF, 157.2pF, 141.8pF, and 72.25pF, respectively; the emitter follower module includes an OPA228 operational amplifier, with the inverting input of the OPA228 connected to the output.

In one embodiment, the wireless communication module is a bluetooth module.

In one embodiment, the wireless communication module is a Wi-Fi module.

In one embodiment, the wireless communication module is a ZigBee module.

Compared with the prior art, the beneficial effects of the utility model are that: the touch display screen is arranged, so that the digital signal generating device is simple to operate, and the wireless communication module is arranged, so that a user can remotely operate the device, and can debug a plurality of devices simultaneously without going to and from the devices when the devices are needed to be debugged.

Drawings

FIG. 1 is a general block diagram of the present invention;

fig. 2 is a schematic diagram of the FPGA module of the present invention;

fig. 3 is a circuit diagram of the DA conversion module of the present invention;

fig. 4 is a circuit diagram of a filter module of the present invention;

fig. 5 is a schematic diagram of the emitter follower module of the present invention.

Detailed Description

In order to make those skilled in the art better understand the technical solutions in the present specification, the technical solutions in the embodiments of the present specification will be clearly and completely described below with reference to the drawings in the embodiments of the present specification, and it is obvious that the described embodiments are only a part of the embodiments of the present specification, and not all of the embodiments. All other embodiments obtained by a person skilled in the art based on the embodiments in the present specification without any inventive step should fall within the scope of protection of the present specification. And the drawings described are only schematic and are non-limiting.

In this context, for the sake of brevity, not all possible combinations of individual features in the various embodiments or examples are described. Therefore, the respective features in the respective embodiments or examples may be arbitrarily combined as long as there is no contradiction between the combinations of the features, and all the possible combinations should be considered as the scope of the present specification.

The contents appearing in the present invention, which do not belong to the protection object of the present invention, are all for making the technical personnel in the field understand the present solution more easily, and should not be understood as seeking protection to these contents, and these contents all belong to the prior art.

As shown in the attached drawing 1, the utility model provides a digital signal generating device based on FPGA, including wireless communication module 1, FPGA module 2, DA conversion module 3, filter module 4, emitter follower module 5, wireless communication module 1 with FPGA module 2 links to each other, FPGA module 2 with DA conversion module 3 links to each other, DA conversion module 3 with filter module 4 links to each other, filter module 4 with emitter follower module 5 links to each other, FPGA module 2 includes FPGA and touch-control display screen, FPGA with touch-control display screen links to each other; the DA conversion module 3 comprises a subtractor consisting of a DAC902 analog-to-digital converter and an OPA690 operational amplifier; the filter module 4 comprises a resistor, a capacitor and an inductor, wherein the input end of the first resistor is connected with the input end of the filter module, the output end of the first resistor is respectively connected with the input end of the first capacitor and the input end of the first inductor, the output end of the first inductor is respectively connected with the input end of the second capacitor and the input end of the second inductor, the output end of the second inductor is respectively connected with the input end of the third capacitor and the input end of the third inductor, the output end of the third inductor is respectively connected with the input end of the fourth capacitor and the input end of the fourth inductor, the output end of the fourth inductor is respectively connected with the input end of the fifth capacitor and the input end of the fifth inductor, the output end of the fifth inductor is respectively connected with the input end of the second resistor and the output end of the filter, the output end of the first capacitor, the output end of the second capacitor, the input end of, An output terminal of the third capacitor, an output terminal of the fourth capacitor, an output terminal of the fifth capacitor, and an output terminal of the second resistor are grounded, the first resistor and the second resistor are 50 ohms, inductance values of the first inductor, the second inductor, the third inductor, the fourth inductor, and the fifth inductor are 180.6nH, 354.5nH, 393nH, 281.3nH, and 62.24nH, respectively, and capacitance values of the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, and the fifth capacitor are 24.9pF, 112.5pF, 157.2pF, 141.8pF, and 72.25pF, respectively; the emitter follower module 5 comprises an OPA228 operational amplifier, the inverting input of the OPA228 being connected to the output.

The DA conversion block 3 is composed of a subtractor composed of a high-speed analog-to-digital converter DAC902 and an operational amplifier OPA 690. The digital signal output by the FPGA module is buffered by a 0 ohm resistor and then input to ports 1 to 12 of the DAC902, wherein the port 1 inputs the most significant bit of the digital signal, and the port 12 inputs the least significant bit of the digital signal. The digital signal is converted into a differential analog current signal through the DAC902, and the differential analog current signal is converted into a differential voltage signal through two 50 ohm resistors. The differential voltage signal is input to the 2 and 3 ports of the subtractor constituted by the OPA690 and subtracted.

The filter module is a ten-order passive low-pass butterworth filter with a cutoff frequency of 40 MHz. Since the frequency of the clock signal used by the platform is 100MHz, the signal output by the DA conversion module is not a smooth signal but a step-by-step signal, each step having a duration of 0.00001S (1/10MHz), and the signal includes high frequency components having a frequency of 100MHz and above. Therefore, the output waveform must be filtered, and the cut-off frequency of the filter is set to 40MHz, so that the high-frequency components with the frequency of 100MHz and above can be effectively filtered out, and useful signals can be reserved. After filtering out these high frequency components, the signal is finally smoothed.

According to the embodiment, the wireless communication module and the touch display screen receive information and transmit the information to the FPGA module 2, the FPGA module 2 generates a waveform signal and displays the waveform signal through the touch display screen, and the FPGA module 2 sends the generated waveform signal to the DA conversion module 3; the DA conversion module 3 converts the digital signal into an analog signal and outputs the analog signal; the filter module 4 carries out filtering processing on the analog signal output by the DA conversion module 3 to remove high-frequency noise; the RF follower module increases the current of the analog signal, enhances the on-load capability, and isolates the system from external systems. The output of the OPA228 is the final output of the system.

In one embodiment, the wireless communication module is a bluetooth module.

In one embodiment, the wireless communication module is a Wi-Fi module.

In one embodiment, the wireless communication module is a ZigBee module.

It should be understood that parts of the specification not set forth in detail are well within the prior art. The scope of the present invention is not limited to the above-described embodiments, and it is obvious that those skilled in the art can make various modifications and variations to the present invention without departing from the scope and spirit of the present invention. It is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims (4)

1. A digital signal generating device based on FPGA comprises a wireless communication module, an FPGA module, a DA conversion module, a filter module and an emitter follower module, wherein the wireless communication module is connected with the FPGA module, the FPGA module is connected with the DA conversion module, the DA conversion module is connected with the filter module, and the filter module is connected with the emitter follower module, and is characterized in that:

the FPGA module comprises an FPGA and a touch display screen, and the FPGA is connected with the touch display screen;

the DA conversion module comprises a subtractor consisting of a DAC902 analog-to-digital converter and an OPA690 operational amplifier;

the filter module comprises a resistor, a capacitor and an inductor, wherein the input end of the first resistor is connected with the input end of the filter module, the output end of the first resistor is respectively connected with the input end of the first capacitor and the input end of the first inductor, the output end of the first inductor is respectively connected with the input end of the second capacitor and the input end of the second inductor, the output end of the second inductor is respectively connected with the input end of the third capacitor and the input end of the third inductor, the output end of the third inductor is respectively connected with the input end of the fourth capacitor and the input end of the fourth inductor, the output end of the fourth inductor is respectively connected with the input end of the fifth capacitor and the input end of the fifth inductor, the output end of the fifth inductor is respectively connected with the input end of the second resistor and the output end of the filter, the output end of the first capacitor, the output end of the second capacitor, the output end of, An output terminal of the third capacitor, an output terminal of the fourth capacitor, an output terminal of the fifth capacitor, and an output terminal of the second resistor are grounded, the first resistor and the second resistor are 50 ohms, inductance values of the first inductor, the second inductor, the third inductor, the fourth inductor, and the fifth inductor are 180.6nH, 354.5nH, 393nH, 281.3nH, and 62.24nH, respectively, and capacitance values of the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, and the fifth capacitor are 24.9pF, 112.5pF, 157.2pF, 141.8pF, and 72.25pF, respectively;

the emitter follower module includes an OPA228 operational amplifier, with the inverting input of the OPA228 connected to the output.

2. The FPGA-based digital signal generating apparatus of claim 1, wherein: the wireless communication module is a Bluetooth module.

3. The FPGA-based digital signal generating apparatus of claim 1, wherein: the wireless communication module is a Wi-Fi module.

4. The FPGA-based digital signal generating apparatus of claim 1, wherein: the wireless communication module is a ZigBee module.

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