CN213455513U

CN213455513U - Wire-saving encoder

Info

Publication number: CN213455513U
Application number: CN202022046403.3U
Authority: CN
Inventors: 王力
Original assignee: Zhejiang Ruiying Sensing Technology Co ltd
Current assignee: Zhejiang Ruiying Sensing Technology Co ltd
Priority date: 2020-09-17
Filing date: 2020-09-17
Publication date: 2021-06-15
Anticipated expiration: 2030-09-17

Abstract

The utility model discloses a province's line formula encoder, including coding disc and rotation axis, coding disc and rotation axis fixed connection still include voltage stabilizing circuit, photocell and first driver chip U3, and the input voltage of input province's line formula encoder lets in voltage stabilizing circuit and photocell respectively, and voltage stabilizing circuit is used for stabilizing input voltage at reference voltage and voltage stabilizing circuit loop through first delay circuit and second delay circuit and first driver chip U3 electric connection. The utility model discloses a economize line formula encoder, it passes through voltage stabilizing circuit and delay circuit, stabilizes input voltage at reference voltage to prevent that the change of external voltage from leading to the time delay time change, this reference voltage also is used for guaranteeing to economize line formula encoder on electric threshold voltage Va's reliable and stable simultaneously.

Description

Wire-saving encoder

Technical Field

The utility model belongs to the technical field of economize the line formula encoder, concretely relates to economize line formula encoder.

Background

The pulse encoder is an optical position detecting element, the encoding disk is fixedly connected with the rotating shaft to detect the rotating angle position and speed change of the shaft, the output signal of the pulse encoder is an electric pulse, and the pulse encoder is a common angular displacement sensor and can also be used as a speed detecting device.

The non-wire-saving encoder outputs A, B, Z, U, V and W6 signals, maintains a section of high resistance (or high level) time of Ta after the power-on of the wire-saving encoder reaches a threshold voltage Va, then generates U, V, W three signals, and finally outputs A, B, Z signals after maintaining the Tb time, so that U, V, W and A, B, Z share a transmission cable, three pairs of (U +/U-, V +/V-, W +/W-) transmission cables can be saved, the name of the wire-saving encoder is wire-saving encoder, and the power timing diagram of the wire-saving encoder can be shown in figure 9.

The advantage of the wire-saving pulse encoder is that the number of required cables is small, the installation cost of the cables is relatively low, and the wire-saving pulse encoder on the market also has the disadvantages, which are mainly expressed as follows:

firstly, the delay times Ta and Tb of the common encoders in the market are changed along with the change of the input voltage, and when the external voltage slightly varies, the fluctuation of the power-on timing sequence of the product is easily caused, and further the external detection device (such as a servo driver) cannot detect the U, V, W signal within the specified time.

Secondly, in order to realize the non-provincial line function, a selection chip (such as SN74HC157) is often added to select an output signal, which requires additional chips on a PCB that is compatible with the non-provincial line encoder, which is not favorable for miniaturization of the encoder.

Therefore, the above problems are further improved.

SUMMERY OF THE UTILITY MODEL

The utility model mainly aims at providing a provincial line formula encoder and processing method thereof, it is through voltage stabilizing circuit and delay circuit, stabilize input voltage at reference voltage to prevent that the change of external voltage from leading to the change of delay time, this reference voltage is also used for guaranteeing the reliable and stable of power-on threshold voltage Va on the provincial line formula encoder simultaneously; the photoelectric cell can also realize the switching between signals generated by the photoelectric cell without adding a chip, can also realize the switching between time delay, waveform output and signals through the single chip microcomputer, realizes the time-sharing gating transmission function of data through resistance isolation, and does not need to additionally add a data selection chip.

The utility model provides a province's line formula encoder, including coding disc and rotation axis, coding disc and rotation axis fixed connection still include:

the voltage stabilizing circuit is used for stabilizing the input voltage at a reference voltage and is electrically connected with the first driving chip U3 through the first delay circuit and the second delay circuit in sequence;

the driving circuit comprises a second driving chip U5, a first element (preferably comprising a resistor network) and a second element (preferably a single chip microcomputer), wherein the second driving chip U5 is electrically connected with the first element or the second element, and the second driving chip U5 is used for outputting a first signal or a second signal generated by the optical cell.

As a further preferable technical solution of the above technical solution, the voltage stabilizing circuit includes a voltage stabilizing chip U1, one path of the 1 pin of the voltage stabilizing chip U1 is connected to the input Voltage (VCC) through a resistor R6 and a resistor R7 in sequence, two ends of the resistor R7 are connected in parallel to a resistor R4, the other path of the 1 pin of the voltage stabilizing chip U1 is electrically connected to the 3 pin, the 2 pin of the voltage stabilizing chip U1 is connected to the reference Voltage (VREF) through a connection end of the resistor R6 and the resistor R7, and the connection end of the resistor R6 and the resistor R7 is also grounded through a capacitor C10;

the voltage stabilizing circuit further comprises a resistor R2, a resistor R3, a resistor R22, a resistor R24, a resistor R15 and a resistor R16, wherein the reference voltage VREF _3.0V is grounded through the resistor R2 and the resistor R3 in sequence, the common connection end of the resistor R2 and the resistor R3 outputs the reference voltage VREF _2.573V, the reference voltage VREF _3.0V is grounded through the resistor R22 and the resistor R24 in sequence, the common connection end of the resistor R22 and the resistor R24 outputs the reference voltage VREF _1V, the reference voltage VREF _3.0V is grounded through the resistor R15 and the resistor R16 in sequence, and the common connection end of the resistor R15 and the resistor R16 outputs the reference voltage VREF _ 2.573V.

As a further preferable technical solution of the above technical solution, the first delay circuit includes a first comparator U6-B, a 7 pin of the first comparator U6-B is connected to a reference voltage through a resistor R28, a resistor R27 is connected in series between the 7 pin and a 5 pin of the first comparator U6-B, and a 6 pin of the first comparator U6-B is connected to ground through a capacitor C9;

the second delay circuit comprises a second comparator U2-B and a third comparator U2-A, wherein a pin 6 of the second comparator U2-B is electrically connected with a pin 7 of the first comparator U6-B, the pin 7 of the first comparator U6-B outputs a first level WKUP, the pin 7 of the second comparator U2-B is connected with a reference voltage through a resistor R41, the pin 7 of the second comparator U2-B is electrically connected with a pin 2 of the third comparator U2-A through a resistor R23, the pin 7 of the second comparator U2-B outputs a second level WKIP1, the pin 2 of the third comparator U2-A is also grounded through a capacitor C17, a resistor R39 is connected between a pin 3 and a pin 1 of the third comparator U2-A in series, and the pin 1 of the third comparator U2-A outputs a third level EN through a resistor R50, and the pin 1 of the third comparator U3536-A is also connected with a reference voltage through a resistor U52R 2-A.

As a further preferable technical solution of the above technical solution, one path of the 1 pin of the first driving chip U3 is connected to the signal U1, the other path of the 1 pin of the first driving chip U3 is connected to the signal a1 "through the resistor R31, two ends of the resistor R31 are connected in parallel to the resistor R32, one path of the 7 pin of the first driving chip U3 is connected to the signal V1, the other path of the 7 pin of the first driving chip U3 is connected to the signal B1" through the resistor R42, two ends of the resistor R42 are connected in parallel to the resistor R43, one path of the 9 pin of the first driving chip U3 is connected to the signal W1, one path of the 9 pin of the first driving chip U3 is connected to the signal Z1 through the resistor R44, and two ends of the resistor R44 are connected in.

As a further preferable embodiment of the above technical solution, the pin 1 of the second driver chip U5 is connected to the signal U, the pin of the second driver chip U5 is connected to the third level EN, the pin 7 of the second driver chip U5 is connected to the signal W, the pin 9 of the second driver chip U5 is connected to the signal V, and one path of the pin 16 of the second driver chip U5 is connected to the ground through the capacitor C41 and the other path of the pin 16 is connected to the input voltage.

Drawings

Fig. 1 is a schematic structural diagram of the wire-saving encoder of the present invention.

Fig. 2 is a signal switching diagram (setting ABZ by UVW) of the present invention.

Fig. 3 is a signal switching diagram (UVW set by ABZ) of the present invention.

Fig. 4 is a single chip microcomputer control signal switching diagram of the wire-saving encoder of the present invention.

Fig. 5 is a voltage stabilizing circuit diagram of the wire-saving encoder of the present invention.

Fig. 6 is a first delay circuit and a second delay circuit of the wire-saving encoder of the present invention.

Fig. 7 is a first driving chip of the wire-saving encoder and a peripheral circuit diagram thereof.

Fig. 8 is a second driving chip of the wire-saving encoder and its peripheral circuit diagram.

Fig. 9 is a timing diagram of the power-up of the wire-saving encoder of the present invention.

Detailed Description

The following description is presented to disclose the invention so as to enable any person skilled in the art to practice the invention. The preferred embodiments in the following description are given by way of example only, and other obvious variations will occur to those skilled in the art. The basic principles of the invention, as defined in the following description, may be applied to other embodiments, variations, modifications, equivalents and other technical solutions without departing from the spirit and scope of the invention.

Referring to fig. 1 of the drawings, fig. 1 is a schematic view of a wire-saving encoder structure of the wire-saving encoder of the present invention, FIG. 2 is a signal switching diagram of the guyed encoder of the present invention (ABZ set by UVW), FIG. 3 is a signal switching diagram of the guyed encoder of the present invention (UVW set by ABZ), FIG. 4 is a diagram of switching control signals of a single chip microcomputer of the wire-saving encoder of the present invention, FIG. 5 is a diagram of a voltage stabilizing circuit of the wire-saving encoder of the present invention, FIG. 6 is a diagram of a first delay circuit and a second delay circuit of the wire-saving encoder of the present invention, fig. 7 is the first driver chip of the wire-saving encoder and its peripheral circuit diagram of the present invention, fig. 8 is the second driver chip of the wire-saving encoder and its peripheral circuit diagram of the present invention, and fig. 9 is the upper electric timing diagram of the wire-saving encoder of the present invention.

In the preferred embodiment of the present invention, it should be noted by those skilled in the art that the input voltage, the encoder disk, the rotation shaft, and the like according to the present invention can be regarded as the prior art.

PREFERRED EMBODIMENTS

The utility model also discloses a economize line formula encoder, including coding disc and rotation axis, coding disc and rotation axis fixed connection still include:

the voltage stabilizing circuit is used for stabilizing the input voltage at a reference voltage (preventing the delay time from changing due to the change of the external input voltage, and meanwhile, the reference voltage is also used for guaranteeing the stability and the reliability of the power-on threshold voltage Va of the wire-saving encoder) and the voltage stabilizing circuit is electrically connected with the first driving chip sequentially through the first delay circuit and the second delay circuit (the voltage stabilizing circuit enables the RC charging delay time not to be changed due to the change of the external voltage);

Preferably, one path of the photocell is electrically connected to the first driver chip U3 (for inputting a signal), the other path of the photocell is electrically connected to the second driver chip U5 (for inputting another signal) through a resistor network, and the first delay circuit is electrically connected to the second driver chip U5.

Specifically, the voltage stabilizing circuit comprises a voltage stabilizing chip U1, one path of a1 pin of the voltage stabilizing chip U1 is connected with an input Voltage (VCC) through a resistor R6 and a resistor R7 in sequence, two ends of the resistor R7 are connected with a resistor R4 in parallel, the other path of the 1 pin of the voltage stabilizing chip U1 is electrically connected with a 3 pin, a 2 pin of the voltage stabilizing chip U1 is connected with a reference Voltage (VREF) through a common connection end of the resistor R6 and the resistor R7, and the common connection end of the resistor R6 and the resistor R7 is grounded through a capacitor C10;

More specifically, the first delay circuit comprises a first comparator U6-B, wherein a 7 pin of the first comparator U6-B is connected with a reference voltage through a resistor R28, a resistor R27 is connected between the 7 pin and a 5 pin of the first comparator U6-B in series, and a 6 pin of the first comparator U6-B is connected with the ground through a capacitor C9;

Furthermore, a1 pin of the first driving chip U3 is connected with the signal U1, another 1 pin of the first driving chip U3 is connected with the signal a1 through the resistor R31, two ends of the resistor R31 are connected with the resistor R32 in parallel, a 7 pin of the first driving chip U3 is connected with the signal V1 in parallel, another 7 pin of the first driving chip U3 is connected with the signal B1 through the resistor R42 in parallel, two ends of the resistor R42 are connected with the resistor R43 in parallel, a 9 pin of the first driving chip U3 is connected with the signal W1 in parallel, a 9 pin of the first driving chip U3 is connected with the signal Z1 through the resistor R44 in parallel, and two ends of the resistor R44 are connected with the resistor R45 in parallel.

Furthermore, the pin 1 of the second driver chip U5 is connected to the signal U, the pin of the second driver chip U5 is connected to the third level EN, the pin 7 of the second driver chip U5 is connected to the signal W, the pin 9 of the second driver chip U5 is connected to the signal V, one path of the pin 16 of the second driver chip U5 is connected to the ground through the capacitor C41, and the other path of the pin 16 is connected to the input voltage.

Preferably, the first driver chip U3 and the second driver chip U5 can input any signal generated by the photocell.

Preferably, signal A +, signal A-and signal A1-are each different forms of signal A, and so on.

Preferably, as shown in fig. 2, the photocell inputs the signal (UVW) to the first driver chip, the photocell inputs the signal (ABZ) to the second driver chip through the resistor network, the first driver chip sends the processed signal (U + V + W +) to the second driver chip, and the second driver chip can output the signal (UVW) and the signal (ABZ) to realize signal switching, and the operating principle thereof is as follows: the method comprises the following steps of inputting A, B and Z three-way signals generated by a photocell (when light irradiates the photocell through a grating, the photocell can generate U, V, W, A, B and Z six-way signals) into a second driving chip through a resistor network, inputting U, V and W three-way signals generated by the photocell into a first driving chip, and inputting U +, V + and W + three-way signals generated after U, V and W three-way signals pass through the first driving chip into the second driving chip; in a first time (Td) when the power of the wire-saving encoder reaches a threshold voltage and a second time (Ta) when the power of the wire-saving encoder reaches the threshold voltage, the second driving chip keeps outputting a high-resistance state, is set by the first driving chip after the second time is finished, and outputs U, V and W signals; after the third time (Tb) is kept, the first driving chip keeps outputting the high impedance state, and the second driving chip outputs A, B and the three-way signal Z, so that the switching of the three-way signal A, B and the three-way signal Z, U, V and the three-way signal W is realized.

Preferably, as shown in fig. 3, the photocell inputs the signal (ABZ) to the first driver chip, the photocell inputs the signal (UVW) to the second driver chip through the resistor network, the first driver chip sends the processed signal (a + B + Z +) to the second driver chip, and the second driver chip can output the signal (UVW) and the signal (ABZ), so as to implement signal switching, where the operating principle is as follows: the method comprises the following steps of inputting U, V and W three-way signals generated by a photocell (when light irradiates the photocell through a grating, the photocell can generate U, V, W, A, B and Z six-way signals) into a second driving chip through a resistor network, inputting A, B and Z three-way signals generated by the photocell into a first driving chip, and inputting A +, B + and Z + three-way signals generated after A, B and Z three-way signals pass through the first driving chip into the second driving chip; in a first time (Td) when the power of the wire-saving encoder reaches a threshold voltage and a second time (Ta) when the power of the wire-saving encoder reaches the threshold voltage, the second driving chip keeps outputting a high-resistance state, is set by the first driving chip after the second time is finished, and outputs U, V and W signals; after the third time (Tb) is kept, the first driving chip keeps outputting the high impedance state, and the second driving chip outputs A, B and the three-way signal Z, so that the switching of the three-way signal A, B and the three-way signal Z, U, V and the three-way signal W is realized.

Preferably, as shown in fig. 4, the photocell inputs a signal (UVW) to the single chip microcomputer, the photocell inputs a signal (ABZ) to the second driving chip through the resistor network, the single chip microcomputer sends a processed signal (U + V + W +) to the second driving chip, and the second driving chip can output the signal (UVW) and the signal (ABZ) to realize signal switching, and the working principle is as follows: a, B and Z signals generated by the photocell are input into a second driving chip through a resistor network, U, V and W signals generated by the photocell are input into a single chip microcomputer, U +, V + and W + signals generated after U, V and W signals pass through the single chip microcomputer are input into the second driving chip, an enabling end of the second driving chip is controlled by the single chip microcomputer, the second driving chip enters a high-impedance state to reach a time point t2, and no signal is output; at a time point t3-t4, the single chip microcomputer controls the second driving chip to enter a normal output state and outputs three signals of U, V and W; after the time point t4, the single chip microcomputer stops outputting the three signals U +, V +, and W +, maintains the high impedance state, outputs the A, B and Z three signals, and implements switching of the A, B and Z three signals and the U, V and W three signals (thus implementing a time-sharing gating transmission function of data through resistance isolation without additionally adding a data selection chip).

It should be mentioned that the technical features such as input voltage, code disc and rotation axis that the utility model discloses the patent application relates to should be regarded as prior art, and the concrete structure of these technical features, theory of operation and the control mode that may involve, spatial arrangement mode adopt the conventional selection in this field can, should not regard as the invention point of the utility model to be in, the utility model discloses a do not do further specifically expand the detailed description.

It will be apparent to those skilled in the art that modifications and variations can be made in the above-described embodiments, or some features of the invention may be substituted or omitted, and any modification, substitution, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.

Claims

1. The utility model provides a province's line formula encoder, includes coding disc and rotation axis, coding disc and rotation axis fixed connection, its characterized in that still includes:

the second driving chip U5, the first element and the second element, the second driving chip U5 is electrically connected to the first element or the second element, and the second driving chip U5 is used for outputting a first signal or a second signal generated by the optical cell.

2. The wire-saving encoder as claimed in claim 1, wherein the voltage regulator circuit comprises a voltage regulator chip U1, wherein one path of the 1 pin of the voltage regulator chip U1 is connected to the input voltage sequentially through a resistor R6 and a resistor R7, two ends of the resistor R7 are connected in parallel to a resistor R4, the other path of the 1 pin of the voltage regulator chip U1 is electrically connected to the 3 pin, the 2 pin of the voltage regulator chip U1 is connected to the reference voltage through the common connection end of the resistor R6 and the resistor R7, and the common connection end of the resistor R6 and the resistor R7 is also connected to the ground through a capacitor C10;

3. The province line type encoder as claimed in claim 2, wherein the first delay circuit comprises a first comparator U6-B, a 7-pin of the first comparator U6-B is connected with a reference voltage through a resistor R28, a resistor R27 is connected in series between the 7-pin and a 5-pin of the first comparator U6-B, a 6-pin of the first comparator U6-B is connected with the ground through a capacitor C9;

4. The wire-saving encoder as claimed in claim 3, wherein a pin 1 of the first driver chip U3 is connected to a signal U1, a pin 1 of the first driver chip U3 is connected to a signal A1 via a resistor R31, two ends of a resistor R31 are connected in parallel to a resistor R32, a pin 7 of the first driver chip U3 is connected to a signal V1, a pin 7 of the first driver chip U3 is connected to a signal B1 via a resistor R42, two ends of the resistor R42 are connected in parallel to a resistor R43, a pin 9 of the first driver chip U3 is connected to a signal W1, a pin 9 of the first driver chip U3 is connected to a signal Z1 via a resistor R44, and two ends of a resistor R44 are connected in parallel to a resistor R45.

5. The provincial line type encoder as claimed in claim 4, wherein the pin 1 of the second driver chip U5 is connected to the signal U, the pin of the second driver chip U5 is connected to the third level EN, the pin 7 of the second driver chip U5 is connected to the signal W, the pin 9 of the second driver chip U5 is connected to the signal V, and the pin 16 of the second driver chip U5 is connected to the ground through the capacitor C41 in one path and is connected to the input voltage in the other path.