CN213367655U - Phase-cut power supply control circuit and wall switch power supply device - Google Patents

Abstract

The utility model discloses a cut looks supply control circuit and wall switch power supply unit. The phase-cut power supply control circuit includes: the device comprises a first main power device, a second main power device and a control module; the control module is configured to output a driving signal for controlling the first and second main power devices to be turned on when the voltage of the first end of the first main power device or the voltage of the first end of the second main power device is greater than or equal to a first threshold voltage, and output a driving signal for controlling the first and second main power devices to be turned off after a preset on-time, so as to output a direct current at the output end of the output control circuit. The utility model discloses a drive double power device switches on simultaneously, turn-offs simultaneously, can realize the phase-cut control to the input alternating current, realizes converting the alternating current from the commercial power into the direct current.

Description

Phase-cut power supply control circuit and wall switch power supply device

Technical Field

The utility model relates to an electronic circuit technical field especially relates to a phase-cut power supply control circuit and wall switch power supply unit.

Background

Wall switches (In-wall switches), also called control panels, are widely used In various fields and are largely present In various devices to provide input interfaces for controlling various devices or lighting fixtures. With the development of the demand of electrical appliances and the trend of home intelligence, the intelligent control panel has gradually replaced the traditional control panel.

For an intelligent control panel, an intelligent module needs to be arranged in the panel to provide the function of intelligent control. The power required by the intelligent module involves a technique of converting ac power of the commercial power into dc power. At present, a switching power supply is generally used for converting alternating current into direct current; this mode needs to use a plurality of devices such as rectifier, inductance, and the scheme is complicated, and components and parts account for bulky, with high costs.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a phase cut power supply control circuit and wall switch power supply unit to the technical problem who exists among the prior art, can realize phase cut DC supply.

In order to achieve the above object, the utility model provides a phase-cut power supply control circuit, phase-cut power supply control circuit includes: a first main power device, a first end of which is coupled to a first input end of alternating current through a load and is coupled to an output end of the output control circuit through a first conducting element, a second end of which is electrically connected to a reference ground, and a control end of which is used for receiving a driving signal; a second main power device, a first end of which is electrically connected to a second input end of the alternating current and is coupled to the output end of the output control circuit through a second conducting element, a second end of which is electrically connected to a reference ground, and a control end of which receives the same driving signal as the control end of the first main power device; the control module is configured to output a driving signal for controlling the first main power device and the second main power device to be turned on when the voltage of the first end of the first main power device is greater than or equal to a first threshold voltage or when the voltage of the first end of the second main power device is greater than or equal to the first threshold voltage, and output a driving signal for controlling the first main power device and the second main power device to be turned off after a preset on-time, so that direct current is output at an output end of the output control circuit.

In order to achieve the above object, the present invention further provides a wall switch power supply device, which includes an output control circuit, and further includes a phase-cut power supply control circuit for receiving alternating current, wherein the phase-cut power supply control circuit is coupled to an output end of the output control circuit through a first conduction element and coupled to an output end of the output control circuit through a second conduction element; wherein cut looks power supply control circuit and adopt the utility model discloses a cut looks power supply control circuit.

The utility model has the advantages that: the utility model discloses a drive double-power device switches on simultaneously, turn-offs simultaneously, can realize the phase-cut control to the input alternating current, and then at output control circuit's output direct current, realizes changing into the direct current from the alternating current of commercial power. Further, the utility model discloses can realize the opening time of automatically regulated main power device through the preset on-time in the configuration control module. And the implementation scheme of the embodiment is simple and easy to implement, the required components are fewer and can be integrated, and the cost can be effectively reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.

Fig. 1 is a schematic structural diagram of an embodiment of a wall switch power supply device according to the present invention;

fig. 2 is a circuit connection diagram of an embodiment of the wall switch power supply device of the present invention;

fig. 3 is a schematic diagram of an operation waveform of the wall switch power supply device shown in fig. 2.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It is to be understood that the embodiments described are only some embodiments of the invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without any creative work belong to the protection scope of the present invention. The terms "first," "second," "third," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the objects so described are interchangeable under appropriate circumstances. Furthermore, the terms "comprises," "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.

In the description of the present invention, it is to be noted that the terms "connected" and "connected" are to be interpreted broadly unless otherwise explicitly defined or limited. For example, the components may be electrically connected or in communication with each other, directly or indirectly through intervening media, or may be in communication within or interacting with each other. It will be understood that when an element is referred to as being "coupled" to another element, there are intervening elements present. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.

Referring to fig. 1, a schematic diagram of an embodiment of a wall switch power supply device according to the present invention is shown. The wall switch power supply device includes: a phase-cut power supply control circuit 10, an output control circuit 18, a first conduction element 11, and a second conduction element 12. The phase-cut power supply control circuit 10 includes: a first main power device 101, a second main power device 102, and a control module 103.

The first main power device 101 has a first terminal coupled to a first input terminal N of the alternating current AC through the load 19 and coupled to the output terminal of the output control circuit 18 through the first pass element 11, and a second terminal electrically connected to the reference ground, and a control terminal for receiving the driving signal G0. The first main power device 101 may be a MOS transistor, preferably an NMOS transistor, but may also be another type of switching transistor, such as a triode, a thyristor, a switching transistor formed by connecting a plurality of the aforementioned transistors, and the like. The voltage direction between the output terminal of the output control circuit 18 and the first terminal of the first main power device 101 can be controlled by the first pass element 11, so that voltage can be output from the first terminal of the first main power device 101 to the output terminal of the output control circuit 18 only; the first conducting element 11 may be a diode or a switching tube.

The second main power device 102 has a first terminal electrically connected to the second input terminal L of the alternating current AC and coupled to the output terminal of the output control circuit 18 through the second pass element 12, a second terminal electrically connected to the reference ground, and a control terminal receiving the same driving signal, i.e., the driving signal G0, as the control terminal of the first main power device 101. The second main power device 102 may be a MOS transistor, preferably an NMOS transistor, but may also be another type of switching transistor, such as a triode, a thyristor, a switching transistor formed by connecting a plurality of the aforementioned transistors, and the like. The voltage direction between the output of the output control circuit 18 and the first end of the second main power device 102 can be controlled by the second pass element 12, so that voltage can be output only from the first end of the second main power device 102 to the output of the output control circuit 18; the second conducting element 12 may be a diode or a switching tube.

The control module 103 is configured to output a driving signal G0 for controlling the first main power device 101 and the second main power device 102 to be turned on when a voltage Vfb of the first terminal of the first main power device 101 is greater than or equal to a first threshold voltage Vref1 or when a voltage of the first terminal of the second main power device 102 is greater than or equal to the first threshold voltage Vref1, and output a driving signal G0 for controlling the first main power device 101 and the second main power device 102 to be turned off after a preset on-time, so as to output a direct current Vout (i.e., a direct current power output) at an output terminal of the output control circuit 18.

In a further embodiment, the phase-cut power supply control circuit 10 further includes: a third pass device 104 and a fourth pass device 105. An input terminal of the control module 103 is coupled to the first terminal of the first main power device 101 through the third conducting element 104 and coupled to the first terminal of the second main power device 102 through the fourth conducting element 105, and an output terminal of the control module 103 is electrically connected to the control terminal of the first main power device 101 and the control terminal of the second main power device 102. The voltage profile between the alternating current AC and the control module 103 can be controlled by the third and fourth conductive elements 104, 105, so that voltage can only be output from the alternating current AC to the input of the control module 103. The third conducting element 104 and the third conducting element 105 may be diodes or switching tubes.

In a further embodiment, the phase-cut power supply control circuit 10 further includes: a low voltage power supply module 106. The low voltage power supply module 106 is configured to provide an operating voltage VDD and at least a threshold voltage (e.g., the first threshold voltage Vref1) to the control module 103.

The embodiment can realize phase-cut control on input alternating current by driving the double-power device to be simultaneously switched on and switched off, and further output direct current at the output end of the output control circuit, so that alternating current of commercial power is converted into direct current. Furthermore, the on-time of the main power device can be automatically adjusted by configuring the preset on-time in the control module. And the implementation scheme of the embodiment is simple and easy to implement, the required components are fewer and can be integrated, and the cost can be effectively reduced.

Referring to fig. 1-3, fig. 2 is a circuit connection diagram of an embodiment of the wall switch power supply device of the present invention, and fig. 3 is a schematic diagram of an operating waveform of the wall switch power supply device shown in fig. 2.

As shown in fig. 2, in this embodiment, the first main power device 101 employs a first NMOS transistor M1, the second main power device 102 employs a second NMOS transistor M2, the output control circuit 18 employs an output capacitor C1, the first conducting element 11 employs a first diode D1, the second conducting element 12 employs a second diode D2, the third conducting element 104 employs a third diode D3, and the third conducting element 105 employs a fourth diode D4. The control module 103 includes: a first comparison unit 231, a logic control unit 232, and a driving unit 233.

Specifically, the drain terminal of the first NMOS transistor M1 is electrically connected to the load 19, and further coupled to the first input terminal N of the alternating current AC through the load 19, and the drain terminal thereof is electrically connected to the anode of the first diode D1, the source terminal thereof is electrically connected to the reference ground, and the gate terminal thereof is used for receiving the driving signal G0. The cathode of the first diode D1 is electrically connected to the output of the output control circuit 18. Preferably, a first body diode DM1 is connected between the source and drain terminals of the first NMOS transistor M1, so as to perform an isolation function when the first NMOS transistor M1 operates normally. The drain terminal of the first NMOS transistor M1 is further electrically connected to the anode of the third diode D3, and the cathode of the third diode D3 is electrically connected to the input terminal of the control module 103. The first plate of the output capacitor C1 is electrically connected to the output of the output control circuit 18, and the second plate of the output capacitor C1 is electrically connected to ground.

Specifically, the drain terminal of the second NMOS transistor M2 is electrically connected to the second input terminal L of the alternating current AC, the source terminal thereof is electrically connected to the ground, and the gate terminal thereof is used for receiving the driving signal G0. Preferably, a second body diode DM2 is connected between the source and drain of the first NMOS transistor M1, so as to perform an isolation function when the second NMOS transistor M2 operates normally. The drain terminal of the second NMOS transistor M2 is further electrically connected to the anode of the fourth diode D4, and the cathode of the fourth diode D4 is electrically connected to the input terminal of the control module 103.

The first comparing unit 231 is configured to compare the Drain terminal voltage Drain1 of the first NMOS transistor M1 or the Drain terminal voltage Drain2 of the second NMOS transistor M2 with the first threshold voltage Vref1, and invert the comparison result when the Drain terminal voltage Drain1 of the first NMOS transistor M1 or the Drain terminal voltage Drain2 of the second NMOS transistor M2 is greater than or equal to the first threshold voltage Vref1, so as to output a first trigger pulse voutk. Specifically, the first comparison unit 231 employs a first comparator CMP 1; a forward input terminal of the first comparator CMP1 is coupled to the drain terminal of the first NMOS transistor M1 through the third diode D3 and coupled to the drain terminal of the second NMOS transistor M2 through the fourth diode D4, so as to receive a node voltage Vfb (i.e., a voltage output from the drain terminal of the first NMOS transistor M1 after passing through the third diode D3 or a voltage output from the drain terminal of the second NMOS transistor M2 after passing through the fourth diode D4); the negative input of the first comparator CMP1 receives the first threshold voltage Vref 1. When the absolute value of the voltage of the alternating current AC is gradually increased, the Drain terminal voltage Drain1 of the first NMOS transistor M1 increases as the voltage of the alternating current AC increases, or the Drain terminal voltage Drain2 of the second NMOS transistor M2 increases as the voltage of the alternating current AC increases; when the voltage difference between the voltage Drain1 and the output voltage Vout at the output terminal of the output control circuit 18 is higher than the turn-on voltage of the first diode D1, or the voltage difference between the voltage Drain2 and the output voltage Vout at the output terminal of the output control circuit 18 is higher than the turn-on voltage of the second diode D2, the output capacitor C1 starts to charge and the output voltage Vout gradually increases; when the output voltage Vout reaches a set target value (accordingly, the node voltage Vfb reaches the first threshold voltage Vref1), the first comparator CMP1 starts inverting, outputting a first trigger pulse VOUTOK; so that the first trigger pulse voutrip is output during both the positive and negative half cycles of the alternating current AC.

The logic control unit 232 is electrically connected to the first comparing unit 231; the logic control unit 232 is configured to output a control signal G1 with a first level according to the first trigger pulse vouttok, start timing, and output a control signal G1 with a second level after the timing time reaches the preset on-time. In this embodiment, the first level is a high level and the second level is a low level. The timing time determines the time when the first and second NMOS transistors M1, M2 are in the on state, and when the timing is over, the first and second NMOS transistors M1, M2 are turned off.

In a further embodiment, the preset on-time (i.e. the timing time) is configured as follows: ton is Tgrid/2-Toff1, where Tgrid is the grid cycle time of the last cycle of the alternating current AC, and Toff1 is the voltage rise time of the current cycle; specifically, the voltage rise time of the present cycle is a time when the voltage of the first terminal of the first NMOS transistor M1 or the voltage of the first terminal of the second NMOS transistor M2 rises from 0 to equal to the first threshold voltage Vref 1.

The driving unit 233 is coupled to the logic control unit 232; the driving unit 233 is configured to output a driving signal G0 for controlling the first NMOS transistor M1 and the second NMOS transistor M2 to be turned on according to a first level of a control signal G1; according to the control signal G1 with the second level, a driving signal G0 is outputted to control the first NMOS transistor M1 and the second NMOS transistor M2 to be turned off. Namely, the first and second NMOS transistors M1 and M2 are turned on and off at the same time, thereby realizing phase-cut control of the input AC.

In a further embodiment, the control module 103 further comprises: a zero-crossing detection unit 234. The zero-crossing detection unit 234 is configured to output a second trigger pulse ZXC when the alternating current AC passes a zero position; the logic control unit 232 is further electrically connected to the zero-crossing detection unit 234, and configured to configure the preset conduction time according to an interval time between two adjacent second trigger pulses ZXC of a previous cycle. Specifically, the preset on-time (i.e. the timing time) is configured as follows: ton is Tgrid/2-Toff1, where Tgrid/2 is the interval time between two adjacent second trigger pulses ZXC in the previous cycle (i.e. the grid cycle time of the first cycle of the alternating current AC), and Toff1 is the voltage rise time in the current cycle; specifically, the voltage rise time of the present cycle is a time when the voltage of the first terminal of the first NMOS transistor M1 or the voltage of the first terminal of the second NMOS transistor M2 rises from 0 to equal to the first threshold voltage Vref 1.

Optionally, in this embodiment, the zero-crossing detection unit 234 is a second comparison unit; the second comparing unit is configured to compare the voltage at the first end of the first main power device 101 or the voltage at the first end of the second main power device 102 with a second threshold voltage Vref2, and invert the voltage at the first end of the first main power device 101 or the voltage at the first end of the second main power device 102 when the voltage is equal to the second threshold voltage Vref2, so as to output the second trigger pulse ZXC, thereby providing a time reference for configuring the timing time for the logic control unit 232. Specifically, the second comparing unit employs a second comparator CMP 2; a forward input terminal of the second comparator CMP2 is coupled to the drain terminal of the first NMOS transistor M1 through the third diode D3 and coupled to the drain terminal of the second NMOS transistor M2 through the fourth diode D4, so as to receive a node voltage Vfb (i.e., a voltage output from the drain terminal of the first NMOS transistor M1 after passing through the third diode D3 or a voltage output from the drain terminal of the second NMOS transistor M2 after passing through the fourth diode D4); the negative input of the second comparator CMP2 receives the second threshold voltage Vref 2. When the alternating current AC passes through the zero, the second comparator CMP2 inverts to output the second trigger pulse ZXC.

In a further embodiment, the control module 103 further comprises: a delay unit 235. The delay unit 235 is electrically connected between the logic control unit 232 and the driving unit 233, and is configured to delay a falling edge of the control signal G1. Specifically, the delay unit 235 delays the falling edge of the control signal G1 by a preset delay time Δ T and then outputs GATEON to the driving unit 233, so as to prevent the first and second NMOS transistors M1, M2 from being turned off before the AC zero crossing point.

In a further embodiment, the phase-cut power supply control circuit 10 further includes: a low voltage power supply module 106; the low voltage power module 106 is configured to provide an operating voltage VDD and at least one threshold voltage (e.g., the first threshold voltage Vref1, and the first threshold voltage Vref2) to the control module 103. In this embodiment, the low voltage power supply module 106 employs a low dropout regulator (LDO), which can have a very low dropout voltage.

The phase-cut power supply control circuit of the present invention is further explained with reference to fig. 2 and 3.

In the positive half cycle of the alternating current AC, comprising a phase 0-t1 and a phase t2-t 3:

stage 0-t 1: when the voltage of the alternating current AC passes through the zero point of the positive half cycle, the second comparator CMP2 reversely outputs the second trigger pulse ZXC to the logic control unit 232; the driving unit 233 outputs a low-level driving signal G0, and the first and second NMOS transistors M1 and M2 are in an off state. The voltage of the alternating current AC gradually increases from the zero point, and the voltage Drain1 of the Drain terminal of the first NMOS transistor M1 increases as the voltage of the alternating current AC increases. When the voltage difference between the voltage Drain1 and the output voltage Vout is higher than the turn-on voltage of the first diode D1, the output capacitor C1 starts to charge, and the output voltage Vout gradually increases; when the output voltage Vout reaches a set target value (accordingly, the node voltage Vfb reaches the first threshold voltage Vref1), the first comparator CMP1 starts to reversely output the first trigger pulse voutoo; the logic control unit 232 outputs a high-level control signal G1 according to the first trigger pulse vouteok, and further controls the first and second NMOS transistors M1 and M2 to be turned on.

Stage t1-t 2: after the first and second NMOS transistors M1 and M2 are turned on, the voltage Drain1 becomes low, and the first diode D1 is reverse biased to be in an off state, thereby preventing the output voltage Vout from discharging to the Drain of the first NMOS transistor M1. After the first and second NMOS transistors M1 and M2 are turned on, the current of the load 19 flows through the first and second NMOS transistors M1 and M2. The logic control unit 232 starts to time internally after receiving the first trigger pulse voutek, and the time for timing determines the time when the first NMOS transistor M1 and the second NMOS transistor M2 are in the on state; after the timing is finished, the low-level control signal G1 for turning off the first and second NMOS transistors M1 and M2 is output at time t 2.

The configured timing time is as follows: ton ═ Tgrid/2-Toff 1. Wherein Tgrid/2 is the interval time between two adjacent second trigger pulses ZXC of the previous cycle (i.e. the grid cycle time of the last negative half cycle of the alternating current AC), and Toff1 is the time for the first terminal of the first NMOS transistor M1 to rise from 0 to equal to the first threshold voltage Vref1 (i.e. the time for the phase control signal G1 to be at the low level in 0-t 1) of the present cycle.

The logic control unit 232 outputs the control signal G1 of low level after receiving the second trigger pulse ZXC again. In order to avoid the early turning off of the first and second NMOS transistors M1 and M2 by the driving signal G0 at time T2, the falling edge of the control signal G1 is delayed by Δ T by the delay unit 235, and then GATEON is output, so that the low level of the driving signal G0 output by the driving unit 233 is delayed by Δ T relative to the low level of the control signal G1.

In the negative half cycle of the alternating current AC, including the stages t2-t3 and t3-t4, the working principle is similar to that of the positive half cycle of the alternating current AC:

stage t2-t 3: when the voltage of the alternating current AC passes through the negative half-cycle zero point, the second comparator CMP2 reversely outputs the second trigger pulse ZXC to the logic control unit 232; after a time delay Δ T relative to time T2, the driving unit 233 outputs a low-level driving signal G0, and the first and second NMOS transistors M1 and M2 are in an off state. The absolute value of the voltage of the alternating current AC gradually increases from the zero point, and the voltage Drain2 of the Drain terminal of the second NMOS transistor M2 increases as the absolute value of the voltage of the alternating current AC increases. When the voltage difference between the voltage Drain2 and the output voltage Vout is higher than the turn-on voltage of the second diode D2, the output capacitor C1 starts to charge, and the output voltage Vout gradually increases; when the output voltage Vout reaches a set target value (accordingly, the node voltage Vfb reaches the first threshold voltage Vref1), the first comparator CMP1 starts to reversely output the first trigger pulse voutoo; the logic control unit 232 outputs a high-level control signal G1 according to the first trigger pulse vouteok, and further controls the first and second NMOS transistors M1 and M2 to be turned on.

Stage t3-t 4: after the first and second NMOS transistors M1 and M2 are turned on, the voltage Drain2 becomes low, and the second diode D2 is reverse biased to be in an off state, thereby preventing the output voltage Vout from discharging to the Drain of the second NMOS transistor M2. After the first and second NMOS transistors M1 and M2 are turned on, the current of the load 19 flows through the first and second NMOS transistors M1 and M2. The logic control unit 232 starts to time internally after receiving the first trigger pulse voutek, and the time for timing determines the time when the first NMOS transistor M1 and the second NMOS transistor M2 are in the on state; after the timing is finished, outputting a low-level control signal G1 for turning off the first NMOS tube M1 and the second NMOS tube M2 at the time t 4; and then enters the next period.

The timing pattern is consistent with the alternating current AC positive half cycle. Specifically, the configuration timing time is as follows: ton ═ Tgrid/2-Toff 1. Wherein Tgrid/2 is the interval time between two adjacent second trigger pulses ZXC of the previous cycle (i.e. the grid cycle time of the last positive half cycle of the alternating current AC), and Toff1 is the time for the voltage at the first end of the second NMOS transistor M2 of the present cycle to rise from 0 to equal to the first threshold voltage Vref1 (i.e. the time for the phase control signal G1 to be at the low level in the t2-t 3). Specifically, the logic control unit 232 outputs the control signal G1 of low level after receiving the second trigger pulse ZXC again. In order to avoid the early turning off of the first and second NMOS transistors M1 and M2 by the driving signal G0 at time T4, the falling edge of the control signal G1 is delayed by Δ T by the delay unit 235, and then GATEON is output, so that the low level of the driving signal G0 output by the driving unit 233 is delayed by Δ T relative to the low level of the control signal G1.

The embodiment can realize phase-cut control on input alternating current by driving the double-power device to be simultaneously switched on and switched off, and further output direct current at the output end of the output control circuit, so that alternating current of commercial power is converted into direct current. Furthermore, the on-time of the main power device can be automatically adjusted by configuring the preset on-time in the control module. And the implementation scheme of the embodiment is simple and easy to implement, the required components are fewer and can be integrated, and the cost can be effectively reduced.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations should also be regarded as the protection scope of the present invention.

Claims (10)

1. A phase-cut power supply control circuit, comprising:

a first main power device, a first end of which is coupled to a first input end of alternating current through a load and is coupled to an output end of the output control circuit through a first conducting element, a second end of which is electrically connected to a reference ground, and a control end of which is used for receiving a driving signal;

a second main power device, a first end of which is electrically connected to a second input end of the alternating current and is coupled to the output end of the output control circuit through a second conducting element, a second end of which is electrically connected to a reference ground, and a control end of which receives the same driving signal as the control end of the first main power device;

the control module is configured to output a driving signal for controlling the first main power device and the second main power device to be turned on when the voltage of the first end of the first main power device is greater than or equal to a first threshold voltage or when the voltage of the first end of the second main power device is greater than or equal to the first threshold voltage, and output a driving signal for controlling the first main power device and the second main power device to be turned off after a preset on-time, so that direct current is output at an output end of the output control circuit.

2. The phase-cut power supply control circuit of claim 1, wherein the control module comprises:

a first comparing unit, configured to compare a voltage of the first end of the first main power device or a voltage of the first end of the second main power device with the first threshold voltage, and invert when the voltage of the first end of the first main power device or the voltage of the first end of the second main power device is greater than or equal to the first threshold voltage, so as to output a first trigger pulse;

the logic control unit is electrically connected with the first comparison unit and used for outputting a control signal of a first level according to the first trigger pulse, starting timing and outputting a control signal of a second level after the timing time reaches the preset conduction time; and the driving unit is coupled to the logic control unit and used for outputting a driving signal for controlling the first main power device and the second main power device to be switched on according to a control signal of a first level and outputting a driving signal for controlling the first main power device and the second main power device to be switched off according to a control signal of a second level.

3. The phase-cut power supply control circuit of claim 2, wherein the control module further comprises:

a zero-crossing detection unit configured to output a second trigger pulse when the alternating current passes through a zero position;

the logic control unit is further electrically connected with the zero-crossing detection unit and is used for configuring the preset conduction time according to the interval time of two adjacent second trigger pulses in the previous period.

4. The phase-cut power supply control circuit according to claim 3, wherein the zero-cross detection unit is a second comparison unit; the second comparing unit is configured to compare a voltage of the first end of the first main power device or a voltage of the first end of the second main power device with a second threshold voltage, and invert the comparison to output the second trigger pulse when the voltage of the first end of the first main power device or the voltage of the first end of the second main power device is equal to the second threshold voltage.

5. The phase-cut power supply control circuit according to claim 3 or 4, wherein the preset conduction time is a difference between an interval time of two adjacent second trigger pulses in a previous period and a voltage rise time in the present period; the voltage rise time of the present period is a time for the voltage of the first terminal of the first main power device or the voltage of the first terminal of the second main power device to rise from 0 to be equal to the first threshold voltage in the present period.

6. The phase-cut power supply control circuit of claim 2, wherein the control module further comprises:

and the delay unit is electrically connected between the logic control unit and the driving unit and is used for delaying the falling edge of the control signal.

7. The phase-cut power supply control circuit of claim 1,

the phase-cut power supply control circuit further comprises: a third conductive element and a fourth conductive element;

the input end of the control module is coupled to the first end of the first main power device through the third conducting element and coupled to the first end of the second main power device through the fourth conducting element, and the output end of the control module is electrically connected to the control end of the first main power device and the control end of the second main power device.

8. The phase-cut power supply control circuit of claim 1, further comprising: a low voltage power supply module; the low voltage power supply module is configured to provide an operating voltage and at least a threshold voltage to the control module.

9. The phase-cut power supply control circuit of claim 1, wherein the first main power device and the second main power device are NMOS transistors.

10. A wall switch power supply device comprises an output control circuit and is characterized by further comprising a phase-cut power supply control circuit for receiving alternating current, wherein the phase-cut power supply control circuit is coupled to the output end of the output control circuit through a first conducting element and coupled to the output end of the output control circuit through a second conducting element; the phase-cut power supply control circuit is applied to the phase-cut power supply control circuit according to any one of claims 1 to 9, so that direct current is output at the output end of the output control circuit according to the alternating current.

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