CN213342165U - On-chip resonator based on broadside coupling distributed capacitor - Google Patents
On-chip resonator based on broadside coupling distributed capacitor Download PDFInfo
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- CN213342165U CN213342165U CN202022104818.1U CN202022104818U CN213342165U CN 213342165 U CN213342165 U CN 213342165U CN 202022104818 U CN202022104818 U CN 202022104818U CN 213342165 U CN213342165 U CN 213342165U
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Abstract
The utility model discloses an on-chip syntonizer based on broadside coupling distributing type condenser. The input end of the resonator is connected with one end of the transmission line, and the output end of the resonator is connected with the other end of the transmission line; the distributed capacitor is in a broadside coupling structure and is realized by using three metal layers TM2, TM1 and M5 on the top of a preset metal layer, and resonance can be generated at any given frequency by changing the physical size of the distributed capacitor; the metal shielding is symmetrically distributed on two sides of the distributed capacitor and the transmission line in a metal layer stacking mode, and the distributed capacitor and the transmission line are used for energy transmission in a coupling mode.
Description
Technical Field
The utility model relates to a syntonizer technical field particularly, relates to an on-chip syntonizer based on broadside coupling distributing type condenser.
Background
From the filter to the coupler, the resonator is probably one of the most basic components of all passive devices. In general, resonators may be implemented using distributed or lumped methods. In a micro-on-chip passive device operating at microwave frequencies, the concentration of components is preferred. However, the distributed element method also has some significant features, particularly the increase of the operating frequency to the millimeter wave region. Both thin film microstrip transmission line (TFMS) structures and coplanar waveguide (CPW) structures have been applied to resonators. Coplanar waveguide (CPW) based structures are preferred due to their great potential for circuit miniaturization. Based on this, it becomes particularly meaningful and challenging to improve coplanar waveguide resonators.
SUMMERY OF THE UTILITY MODEL
The present invention aims at least solving one of the technical problems existing in the prior art or the related art.
To this end, the present invention aims to propose an on-chip resonator based on broadside-coupled distributed capacitors.
In order to achieve the above object, the present novel technical solution provides an on-chip resonator based on broadside-coupled distributed capacitor, which is formed by patterning a preset layer metal layer, where the preset layer metal layer includes: the metal layer TM2, the metal layer TM1, the metal layer M5, the metal layer M4, the metal layer M3, the metal layer M2, the metal layer M1 and the silicon substrate layer positioned at the bottom are sequentially arranged; silicon dioxide layers are arranged between the metal layer TM2 and the metal layer TM1, between the metal layer TM1 and the metal layer M5, between the metal layer M5 and the metal layer M4, between the metal layer M4 and the metal layer M3, between the metal layer M3 and the metal layer M2 and between the metal layer M2 and the metal layer M1; the metal layer TM1, the metal layer M5, and the silicon dioxide layer therebetween constitute a metal-insulator-metal layer MIM,
the resonator includes: the antenna comprises a transmission line, a distributed capacitor and a metal shielding layer, wherein the metal shielding layer is distributed on a metal layer TM2, a metal layer TM1, a metal layer M5, a metal layer M4, a metal layer M3, a metal layer M2 and a metal layer M1, and the metal shielding layer is in a symmetrical structure by taking the transmission line as a symmetry axis;
the input end of the resonator is connected with one end of the transmission line, and the output end of the resonator is connected with the other end of the transmission line; the distributed capacitor adopts a broadside coupling structure, and three metal layers on the top of a preset metal layer are used: a metal layer TM2, a metal layer TM1 and a metal layer M5; two wide sides are respectively arranged on the metal shielding layers on the metal layer TM2, the metal layer TM1 and the metal layer M5, the positions of the three wide sides correspond to each other to form a wide side coupling structure of the distributed capacitor, each wide side is divided into an upper part and a lower part by taking the transmission line as a symmetry axis, and the distributed capacitor and the transmission line carry out energy transmission in a coupling mode.
Furthermore, the transmission line is formed by carving a preset metal layer with a topmost metal layer TM 2.
Furthermore, the topmost layer of the metal shielding layer with a side opening is carved on the upper side and the lower side of the metal layer TM2 by taking the transmission line as a symmetrical line, the upper part and the lower part of the topmost layer of the metal shielding layer are not connected, the openings on the two sides correspond to each other, and a wide edge is arranged at each opening to serve as one layer of the distributed capacitor.
Further, the other layers of the metal shielding layer except the topmost layer are all in a continuous box structure.
Further, the two broadsides in two adjacent layers of the distributed capacitor have the same physical size and opposite directions, and the metal layer TM2 has the same physical size and same direction as the two broadsides in the metal layer M5; the same physical dimensions as the broadside in metal layer TM1, in the opposite direction.
Further, the width b of the transmission line is 10 μm, and the length a is 176 μm;
the length of the wide side is 138 mu m, the width of the wide side is 12 mu m, the opening distance L1 between the free end of the wide side and the metal shielding layer is 22 mu m, and the distance W1 between the wide side and the side parallel to the metal shielding layer is 48 mu m
Furthermore, the width W2 of the ring of the upper half of the metal shielding layer is 8 μm, the bottom layer of the metal shielding layer is grounded, the width W3 is 68 μm, and the length L2 is 176 μm.
The utility model has the advantages that:
the utility model discloses the syntonizer can be through changing the physical dimension of distributing capacitor, can produce the resonance on arbitrary given frequency, and uses the value of condenser to adjust simply through selecting different metal levels, and can not show the area that increases this wave filter. The utility model adopts 0.13 μm (Bi) -CMOS process, which can generate resonance at 47 GHz. Chip size was only 0.176X 0.149mm except for the patch2。
Additional aspects and advantages of the invention will be set forth in the description which follows, or may be learned by practice of the invention.
Drawings
Fig. 1 shows a structural diagram of an on-chip resonator based on a broadside-coupled distributed capacitor according to the present invention;
FIG. 2 shows a schematic diagram of a preset layer structure of an on-chip resonator based on a broadside-coupled distributed capacitor;
fig. 3 shows a schematic diagram of a layer of a preset-layer metal TM2 of an on-chip resonator based on a broadside-coupled distributed capacitor;
fig. 4 shows a schematic diagram of a layer of a preset-layer metal TM1 of an on-chip resonator based on a broadside-coupled distributed capacitor;
fig. 5 shows a schematic diagram of a layer of a preset-layer metal M5 of an on-chip resonator based on a broadside-coupled distributed capacitor;
FIG. 6 shows a simplified LC equivalent circuit model schematic for designing the novel broadside-coupled distributed capacitor-based on-chip resonator;
FIG. 7 shows a transformed LC equivalent circuit model schematic for designing the novel broadside-coupled distributed capacitor-based on-chip resonator;
FIG. 8 is a graph showing the results of EM simulations using different values of C1' in FIG. 7;
figure 9 shows the result of a comparison between the structure shown in figure 1 and the simplified LC equivalent circuit model shown in figure 2 based on broadside coupled distributed capacitors;
fig. 10 shows the effect of different values of L and W on the resonant frequency in fig. 3-5.
Fig. 11 shows a graph comparing the EM simulation results of the structure of fig. 1 with the actual test results of the resonator.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention more clearly understood, the present invention will be described in further detail with reference to the accompanying drawings and detailed description. It should be noted that the embodiments and features of the embodiments of the present application may be combined with each other without conflict.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those specifically described herein, and therefore the scope of the present invention is not limited to the specific embodiments disclosed below.
Referring to fig. 2, a schematic diagram of the preset metal layers used in the on-chip resonator based on the broadside-coupled distributed capacitor is shown. The method comprises the following steps: the metal layer TM2, the metal layer TM1, the metal layer M5, the metal layer M4, the metal layer M3, the metal layer M2, the metal layer M1 and the silicon substrate layer positioned at the bottom are sequentially arranged; silicon dioxide layers are arranged between the metal layer TM2 and the metal layer TM1, between the metal layer TM1 and the metal layer M5, between the metal layer M5 and the metal layer M4, between the metal layer M4 and the metal layer M3, between the metal layer M3 and the metal layer M2 and between the metal layer M2 and the metal layer M1; the metal layer TM1, the metal layer M5, and the silicon dioxide layer therebetween constitute a metal-insulator-metal layer MIM. The metal layer TM2, the metal layer TM1, the metal layer M5 and the metal layer M2 are all aluminum metal layers. The thickness of the metal layer TM2 is 3 μm; the thickness of the metal layer TM1 is 2 μm; the metal layer M5, the metal layer M4, the metal layer M3 and the metal layer M2 are all 0.45 mu M; the thickness of the metal layer M1 is 0.4 μ M; the thickness of the silicon substrate layer is 200 μm; the distance between the lower surface of the metal layer TM2 and the upper surface of the metal layer TM1 is 2.8 μm; the distance between the lower surface of the metal layer TM1 and the upper surface of the metal layer M2 is 4 μ M; and the distance between the lower surface of the metal layer M2 and the upper surface of the silicon substrate layer is 2.07 μ M. The pre-set layer structure of the present invention is designed and implemented in standard 0.13-mum (Bi) -CMOS technology.
Fig. 1 shows a structural schematic diagram of an on-chip resonator based on a broadside-coupled distributed capacitor of the present invention. Furthermore, the on-chip resonator based on the broadside coupling distributed capacitor is formed by carving a preset metal layer,
the resonator includes: the antenna comprises a transmission line 4, a distributed capacitor and a metal shielding layer 2, wherein the metal shielding layer 2 is distributed on a metal layer TM2, a metal layer TM1, a metal layer M5, a metal layer M4, a metal layer M3, a metal layer M2 and a metal layer M1, and the metal shielding layer 2 is in a symmetrical structure by taking the transmission line 4 as a symmetry axis;
the resonator input end 1 is connected with one end of the transmission line 4, and the resonator output end 5 is connected with the other end of the transmission line 4; the distributed capacitor adopts a broadside coupling structure, and three metal layers on the top of a preset metal layer are used: a metal layer TM2, a metal layer TM1 and a metal layer M5; two wide sides 3 are respectively arranged on the metal shielding layers on the metal layer TM2, the metal layer TM1 and the metal layer M5, the positions of the three wide sides 3 correspond to each other to form a wide side coupling structure of the distributed capacitor, each wide side is divided into an upper part and a lower part by taking the transmission line as a symmetry axis, and the distributed capacitor and the transmission line carry out energy transmission in a coupling mode.
Referring to fig. 3, the transmission line is characterized by using a predetermined metal layer, a topmost metal layer TM 2.
The topmost layer of the metal shielding layer with a side opening is carved on the upper side and the lower side of the metal layer TM2 by taking a transmission line as a symmetrical line, the upper part and the lower part of the topmost layer of the metal shielding layer are not connected, the openings on the two sides correspond to each other, and a wide edge is arranged at the opening on each side to serve as one layer of the distributed capacitor.
Referring to fig. 4 and 5, the metal shielding layer is a continuous block structure except for the top layer.
The physical sizes of two wide sides in two adjacent layers of the distributed capacitor are the same, the directions are opposite, and the physical sizes of the metal layer TM2 and the two wide sides in the metal layer M5 are the same, and the directions are the same; the same physical dimensions as the broadside in metal layer TM1, in the opposite direction.
The width of the transmission line is 10 μm, and the length of the transmission line is 176 μm;
the length of the wide side is 138 mu m, the width of the wide side is 12 mu m, the opening distance L1 between the free end of the wide side and the metal shielding layer is 22 mu m, and the distance W1 between the wide side and the side parallel to the metal shielding layer is 48 mu m
The width W2 of the upper half of the metal shielding layer is 8 μm, the bottom layer of the metal shielding layer is grounded, the width W3 is 68 μm, and the length L2 is 176 μm.
In this embodiment, a broadside coupling structure is used to build the required distributed capacitance. And the value of the capacitor can be simply adjusted by selecting different metal layers without adding extra area.
Fig. 3-5 show schematic diagrams of preset layer metal layer TM2, metal layer TM1 and metal layer M5 of the novel broadside-coupled distributed capacitor-based on-chip resonator. For clarity, a layer diagram of preset layer metal layers TM2, TM1, and M5 is shown, where TM2 includes a transmission line, two opposite broadsides for forming a distributed capacitor, and a metal shield implemented with a stack of metal layers. The metal layer TM1 and the metal layer M5 layers include two broadsides for forming a distributed capacitor and a metal shield implemented with a stack of metal layers. By contrast, it can be clearly demonstrated that the physical dimensions of the broadsides of each layer are the same, and the directions are opposite, and the physical dimensions of the two broadsides of the metal layer TM2 and the metal layer M5 are the same, and the directions are the same and opposite to the physical dimensions of the two broadsides of the metal layer TM 1.
Fig. 6 and 7 show simplified LC equivalent circuit model diagrams and further transformed LC equivalent circuit diagrams for designing the novel broadside-coupled distributed capacitor-based on-chip resonator. The LC equivalent circuit diagram of the novel broadside-coupled distributed capacitor-based on-chip resonator is presented for a full understanding of the resonator. Therein, the distributed capacitance is modeled as an LC network with L1 and C1 in parallel. The transmission line was modeled as a lossless pi-network containing L2 and C2, with distributed capacitance and transmission line carrying energy transfer by way of coupling. After further transformation and appropriate analysis, the following relationship can be obtained
From the above formula, by changing the values of C1 ', C1, L1, and L1', the resonance frequency can be effectively controlled. In practice, it is necessary to first determine the value of the inductance according to a given physical dimension. The position of the resonance frequency can be effectively controlled by using the capacitance value.
As shown in fig. 8, a graph of the results of EM simulation using different values of C1' in fig. 7 is shown; to verify the correctness of the above analysis, the frequency response of the model shown in fig. 7 is shown in fig. 8. It can be seen that by varying the value of C1', the resonant frequency can be effectively tuned.
Fig. 9 is a comparison result of S21 parameters of the simplified LC lumped model and the EM electromagnetic simulation shown in fig. 6 and 7 and fig. 10 is a comparison result of S11 parameters of the simplified LC lumped model and the EM electromagnetic simulation shown in fig. 6 and 7. To demonstrate the effectiveness of the simplified LC equivalent circuit model for analysis. Reasonable consistency is obtained between the two responses except for the loss effect of the electromagnetic structure which is not considered by the LC equivalent circuit model.
Fig. 10 shows the effect of different values of L and W on the resonant frequency in fig. 3-5. The use of distributed capacitors of different widths and lengths all contribute to the resonant frequency and can be used to fine tune the resonant frequency. As shown in FIG. 10(a), the resonance frequency was shifted from 44GHz to 50.5GHz, while the value of L was changed from 158 μm to 138 μm in steps of 10 μm, and the value of W was fixed at 4 μm. Furthermore, as shown in graph (b), the operating frequency of the illustrated structure also shifted from 44 to 50.5GHz, while the value of W was swept from 4 to 20 μm in 4 μm steps, with the value of L fixed at 138 μm.
As shown in FIG. 11, the measurement was carried out using a G-S-G probe, a Keysight vector network analyzer E8361A and N5260-60003, and the measurement range was from 1GHz to 67 GHz. Calibration on the wafer is accomplished by using a conventional short slot to move the reference plane from the connector of the device to the tip of the rf probe. For comparison, the electromagnetically simulated and measured resonant cavities | S21| and | S11| of FIG. 6 are plotted. As shown in fig. 11, the simulated resonance frequency was about 50GHz with attenuation exceeding 15.5dB, while the measured resonance frequency was 47GHz with attenuation exceeding 12 dB. The result shows that the electromagnetic simulation result of the resonant cavity is well matched with the actual measurement result.
The electromagnetic simulation result is different from the actual measurement result for two reasons. One is that the G-S-G pad layer is not included in the electromagnetic simulation, which may introduce additional losses and parasitic capacitance. Another reason is that wafer calibration cannot eliminate errors caused by G-S-G shims because the measurements use an off-the-shelf calibration kit. Figure 6 also shows a mold microphotograph of the structure. The die area of the chip, except for the test pads, was 0.176X 0.149mm2。
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. The utility model provides an on-chip syntonizer based on broadside coupling distributed capacitor, adopts and predetermines layer metal level sculpture and form, predetermine the layer metal level and include: the metal layer TM2, the metal layer TM1, the metal layer M5, the metal layer M4, the metal layer M3, the metal layer M2, the metal layer M1 and the silicon substrate layer positioned at the bottom are sequentially arranged; silicon dioxide layers are arranged between the metal layer TM2 and the metal layer TM1, between the metal layer TM1 and the metal layer M5, between the metal layer M5 and the metal layer M4, between the metal layer M4 and the metal layer M3, between the metal layer M3 and the metal layer M2 and between the metal layer M2 and the metal layer M1; the metal layer TM1, the metal layer M5, and the silicon dioxide layer therebetween constitute a metal-insulator-metal layer MIM,
the resonator includes: the antenna comprises a transmission line, a distributed capacitor and a metal shielding layer, wherein the metal shielding layer is distributed on a metal layer TM2, a metal layer TM1, a metal layer M5, a metal layer M4, a metal layer M3, a metal layer M2 and a metal layer M1, and the metal shielding layer is in a symmetrical structure by taking the transmission line as a symmetry axis;
the input end of the resonator is connected with one end of the transmission line, and the output end of the resonator is connected with the other end of the transmission line; the distributed capacitor adopts a broadside coupling structure, and three metal layers on the top of a preset metal layer are used: a metal layer TM2, a metal layer TM1 and a metal layer M5; two wide sides are respectively arranged on the metal shielding layers on the metal layer TM2, the metal layer TM1 and the metal layer M5, the positions of the three wide sides correspond to each other to form a wide side coupling structure of the distributed capacitor, each wide side is divided into an upper part and a lower part by taking the transmission line as a symmetry axis, and the distributed capacitor and the transmission line carry out energy transmission in a coupling mode.
2. The resonator according to claim 1,
the transmission line is formed by carving a TM2 metal layer on the topmost layer of a preset metal layer.
3. The resonator according to claim 1, wherein the topmost metal shielding layer having an opening is formed on the metal layer TM2 on both sides of the transmission line, the topmost metal shielding layer is not connected to the top and bottom portions, the openings on both sides are aligned, and a wide side is provided at the opening on each side as a layer of the distributed capacitor.
4. The resonator of claim 3, wherein the two broadsides of two adjacent layers of distributed capacitance are physically the same size and in opposite directions, and metal layer TM2 is physically the same size and in the same direction as the two broadsides of metal layer M5; the same physical dimensions as the broadside in metal layer TM1, in the opposite direction.
5. The resonator according to claim 3, characterized in that the layers of the metallic shield other than the topmost layer are of continuous box structure.
6. The broadside-coupled distributed capacitor-based on-chip resonator of claim 1,
the width of the transmission line is 10 μm, and the length of the transmission line is 176 μm;
the length of the wide side is 138 mu m, the width of the wide side is 12 mu m, the opening distance L1 between the free end of the wide side and the metal shielding layer is 22 mu m, and the distance W1 between the wide side and the side parallel to the metal shielding layer is 48 mu m.
7. The broadside-coupled distributed capacitor-based on-chip resonator according to claim 1, wherein the ring width W2 ═ 8 μm in the upper half of the metal shielding layer, the bottom layer of the metal shielding layer is grounded, the width W3 ═ 68 μm, and the length L2 ═ 176 μm.
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