CN213342005U

CN213342005U - AC input slow starting circuit for power supply

Info

Publication number: CN213342005U
Application number: CN202022437694.9U
Authority: CN
Inventors: 杨琼
Original assignee: Luoyang Longsheng Technology Co Ltd
Current assignee: Luoyang Longsheng Technology Co Ltd
Priority date: 2020-10-28
Filing date: 2020-10-28
Publication date: 2021-06-01
Anticipated expiration: 2030-10-28

Abstract

The utility model discloses an AC input slow starting circuit for power supply, which comprises an AC input port, a rectifier bridge, an MOS tube, a voltage stabilizing diode, a timer, a first reverse logic optical coupler, a second reverse logic optical coupler and a DC-DC converter, wherein the AC input port is connected with the input end of the rectifier bridge, and the positive output end of the rectifier bridge is connected with the MOS tube and the DC-DC converter; the live wire and the zero wire are connected with the source electrode of the MOS tube through a first resistor and a voltage stabilizing diode which are connected in series, and a first diode and a second diode are respectively connected between the live wire and the first resistor and between the zero wire and the first resistor; the timer is connected with the voltage stabilizing diode, the MOS tube and the first inverse logic optocoupler; the negative input end of the first inverse logic optocoupler is connected with the positive input end of the second inverse logic optocoupler, and the output end of the first inverse logic optocoupler is connected with the DC-DC converter, the timer and the second inverse logic optocoupler; and the positive output end and the negative output end of the second inverse logic optocoupler are respectively connected with the grid and the drain of the MOS tube. The utility model discloses can effectively restrain input impulse current, the power still can normally function under the switching on and shutting down condition repeatedly moreover.

Description

AC input slow starting circuit for power supply

Technical Field

The utility model belongs to the technical field of the power slow start technique and specifically relates to a power is with exchanging input slow start circuit for exchange input requirement input impulse current little and can frequently start the power.

Background

At present, in an ac input switching power supply, at the moment of power supply energization, due to the influence of a capacitive load in an input loop, a capacitor at an input end is short-circuited at the moment of power supply energization, so that a large impact current is generated. The impact current is far higher than the current value of power supply of a power supply, so that the power supply system is damaged, and the phenomena of tripping when the power supply system is opened and fuses, and the like can be caused; and when the power supply system is powered on again after power supply interruption, the power supply system cannot be frequently turned on and off due to the fact that the input end capacitor cannot be rapidly discharged, and even when the power supply system is frequently turned on and off, the power supply is damaged, and even the input source is damaged.

Disclosure of Invention

In order to solve the above problem, the utility model aims at providing an ac input delays starting circuit for power, the condition of the unable normal work fast of system when its impulse current that can effectively restrain the power and produce when starting up and the switch-on and switch-off repeatedly effectively protects the inside device of power and input source, improves the reliability of power and the safety of protection input electric wire netting.

In order to achieve the purpose, the utility model adopts the following technical scheme:

an alternating current input slow start circuit for a power supply comprises an alternating current input port, a rectifier bridge BD1, an MOS tube M1, a voltage stabilizing diode ZD1, a timer N1, a first reverse logic optical coupler OP1, a second reverse logic optical coupler OP2 and a DC-DC converter N2, wherein a live wire L and a zero wire N of the alternating current input port are respectively connected with an input end of the rectifier bridge BD1, a positive output end of the rectifier bridge BD1 is connected with a grid electrode of the MOS tube M1 through a second resistor R2, the positive output end of the rectifier bridge BD1 is connected with a source electrode of the MOS tube M1 through a first capacitor C1, the positive output end of the rectifier bridge BD 2 is connected with a positive input end of the MOS tube M1, and a third resistor R3 is connected between a drain electrode and a source electrode of the MOS tube M1; the live wire L and the zero wire N are connected with the source electrode of the MOS transistor M1 through a first resistor R1 and a voltage stabilizing diode ZD1 which are connected in series, a second capacitor C2 is connected with the voltage stabilizing diode ZD1 in parallel, a first diode D1 is connected between the live wire L and the first resistor R1, and a second diode D2 is connected between the zero wire N and the first resistor R1; the cathode of the voltage stabilizing diode ZD1 is connected with one end of a first resistor R1, and is connected with a power supply end and a reset end of a timer N1, a fourth capacitor C4 is connected between the reset end and a trigger input end, a fourth resistor R4 is connected between the trigger input end and a ground end, a third capacitor C3 is connected between the ground end and a control voltage end, the ground end is also connected with the source electrode of an MOS (metal oxide semiconductor) transistor M1, a threshold input end is connected with the trigger input end, and an output end is connected with the positive input end of a first anti-logic optical coupler OP1 through a fifth resistor R5; the negative input end of the first inverted logic optical coupler OP1 is connected with the positive input end of the second inverted logic optical coupler OP2, the positive output end is connected with the enable/disable signal end of the DC-DC converter N2, and the negative output end is connected with the grounding end of the timer N1 and the negative input end of the second inverted logic optical coupler OP2 and is connected with the negative input end of the DC-DC converter N2; the positive output end of the second inverse logic optical coupler OP2 is connected with the gate of the MOS transistor M1, and the negative output end is connected with the drain of the MOS transistor M1.

Further, the MOS transistor M1 is an N-channel jfet.

Due to the adoption of the technical scheme, the utility model discloses have following superiority:

the alternating current input slow starting circuit for the power supply has the advantages of simple circuit design, low manufacturing cost, few components, convenience, reliability, strong practicability and wide application range, is suitable for various switching power supplies, ensures that the switching power supplies not only can effectively inhibit input impact current, but also can still normally function under the condition of repeated startup and shutdown, effectively protects the input source and the power supply of the power supply, improves the reliability of the power supply and protects the safety of an input power grid, and has wide application prospect in the field of power supply application.

Drawings

Fig. 1 is a schematic diagram of an ac input slow start circuit for a power supply according to the present invention.

Detailed Description

The technical solution of the present invention will be further described in detail with reference to the accompanying drawings and examples.

As shown IN fig. 1, the ac input slow start circuit for a power supply includes an ac input port, a rectifier bridge BD1, a MOS transistor M1, a zener diode ZD1, a timer N1, a first inverse logic optical coupler OP1, a second inverse logic optical coupler OP2, and a DC-DC converter N2, where a live line L and a null line N of the ac input port are respectively connected to an input end of the rectifier bridge BD1, a positive output end of the rectifier bridge BD1 is connected to a gate of the MOS transistor M1 through a second resistor R2, and is connected to a source of the MOS transistor M1 through a first capacitor C1, and is further connected to a positive input end (+ IN pin) of the DC-DC converter N2, a negative output end is connected to a drain of the MOS transistor M1, and a third resistor R3 is connected between a drain and a source of the MOS transistor M1; the live wire L and the zero wire N are connected with the source electrode of the MOS transistor M1 through a first resistor R1 and a voltage stabilizing diode ZD1 which are connected in series, a second capacitor C2 is connected with the voltage stabilizing diode ZD1 in parallel, a first diode D1 is connected between the live wire L and the first resistor R1, and a second diode D2 is connected between the zero wire N and the first resistor R1; the cathode of the voltage stabilizing diode ZD1 is connected with one end of a first resistor R1, and is connected with a power supply end (VCC) and a RESET end (RESET) of a timer N1, a fourth capacitor C4 is connected between the RESET end (RESET) and a trigger input end (TRIG), the fourth resistor R4 is connected between the trigger input end (TRIG) and a ground end (GND), a third capacitor C3 is connected between the ground end (GND) and a control voltage end (CONT), the ground end (GND) is also connected with the source of an MOS (metal oxide semiconductor) transistor M1), a threshold input end (THRES) is connected with the trigger input end (TRIG), and an output end (OUT) is connected with the positive input end of a first anti-logic optical coupler 1 through a fifth resistor R5; the negative input end of the first inverted logic optical coupler OP1 is connected with the positive input end of the second inverted logic optical coupler OP2, the positive output end is connected with an enable/disable signal end (PC pin) of the DC-DC converter N2, and the negative output end is connected with the ground end (GND) of the timer N1 and the negative input end (IN pin) of the second inverted logic optical coupler OP2 and is connected with the negative input end (-IN pin) of the DC-DC converter N2; the positive output end of the second inverse logic optical coupler OP2 is connected with the gate of the MOS transistor M1, and the negative output end is connected with the drain of the MOS transistor M1.

The full-wave rectification circuit consisting of the alternating current input port and the rectifier bridge BD1 is used by the rear-end DC-DC converter N2, the full-wave rectification circuit consisting of the first diode D1, the second diode D2 and the first resistor R1 converts the alternating current input voltage into a stable input source voltage 12VDC, and supplies the stable input source voltage to the voltage stabilizing diode ZD1 and the timer N1 to work, the 555 delay circuit consisting of the timer N1, the fourth capacitor C4 and the fourth resistor R4 realizes a slow start function, and the control circuit consisting of the MOS transistor M1, the second resistor R2, the third resistor R3, the first reverse logic optical coupling OP1 and the second reverse logic optical coupling OP2 realizes the control of the work of the DC-DC converter N2.

The MOS transistor M1 is an N-channel junction field effect transistor with the model number of FDA50N 50; the models of the first inverted logical optical coupler OP1 and the second inverted logical optical coupler OP2 are both M212; timer N1 was model TLC555 QD; the zener diode ZD1 is of type JBZX49C 12. The types of the components can be replaced according to different specific conditions in the circuit.

The utility model discloses AC input slow start circuit for power, its theory of operation is: after the alternating current voltage of the alternating current input port is rectified by a rectifier bridge BD1, a first capacitor C1 is charged by a third resistor R3 to suppress impact current generated at the moment of power-on, meanwhile, after the alternating current input voltage is subjected to full-wave rectification by a first diode D1 and a second diode D2, a stable working voltage is generated by the first resistor R1 to supply power to a timer N1, and then the alternating current input voltage is subjected to timing work by a timing circuit consisting of the timer N1, the fourth capacitor C4 and a fourth resistor R4, the timing circuit does not count time before, an output end (OUT) of the timer N1 outputs a low level, at the moment, a first inverse logic optical coupler OP1 is conducted with a second inverse logic optical coupler OP2, and an enable/disable signal end (PC pin) of a DC-DC converter N2 is pulled down due to the effect of the first inverse logic optical coupler OP1, so that the operation cannot be performed; meanwhile, the positive and negative output terminals of the second inverted optocoupler OP2 are also at low level, which causes the gate and the drain of the first MOS transistor M1 to be non-conductive at the moment of power-on.

When the time of a timing circuit formed by the timer N1, the fourth capacitor C4 and the fourth resistor R4 is prolonged enough to fully charge the first capacitor C1, the first MOS transistor M1 is triggered by the second inverse logic optocoupler OP2 to be completely conducted, and meanwhile, the DC-DC converter N2 is turned on by the conduction of the first inverse logic optocoupler OP 1.

Due to the existence of the time delay circuit, when the first MOS transistor M1 is turned on, the electricity on the first capacitor C1 is fully charged, so that when the first MOS transistor M1 is turned on, the surge current formed by charging the first capacitor C1 is avoided, and the purpose of protecting the input source is achieved.

The timer N1 is powered by a source generated by full-wave rectification of the first diode D1 and the second diode D2, instead of the first capacitor C1. Because the second capacitor C2 has a small capacity, the power supply of the timer N1 is cut off immediately when the input source is disconnected, and the timing circuit is restarted when the input source is powered on again, so that a large surge current generated by the DC-DC converter N2 and the MOS transistor M1 being in an open state during restarting is avoided, which may cause damage to the MOS transistor M1 and even damage to the input source.

The utility model discloses the principle key point that AC input delays starting circuit for power divide into following two points:

firstly, the time for turning on the MOS transistor M1 must be long enough, that is, the delay time must be long enough; the fourth resistor R4 is selected to have a sufficiently large resistance, and the fourth capacitor C4 is selected to have a small resistance, but the product of the resistance of the fourth resistor R4 and the capacitance of the fourth capacitor C4 is ensured to be sufficiently large.

By the formula time constant τ = RC, we can see that the larger the value of C, R, the slower the charging process for the capacitor and the slower the voltage build-up on the capacitor. Thus we can set τ₁=R₃C₁；τ₂=R₄C₄；

Only when₁Less than τ₂Is generally 5 τ₁≥τ₂Therefore, the on-time of the MOS transistor M1 is long enough, and the effect of no input impact current at the moment of starting up is achieved.

Secondly, after the alternating current input end is full-wave rectified through a first diode D1 and a second diode D2, the timer N1 and the voltage stabilizing diode ZD1 are independently supplied with power, and the rectified 300V is not supplied, namely, the voltage at two ends of a first capacitor C1 is supplied with power, so that after the input source is powered off, because the capacity of a second capacitor C2 is small, the power supply of the timer N1 is immediately cut off at the moment when the input source is disconnected, and when the input source is powered on again, the timing circuit is used for timing again, and the phenomenon that when the input source is restarted, the DC-DC converter N2 and the MOS tube M1 are in an open state, large impact current is generated, so that the input source and the input source of the power source can be repeatedly turned on and.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An AC input slow starting circuit for a power supply is characterized in that: the high-voltage direct-current power supply comprises an alternating-current input port, a rectifier bridge BD1, an MOS tube M1, a voltage-stabilizing diode ZD1, a timer N1, a first reverse logic optical coupler OP1, a second reverse logic optical coupler OP2 and a DC-DC converter N2, wherein a live wire L and a zero wire N of the alternating-current input port are respectively connected with the input end of the rectifier bridge BD1, the positive output end of the rectifier bridge BD1 is connected with the grid of the MOS tube M1 through a second resistor R2, the positive output end of the rectifier bridge BD1 is connected with the source of the MOS tube M1 through a first capacitor C1, the positive output end of the rectifier bridge BD1 is also connected with the positive input end of the DC-DC converter N2, the negative output end of the rectifier bridge BD1 is connected with; the live wire L and the zero wire N are connected with the source electrode of the MOS transistor M1 through a first resistor R1 and a voltage stabilizing diode ZD1 which are connected in series, a second capacitor C2 is connected with the voltage stabilizing diode ZD1 in parallel, a first diode D1 is connected between the live wire L and the first resistor R1, and a second diode D2 is connected between the zero wire N and the first resistor R1; the cathode of the voltage stabilizing diode ZD1 is connected with one end of a first resistor R1, and is connected with a power supply end and a reset end of a timer N1, a fourth capacitor C4 is connected between the reset end and a trigger input end, a fourth resistor R4 is connected between the trigger input end and a ground end, a third capacitor C3 is connected between the ground end and a control voltage end, the ground end is also connected with the source electrode of an MOS (metal oxide semiconductor) transistor M1, a threshold input end is connected with the trigger input end, and an output end is connected with the positive input end of a first anti-logic optical coupler OP1 through a fifth resistor R5; the negative input end of the first inverted logic optical coupler OP1 is connected with the positive input end of the second inverted logic optical coupler OP2, the positive output end is connected with the enable/disable signal end of the DC-DC converter N2, and the negative output end is connected with the grounding end of the timer N1 and the negative input end of the second inverted logic optical coupler OP2 and is connected with the negative input end of the DC-DC converter N2; the positive output end of the second inverse logic optical coupler OP2 is connected with the gate of the MOS transistor M1, and the negative output end is connected with the drain of the MOS transistor M1.

2. The ac input slow start circuit for a power supply according to claim 1, wherein: the MOS transistor M1 is an N-channel junction field effect transistor.