CN213305249U - Airborne DC-DC filtering surge suppression circuit - Google Patents
Airborne DC-DC filtering surge suppression circuit Download PDFInfo
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- CN213305249U CN213305249U CN202022050745.2U CN202022050745U CN213305249U CN 213305249 U CN213305249 U CN 213305249U CN 202022050745 U CN202022050745 U CN 202022050745U CN 213305249 U CN213305249 U CN 213305249U
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Abstract
An airborne DC-DC filtering surge suppression circuit comprises a peak suppression circuit, a filtering suppression circuit, an anti-reverse connection circuit and a surge suppression circuit which are sequentially connected; the peak suppression circuit is used for processing a high-voltage peak from a power bus to obtain a suppressed direct-current voltage; the filtering suppression circuit is used for filtering the suppressed direct-current voltage obtained by the peak suppression circuit; the reverse connection preventing circuit is used for preventing the rear-stage power receiving equipment from being burnt due to the reverse connection input end; the surge suppression circuit is used for carrying out overvoltage surge discharge on the direct-current voltage output by the reverse-connection preventing circuit to obtain a clamping voltage. Through the reasonable setting to component structure, with filter suppression circuit and surge suppression circuit set together, greatly reduced the product occupy the printing board cloth board area, and reduced protection circuit's scale, the utility model discloses measure, can resist multiple external factor interference, interference killing feature is strong, low cost, application prospect are extensive.
Description
Technical Field
The utility model belongs to the technical field of switching power supply, concretely relates to machine carries DC-DC filtering surge suppression circuit.
Background
In an aviation onboard 28V direct-current power supply, GJB181A requires that an electrical load can bear overvoltage surge and undervoltage surge in airplane power supply. In many cases, overvoltage surge occurs during switching of the generator, switching of power supply, load transient, etc., and sudden decrease or sudden increase of load may cause instantaneous increase or decrease of the generator bus voltage, which may generate overvoltage surge. It is known that surge voltage greatly exceeds steady-state power supply voltage, when it attacks electric equipment, it often causes misoperation and equipment damage, possibly causes the whole system to pause, communication to stop, and equipment may be damaged seriously.
Disclosure of Invention
To the above problem, the utility model aims at providing an airborne DC-DC filtering surge suppression circuit, through the reasonable setting to the part structure, with filtering suppression circuit and surge suppression circuit set together, and the filtering suppression circuit function satisfies the requirement in GJB151A, the surge suppression circuit satisfies the requirement in GJB181A, greatly reduced airborne DC-DC filtering surge suppression circuit occupy the printing board cloth board area, and reduced protection circuit's scale, the utility model discloses measure, can resist multiple external factor interference, the interference killing feature is strong, low cost, application prospect are extensive.
In order to achieve the above object, the utility model discloses the technical scheme who takes includes:
an airborne DC-DC filtering surge suppression circuit comprises a peak suppression circuit, a filtering suppression circuit, an anti-reverse connection circuit and a surge suppression circuit which are sequentially connected; the peak suppression circuit is used for processing a high-voltage peak from a power bus to obtain a suppressed direct-current voltage; the filtering suppression circuit is used for filtering the suppressed direct-current voltage obtained by the peak suppression circuit; the reverse connection preventing circuit is used for preventing the rear-stage power receiving equipment from being burnt due to the reverse connection input end; the surge suppression circuit is used for carrying out overvoltage surge discharge on the direct-current voltage output by the reverse-connection preventing circuit to obtain a clamping voltage.
Preferably, the spike suppression circuit comprises a transient suppression diode D1 and a transient suppression diode D2 connected in series; one end of the transient suppression diode D1 is connected with the positive end of the direct current input and the filter suppression circuit, and one end of the transient suppression diode D2 is connected with the negative end of the direct current input and the filter suppression circuit.
Preferably, the filter suppression circuit comprises a capacitor C1, a capacitor CY1, a capacitor CY2, a capacitor C2, a capacitor CY3, a capacitor CY4, a capacitor C3, an inductor L1 and an inductor L2 which are connected;
one end of a capacitor C1 is connected with one end of a capacitor CY1, the A end of an inductor L1 and the spike suppression circuit, the other end of the capacitor C1 is connected with one end of a capacitor CY1, the C end of an inductor L1 and the spike suppression circuit, and the other ends of CY1 and CY2 are connected with the EARTH ground of the shell; one end of a capacitor C2 is connected with the end B of the inductor L1 and one end of the inductor L2, the other end of the capacitor C2 is connected with the end D of the inductor L1, one end of a capacitor C3, one end of a capacitor CY4 and an anti-reverse connection circuit, the other end of the capacitor C3 is connected with the other end of the inductor L2, one end of a capacitor CY3 and the anti-reverse connection circuit, and the other end of the capacitor CY3 and the other end of the capacitor CY4 are connected with the EARTH ground EARTH of the shell.
Preferably, the anti-reverse circuit protects the MOS transistor 1Q1 and the integrated chip 1U1 which are connected in parallel, and further comprises a resistor 1R7 which is connected with the integrated chip 1U1 in series;
a pin 3 of the MOS tube 1Q1 is connected with a filter suppression circuit, a pin 2 SOURCE end of the integrated chip 1U1 and a pin 4 IN end of the integrated chip 1U1, a pin 2 of the MOS tube is connected with a surge suppression circuit and an pin 8 OUT end of the integrated chip 1U1, and a pin 1 of the MOS tube 1 is connected with a pin 1 GATE end of the integrated chip 1U 1; one end of the resistor 1R7 is connected with a 6-pin VSS end of the integrated chip 1U1, and the other end of the resistor 1R7 is connected with the filter suppression circuit and the surge suppression circuit.
Preferably, the surge suppression circuit comprises a resistor 1R1, a resistor 1R2, a resistor 1R3, a resistor 1R4, a resistor 1R5, a resistor 1R6, a resistor 1RS, a capacitor 1C21, a capacitor 1C22, a capacitor 1C24, a capacitor 1C25, a MOS transistor 1Q2 and a chip 1U2 which are connected;
the resistor 1R1, the resistor 1R2 and the resistor 1R3 are sequentially connected in series, one end of the resistor 1R2 is connected with a pin D of the MOS tube 1Q2 and a common end of a pin 2 of the MOS tube in the anti-reverse connection circuit and an 8-pin OUT end of the integrated chip 1U1, a common end of the resistor 1R2 and the resistor 1R1 is connected with a pin 5 VCC end and a pin 6 SHDN end of the chip 1U2, a common end of the resistor 1R2 and the resistor 1R3 is connected with an 8-pin UV end of the chip 1U2, one end of the resistor 1R3 is connected with a pin 7 OV end of the chip 1U2, a pin 9 GND end of the chip 1U2, one end of the capacitor 1C22 and the other end of the resistor 1R7 of the anti-reverse connection circuit, and the other end of the capacitor 1C22 is connected with a pin 12;
a G pin of the MOS tube 1Q2 is connected with one end of a resistor 1R4, the other end of the resistor 1R4 is connected with a 4 pin GATE end of the chip 1U2 and one end of a capacitor 1C21, the other end of the capacitor 1C21 is connected with a network Vo1-, an S pin of the MOS tube 1Q2 is connected with a 3 pin SNS end of the chip 1U2 and one end of a resistor 1RS, and the other end of the resistor 1RS is connected with a 2 pin OUT end of the chip 1U 2;
the resistor 1R5 is connected with the resistor 1R6 in series, the common end of the resistor 1R5 and the resistor 1R6 is connected with the 1 pin FB end of the chip 1U2, one end of the resistor 1R5 is connected with the 2 pin OUT end of the chip 1U2 and one end of the capacitor 1C24, one end of the resistor 1R6 is connected with one end of the capacitor 1C22, the other end of the capacitor 1C24 and the network Vo1-, and the capacitor 1C24 is connected with the capacitor 1C25 in parallel.
Preferably, the chip 1U1 in the anti-reverse connection circuit is of the type LTC4359 chip.
Preferably, the chip 1U2 in the surge suppression circuit is an LTC4363 chip.
Compared with the prior art, the utility model has the advantages that:
the utility model discloses an airborne DC-DC filtering surge suppression circuit, through the reasonable setting to the part structure, with filtering suppression circuit and surge suppression circuit collection together, and the filtering suppression circuit function satisfies the requirement in the rear stage powered device GJB151A, the surge suppression circuit satisfies the requirement in the rear stage powered device GJB181A, greatly reduced airborne DC-DC filtering surge suppression circuit occupy the printing board cloth board area, and reduced protection circuit's scale, the utility model discloses measure, can resist multiple external factor interference, the interference killing feature is strong, low cost, application prospect are extensive.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic circuit diagram of the present invention;
the reference numerals in the figures denote:
1a spike suppression circuit; 2 a filter suppression circuit; 3 anti-reverse connection circuit; 4 surge suppression circuit.
Detailed Description
The present invention will now be described in further detail with reference to the accompanying drawings, which are provided for purposes of illustration and not limitation.
With reference to fig. 1, the utility model provides an airborne DC-DC filtering surge suppression circuit, which comprises a peak suppression circuit 1, a filtering suppression circuit 2, an anti-reverse connection circuit 3 and a surge suppression circuit 4, which are connected in sequence;
the peak suppression circuit 1 is used for processing a high-voltage peak from a power bus, suppressing the peak voltage on the bus in the safe working range of a post-stage circuit, and obtaining a suppressed direct-current voltage;
the filtering suppression circuit 2 is configured to perform filtering processing on the suppressed dc voltage obtained by the peak suppression circuit 1, specifically, perform filtering processing on an interference signal radiated in the front-end dc voltage, so that the post-stage circuit and the powered device operate normally;
the reverse connection preventing circuit 3 is used for preventing the rear-stage power receiving equipment from being burnt due to reverse connection of the input end, so that the rear-stage circuit and the power receiving equipment cannot be burnt due to reverse connection;
the surge suppression circuit 4 is used for performing overvoltage surge discharge on the direct-current voltage output by the reverse connection preventing circuit 3 to obtain a clamping voltage, specifically clamping the surge voltage exceeding the maximum working voltage of the rear-stage power receiving equipment in the direct-current voltage output by the reverse connection preventing circuit 3 into the working voltage range of the rear-stage power receiving equipment, discharging overvoltage surge generated by front-stage transient, and clamping the overvoltage surge voltage into the maximum working range of the rear-stage power receiving equipment, so that the rear-stage module can normally work and cannot be damaged due to overvoltage.
In the present embodiment, the spike suppression circuit 1 includes a transient suppression diode D1 and a transient suppression diode D2 connected in series; one end of the transient suppression diode D1 is connected to the positive terminal of the dc input and the filter suppression circuit 2, and one end of the transient suppression diode D2 is connected to the negative terminal of the dc input and the filter suppression circuit 2.
The transient suppression diode D1 and the transient suppression diode D2 are used to suppress spike voltage of the dc input on the power bus, and input the suppressed dc voltage to the filtering suppression circuit 2.
In this embodiment, the filter suppression circuit 2 includes a capacitor C1, a capacitor CY1, a capacitor CY2, a capacitor C2, a capacitor CY3, a capacitor CY4, a capacitor C3, an inductor L1, and an inductor L2, which are connected;
one end of a capacitor C1 is connected with one end of a capacitor CY1, the A end of an inductor L1 and the spike suppression circuit 1, the other end of the capacitor C1 is connected with one end of a capacitor CY1, the C end of an inductor L1 and the spike suppression circuit 1, and the other end of CY1 and the other end of CY2 are connected with the EARTH ground of the shell; one end of a capacitor C2 is connected with the end B of the inductor L1 and one end of the inductor L2, the other end of the capacitor C2 is connected with the end D of the inductor L1, one end of a capacitor C3, one end of a capacitor CY4 and the anti-reverse connection circuit 3, the other end of the capacitor C3 is connected with the other end of the inductor L2, one end of a capacitor CY3 and the anti-reverse connection circuit 3, and the other end of the capacitor CY3 and the other end of the capacitor CY4 are connected with the EARTH ground of the shell.
The capacitor C1, the capacitor C2 and the capacitor C3 are all differential mode capacitors, and the differential mode capacitors are capacitors connected between lines in parallel and used for filtering differential mode noise. In principle, the larger the differential mode capacitance value is, the better the filtering effect is, and the filtering effect is mainly reflected on low frequency. However, the cost and volume of the capacitor are increased due to the increase of the differential mode capacitance value, and in actual selection, large capacitance cannot be pursued at one step, so that the performance, cost and volume are considered comprehensively, and the differential mode capacitor with higher selective price ratio is required.
The capacitor CY1, the capacitor CY2, the capacitor CY3 and the capacitor CY4 are common mode capacitors, one end of each common mode capacitor is mainly connected to a power line, and the other end of each common mode capacitor is connected to a housing end.
The inductor L1 is a common mode choke coil, and the value of the common mode choke coil is 1.5-5 mH; the most important part of the inductor L1 in the design of the filter is the common mode choke coil, which has a high inductance and is small in size, and is the main tool for suppressing the common mode interference signal. The common mode choke is formed by winding coils with the same number of turns and opposite winding directions on an upper half ring and a lower half ring of a ferrite magnetic ring respectively. An ideal common mode choke attenuates common mode current only and has no effect on the desired differential mode signal or power. However, in actual winding, the upper and lower coils cannot be identical, so that the common mode choke always has some leakage inductance, and thus some attenuation is caused to the differential mode signal. It is also for this reason that the common mode choke can provide both common mode and differential mode filtering. However, the leakage inductance acting on the differential mode cannot be too large, since it would saturate the choke. If the differential mode attenuation is insufficient, the filter is matched with a differential mode filter for use. The common mode choke coil has weak interference signals and works near the initial magnetic conductivity, and the calculation method of the common mode choke coil shows that the improvement of the number of turns of the coil, the initial magnetic conductivity of the magnetic material and the effective sectional area of the magnetic ring is an effective way for improving the inductance value, wherein the improvement of the number of turns is most effective.
The inductor L2 is a differential mode choke coil, the value of the differential mode choke coil is 10-100 eta H, and the differential mode choke coil mainly plays a role in restraining differential mode noise. In the design of an EMI power filter, in order to improve the suppression capability of differential mode noise, a differential mode choke coil and a differential mode capacitor are often used to form an L-type, T-type, ii-type, or other filter circuit. The inductor L2 is connected in series in the filter circuit and has a tiny impedance for low-frequency alternating current signals and a large impedance for high-frequency noise; the biggest difference from the common mode inductor is that the differential mode inductor is directly connected in series with the load and is wound in a single winding structure, unlike the common mode choke in which two identical windings are used on one core. Therefore, when the current passing through the differential mode choke coil is too large, magnetic saturation occurs, and the inductance also decreases, thereby losing the filtering effect.
The filter suppression circuit 2 is used for attenuating frequency signals exceeding the standard, such as distortion and other fluctuations on a power bus and interference signals, and can enable power EMI filtering to meet the requirements of electromagnetic compatibility tests such as electrostatic discharge of CE102, CE107, CS101, CS106, CS114, CS115, CS116, RE102 and RS103 during the electromagnetic compatibility test.
In this embodiment, the anti-reverse connection circuit 3 protects the parallel MOS transistor 1Q1 and the integrated chip 1U1, and further includes a resistor 1R7 connected in series with the integrated chip 1U 1;
a pin 3 of the MOS tube 1Q1 is connected with a filtering suppression circuit 2, a pin 2 SOURCE end of the integrated chip 1U1 and a pin 4 IN end of the integrated chip 1U1, a pin 2 of the MOS tube is connected with a surge suppression circuit 4 and a pin 8 OUT end of the integrated chip 1U1, and a pin of the MOS tube 1 is connected with a pin 1 GATE end of the integrated chip 1U 1; one end of the resistor 1R7 is connected with a 6-pin VSS end of the integrated chip 1U1, and the other end of the resistor 1R7 is connected with the filter suppression circuit 2 and the surge suppression circuit 4.
The integrated chip 1U1 is a reverse connection protection chip, and it functions in that when reverse connection occurs, the MOS transistor 1Q1 is driven to do not work, so that the power supply is protected, and the reverse connection protection is achieved, and the resistor 1R7 is a current-limiting resistor for limiting the magnitude of the current of the branch in which the resistor is located, so as to prevent the series-connected components from being burned out due to excessive current.
The chip 1U1 in the anti-reverse connection circuit is an LTC4359 chip.
Specifically, the surge suppression circuit 4 includes a resistor 1R1, a resistor 1R2, a resistor 1R3, a resistor 1R4, a resistor 1R5, a resistor 1R6, a resistor 1RS, a capacitor 1C21, a capacitor 1C22, a capacitor 1C24, a capacitor 1C25, a MOS transistor 1Q2, and a chip 1U2, which are connected;
the resistor 1R1, the resistor 1R2 and the resistor 1R3 are sequentially connected in series, one end of the resistor 1R2 is connected with a pin D of the MOS tube 1Q2 and a common end of a pin 2 of the MOS tube in the anti-reverse connection circuit 3 and an 8-pin OUT end of the integrated chip 1U1, a common end of the resistor 1R2 and the resistor 1R1 is connected with a pin 5 VCC end and a pin 6 SHDN end of the chip 1U2, a common end of the resistor 1R2 and the resistor 1R3 is connected with an 8-pin UV end of the chip 1U2, one end of the resistor 1R3 is connected with a pin 7 OV end of the chip 1U2, a pin 9 GND end of the chip 1U2, one end of the capacitor 1C22 and the other end of the resistor 1R7 of the anti-reverse connection circuit 3, and the other end of the capacitor 1C22 is connected with a pin;
the resistor R1, the resistor R2 and the resistor R3 form a voltage division network, high input voltage is divided to supply power to a VCC pin of the connection chip 1U2, the connection chip 1U2 chip works normally, 8 pins of the connection chip 1U2 are under-voltage set ends, when the input voltage reaches a required protection value by changing the resistance value of the resistor 1R3, the voltage of UV of the 8 pins of the connection chip 1U2 is equal to or lower than 1.25V, and therefore the circuit achieves under-voltage protection.
The MOS transistor 1Q2 is responsible for suppressing and absorbing voltages beyond the limit voltage when a surge voltage occurs, so as to protect the subsequent electric equipment.
The capacitor 1C22 is a timing protection capacitor, and when the voltage on the capacitor exceeds 1.25V, the module is turned off for protection.
A G pin of the MOS tube 1Q2 is connected with one end of a resistor 1R4, the other end of the resistor 1R4 is connected with a 4 pin GATE end of the chip 1U2 and one end of a capacitor 1C21, the other end of the capacitor 1C21 is connected with a network Vo1-, an S pin of the MOS tube 1Q2 is connected with a 3 pin SNS end of the chip 1U2 and one end of a resistor 1RS, and the other end of the resistor 1RS is connected with a 2 pin OUT end of the chip 1U 2;
the resistor 1R4 is used to suppress the switching speed of the 1Q1MOS transistor and prevent the generation of switching oscillation, and the capacitor 1C21 is used to eliminate the interference on the driving signal.
The resistor 1RS is a current detection resistor, and is mainly used for detecting a current flowing through the power line, and when the current exceeds the protection voltage of the point, the circuit is turned off in time, so that the purpose of protecting the circuit is achieved.
The resistor 1R5 is connected with the resistor 1R6 in series, the common end of the resistor 1R5 and the resistor 1R6 is connected with the 1 pin FB end of the chip 1U2, one end of the resistor 1R5 is connected with the 2 pin OUT end of the chip 1U2 and one end of the capacitor 1C24, one end of the resistor 1R6 is connected with one end of the capacitor 1C22, the other end of the capacitor 1C24 and the network Vo1-, and the capacitor 1C24 is connected with the capacitor 1C25 in parallel.
The resistors 1R5 and 1R6 are used for voltage division, the FB terminal of 1U2 is a voltage feedback terminal and is mainly used for setting a clamping voltage when a surge voltage is generated, and the voltage of the FB terminal is equal to 1.25V by changing the resistance values of the resistors 1R5 and 1R6 so as to set the clamping voltage when the surge voltage is generated.
Wherein, 1C24, 1C25 are energy storage capacitors, are used for storing electric quantity, for the use of back level module.
The model of the chip 1U2 in the surge suppression circuit 4 is LTC 4363.
The specific working principle of the airborne DC-DC filtering surge suppression circuit is as follows:
the peak suppression circuit 1 and the filter suppression circuit 2 play roles in clamping the peak high voltage on the bus and suppressing the conduction and radiation interference on the power bus; the reverse connection preventing circuit 3 plays a role of protecting the safety of the rear-stage circuit and the power receiving equipment when the power supply at the input end is reversely connected; the surge suppression circuit 4 limits the voltage to a specific voltage range.
When on-board equipment is powered on, a power bus is firstly inhibited through the peak inhibiting circuit 1, when voltage on the bus suddenly has high pulse, the transient diode in the peak inhibiting circuit 1 works to clamp the high pulse voltage to the clamping voltage of the transient diode, at this time, a direct current power supply passing through the peak inhibiting circuit 1 enters the filtering inhibiting circuit 2, interference signals on the bus are inhibited through the filtering inhibiting circuit 2, so that fluctuation such as distortion and the like on the power bus and the interference signals are attenuated, over-standard frequency signals are inhibited through the filtering inhibiting circuit 2 to reach a required range, direct current after filtering inhibition passes through the reverse connection preventing circuit, when the power supply is reversely connected, the MOS tube 1Q1 is not conducted, and at this time, the power supply is cut off; when the current flows through the reverse connection prevention circuit in the forward direction, the MOS tube 1Q1 is conducted, and at the moment, the direct current voltage is input into the surge suppression circuit 4; can set up the parameter of clamping voltage through the resistance parameter that sets up resistance 1R5 and resistance 1R6, electric capacity 1C22 sets up the turn-off radiating time of excessive pressure MOS pipe 1Q2, when overvoltage, the voltage of surge suppression circuit 4 rear end is at first clamped at formulating the voltage, rear end system can not receive the harm, and can continue work, along with time growth, MOS pipe 1Q2 can produce certain heat, MOS pipe 1Q2 will be shut off to chip 1U2 afterwards, make MOS pipe 1Q2 dispel the heat in formulating the time, will open MOS pipe 1Q2 afterwards and continue to carry out the voltage clamp, it is normal to supply power until the voltage disappears.
The preferred embodiments of the present disclosure are described in detail with reference to the accompanying drawings, however, the present disclosure is not limited to the specific details of the above embodiments, and various simple modifications may be made to the technical solution of the present disclosure within the technical idea of the present disclosure, and these simple modifications all belong to the protection scope of the present disclosure.
It should be noted that, in the foregoing embodiments, various features described in the above embodiments may be combined in any suitable manner, and in order to avoid unnecessary repetition, various combinations that are possible in the present disclosure are not described again.
Claims (7)
1. An airborne DC-DC filtering surge suppression circuit is characterized by comprising a peak suppression circuit (1), a filtering suppression circuit (2), an anti-reverse connection circuit (3) and a surge suppression circuit (4) which are sequentially connected;
the peak suppression circuit (1) is used for processing a high-voltage peak from a power bus to obtain a suppressed direct-current voltage;
the filtering suppression circuit (2) is used for filtering the suppressed direct-current voltage obtained by the peak suppression circuit (1);
the reverse connection preventing circuit (3) is used for preventing the rear-stage power receiving equipment from being burnt due to a reverse connection input end;
the surge suppression circuit (4) is used for carrying out overvoltage surge discharge on the direct-current voltage output by the reverse connection preventing circuit (3) to obtain a clamping voltage.
2. An on-board DC-DC filtering surge suppression circuit according to claim 1, characterized in that the spike suppression circuit (1) comprises a transient suppression diode D1 and a transient suppression diode D2 in series;
one end of the transient suppression diode D1 is connected with the positive end of the direct current input and the filter suppression circuit (2), and one end of the transient suppression diode D2 is connected with the negative end of the direct current input and the filter suppression circuit (2).
3. An on-board DC-DC filtering surge suppression circuit according to claim 2, characterized in that the filter suppression circuit (2) comprises a capacitor C1, a capacitor CY1, a capacitor CY2, a capacitor C2, a capacitor CY3, a capacitor CY4, a capacitor C3 and an inductor L1, an inductor L2 connected;
one end of the capacitor C1 is connected with one end of the capacitor CY1, the end A of the inductor L1 and the spike suppression circuit (1), the other end of the capacitor C1 is connected with one end of the capacitor CY1, the end C of the inductor L1 and the spike suppression circuit (1), and the other end of the CY1 and the other end of the CY2 are connected with the EARTH ground EARTH of the shell;
the one end of electric capacity C2 is connected the B end of inductance L1 and the one end of inductance L2, and the D end of inductance L1, the one end of electric capacity C3, the one end and the anti-reverse connection circuit (3) of electric capacity CY4 are connected to the electric capacity C2 other end, the other end of electric capacity C3 connection inductance L2, the one end and the anti-reverse connection circuit (3) of electric capacity CY3, the outer shell EARTH EARTH is connected to the other end of electric capacity CY3 and the other end of electric capacity CY 4.
4. An airborne DC-DC filtering surge suppression circuit according to claim 3, characterized in that the anti-reverse connection circuit (3) protects the MOS transistor 1Q1 and the integrated chip 1U1 in parallel, and further comprises a resistor 1R7 in series with the integrated chip 1U 1;
a pin 3 of the MOS tube 1Q1 is connected with a filter suppression circuit (2), a pin 2 SOURCE end of the integrated chip 1U1 and a pin 4 IN end of the integrated chip 1U1, a pin 2 of the MOS tube is connected with a surge suppression circuit (4) and a pin 8 OUT end of the integrated chip 1U1, and a pin 1 of the MOS tube 1 is connected with a pin 1 GATE end of the integrated chip 1U 1;
one end of the resistor 1R7 is connected with a 6-pin VSS end of the integrated chip 1U1, and the other end of the resistor 1R7 is connected with the filter suppression circuit (2) and the surge suppression circuit (4).
5. The airborne DC-DC filtering surge suppression circuit according to claim 4, wherein the surge suppression circuit (4) comprises a resistor 1R1, a resistor 1R2, a resistor 1R3, a resistor 1R4, a resistor 1R5, a resistor 1R6, a resistor 1RS, a capacitor 1C21, a capacitor 1C22, a capacitor 1C24, a capacitor 1C25, a MOS transistor 1Q2 and a chip 1U2 which are connected;
the resistor 1R1, the resistor 1R2 and the resistor 1R3 are sequentially connected in series, one end of the resistor 1R2 is connected with a pin D of the MOS transistor 1Q2 and a common end of a pin 2 of the MOS transistor in the anti-reverse connection circuit (3) and an pin 8 OUT end of the integrated chip 1U1, the common end of the resistor 1R2 and the resistor 1R1 is connected with a pin 5 VCC end and a pin 6 SHDN end of the chip 1U2, the common end of the resistor 1R2 and the resistor 1R3 is connected with a pin 8 UV end of the chip 1U2, one end of the resistor 1R3 is connected with a pin 7 OV end of the chip 1U2, a pin 9 GND end of the chip 1U2, one end of the capacitor 1C22 and the other end of the resistor 1R7 of the anti-reverse connection circuit (3), and the other end of the capacitor 1C22 is connected with a pin 12 TMR end of the;
a G pin of the MOS transistor 1Q2 is connected with one end of a resistor 1R4, the other end of the resistor 1R4 is connected with a 4-pin GATE end of a chip 1U2 and one end of a capacitor 1C21, the other end of the capacitor 1C21 is connected with a network Vo1-, an S pin of the MOS transistor 1Q2 is connected with a 3-pin SNS end of the chip 1U2 and one end of a resistor 1RS, and the other end of the resistor 1RS is connected with a 2-pin OUT end of the chip 1U 2;
the resistor 1R5 and the resistor 1R6 are connected in series, the common end of the resistor 1R5 and the resistor 1R6 is connected with the end FB of the pin 1 of the chip 1U2, one end of the resistor 1R5 is connected with the end OUT of the pin 2 of the chip 1U2 and one end of the capacitor 1C24, one end of the resistor 1R6 is connected with one end of the capacitor 1C22, the other end of the capacitor 1C24 and the network Vo1-, and the capacitor 1C24 and the capacitor 1C25 are connected in parallel.
6. An airborne DC-DC filtering surge suppression circuit according to claim 4, characterized in that the chip 1U1 in the anti-reverse connection circuit (3) is of the type LTC4359 chip.
7. An on-board DC-DC filtering surge suppression circuit according to claim 5, characterized in that the chip 1U2 in the surge suppression circuit (4) is of the type LTC4363 chip.
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| CN115360897A (en) * | 2022-10-20 | 2022-11-18 | 陕西中科天地航空模块有限公司 | Airborne DC-DC filtering current suppression device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114172230A (en) * | 2021-11-02 | 2022-03-11 | 湖北亿咖通科技有限公司 | Circuit system for vehicle-mounted camera |
| CN114726197A (en) * | 2022-02-24 | 2022-07-08 | 华南农业大学 | Novel circulating current restraining structure of three-winding transformer |
| CN115129136A (en) * | 2022-08-30 | 2022-09-30 | 中国电子科技集团公司第十五研究所 | Intelligence machine carries VPX power and computer |
| CN115360897A (en) * | 2022-10-20 | 2022-11-18 | 陕西中科天地航空模块有限公司 | Airborne DC-DC filtering current suppression device |
| CN115360897B (en) * | 2022-10-20 | 2023-02-14 | 陕西中科天地航空模块有限公司 | Airborne DC-DC filtering current suppression device |
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Inventor after: Wang Jiaxue Inventor after: Wang Ke Inventor after: Zhang Chaoyang Inventor after: Xia Mingyu Inventor before: Wang Jiaxue Inventor before: Wang Ke Inventor before: Zhang Chaoyang Inventor before: Xia Mingyu |
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