CN213276321U

CN213276321U - 8-channel analog input module

Info

Publication number: CN213276321U
Application number: CN202022645719.4U
Authority: CN
Inventors: 冯哲彬; 蒋杰; 王维建
Original assignee: SHANGHAI XINHUA CONTROL TECHNOLOGY (GROUP) CO LTD
Current assignee: SHANGHAI XINHUA CONTROL TECHNOLOGY (GROUP) CO LTD
Priority date: 2020-11-16
Filing date: 2020-11-16
Publication date: 2021-05-25
Anticipated expiration: 2030-11-16

Abstract

An 8-channel analog input module comprising: the power supply submodule is used for supplying power to the inside and the outside of the analog input module; the control chip is used for communicating with an upper computer and processing signals; a communication data bus for direct and efficient communication with an external DCS controller; the digital isolation submodule is used for isolating the external power supply circuit and the external input signal from the control chip; the LED indicator light is used for inputting the indication of the result after the signal processing; the ADC is analog-to-digital conversion, and the submodule is used for performing analog-to-digital conversion on an input signal; and the multi-way switch array is used for switching and polling between the ADC submodule and different input channels. The utility model discloses a higher AD sampling chip of accuracy makes the 4-20mA signal of gathering more accurate, and has optimized communication structure, can make and communicate between IO data is direct and the controller, has cancelled corresponding special communication module, makes equipment compact, satisfies on-the-spot needs.

Description

8-channel analog input module

Technical Field

The application relates to the technical field of industrial automation control, in particular to an 8-channel analog quantity input module used under a DCS (distributed control system).

Background

At present, Distributed Control Systems (DCS) have been widely used in the field of automation Control of power, petroleum, chemical industry, steel, paper making, cement, desulfurization, dust removal, water treatment, etc., and the distributed Control systems are a multi-level Computer system composed of a process Control level and a process monitoring level and using a Communication network as a link, and integrate 4C technologies such as Computer (Computer), Communication (Communication), display (CRT) and Control (Control), and the basic idea is distributed Control, centralized operation, hierarchical management, flexible configuration and convenient configuration. In the prior art, the distributed control system mainly has a 3-layer network structure: an Information monitoring network (Information super network) mainly used for data monitoring of a third-party system; a real-time data network in which a Unit Control network (Unit Control net) DCS controller interacts with an upper computer; the real-time data network is characterized in that an IO Control network (IO Control net) inputs and outputs a device signal in situ, enters a DCS special IO module, and communicates with the DCS controller under a special communication module.

Through the structural characteristics of the Distributed Control System (DCS) described above, in the application of a small system, at least two layers of network structures need to be constructed, and a communication data network between an upper computer and local equipment is realized through a controller and a special communication module, so that the concepts of decentralized control and centralized operation are realized. In the application of the small-scale system, the network is too complex, the cost is correspondingly increased, and the use of the existing small-scale control system in the transformation and optimization is not facilitated.

SUMMERY OF THE UTILITY MODEL

In view of the above-mentioned drawbacks of the prior art, the present invention is directed to an analog input module of a compact DCS system, which can measure a 4-20mA standard signal output by a field device without disturbance, thereby meeting the needs of an industrial field.

An 8-channel analog input module comprising:

the power supply submodule is used for supplying power to the inside and the outside of the analog input module;

the control chip is used for communicating with an upper computer and processing signals;

a communication data bus for direct and efficient communication with an external DCS controller;

the digital isolation submodule is used for isolating the external power supply circuit and the external input signal from the control chip;

the LED indicator light is used for inputting the indication of the result after the signal processing;

the multi-way switch array is used for switching polling between the ADC module and different input channels;

an ADC (analog-to-digital conversion) submodule for performing analog-to-digital conversion on an input signal;

the control chip is communicated with the LED indicator lamp and is configured to control the display of the LED indicator lamp;

the control chip is communicated with a communication data bus, the communication data bus is communicated with an external DCS controller, and the control chip is configured to control communication of the communication data bus;

the control chip is communicated with the multi-way switch array through the digital isolation sub-module and the ADC sub-module in sequence, and the control chip is configured to receive input signals which sequentially pass through the multi-way switch array, the ADC sub-module and the digital isolation sub-module;

the other path of the control chip is directly communicated with the multi-way switch array, and the control chip is configured to control the multi-way switch array.

Further, the power supply sub-modules comprise 24VA, 24VB, 24VC and 24 VD; 24VC and 24VD are used for supplying power to possible field devices, and 24VA and 24VB are used for supplying power to the inside of the analog quantity input module after the internal 24V to 5V DCDC direct-current voltage conversion module converts.

And furthermore, the control chip comprises an FPGA chip and an ARM chip.

Further, the ARM chip is in communication with the LED indicator light, the ARM chip being configured to control the LED light.

Further, the ARM chip is communicated with the FPGA and is configured to receive signals from the FPGA and transmit processed signals back to the FPGA.

Further, the FPGA is in communication with the communication data bus, the FPGA being configured to control the communication data bus; the FPGA is directly communicated with the multi-way switch array and is configured to control the channel selection of the multi-way switch array; the FPGA is further communicated with the multi-way switch array sequentially through the digital isolation sub-module and the ADC sub-module, and the FPGA is configured to receive input signals sequentially through the multi-way switch array, the ADC sub-module and the digital isolation sub-module.

Further, the multi-way switch array includes U72 and 8U 53; u72 is configured as a 3-8 decoder and U53 is configured as a relay.

Further, U72 includes 4 input pins CHN _ a1, CHN _ B1, CHN _ C1, and CHN _ D1; the 4 input pins of the U72 are connected with the FPGA and are configured to be controlled by signals output by the FPGA;

further, U72 includes 8 output pins SW2Ch0-Ch7, U72 is configured to select a certain output pin to output low level according to the input CHN _ A1, CHN _ B1, CHN _ C1 signals.

Further, each U53 includes pins xspout +, xspout, AIX +, and AIX-; output pins xSWout +, xSWout are connected to the ADC, and input pins AIX +, AIX-are connected to the external signal source chX; the U53 is configured to turn on one of the corresponding signal sources Ch0-Ch7 to the output pins xspout +, xspout according to the output levels of the output pins SW2Ch0-Ch7 of the U72; wherein X represents a number from 0 to 7.

Compared with the prior art, the beneficial effects of the utility model are as follows:

the AD sampling chip with higher accuracy is adopted, so that the acquired 4-20Ma signals are more accurate, the communication structure is optimized, the IO data can be directly communicated with the controller, a corresponding special communication module is omitted, the equipment is compact, and the field requirement is met.

Drawings

FIG. 1 is a functional block diagram of a channel analog input module according to an embodiment of the present application;

fig. 2 is a schematic block diagram of an analog input module multi-way switch array according to an embodiment of the present application.

Detailed Description

The preferred embodiments of the present application will be described below with reference to the accompanying drawings for clarity and understanding of the technical contents thereof. The present application may be embodied in many different forms of embodiments and the scope of the present application is not limited to only the embodiments set forth herein.

The conception, specific structure and technical effects of the present invention will be further described below to fully understand the objects, features and effects of the present invention, but the present invention is not limited thereto.

An embodiment of the utility model

As shown in fig. 1, the 8-channel analog input module includes the following sub-modules and components:

the power supply sub-module comprises 24VC and 24VD used for supplying power to possible field devices, and 24VA and 24VB used for supplying power to each chip after the internal 24V-to-5V DCDC direct-current voltage conversion module converts;

the control chip comprises an FPGA chip and an ARM chip and is used for communication and signal processing of an upper computer;

the communication data bus is used for realizing direct and effective communication with an external DCS controller through a special 485 chip;

and an ADC (analog-to-digital conversion) submodule for performing analog-to-digital conversion on the input signal.

Wherein:

24VA and 24VB are two external 24V direct current power supply inputs, and are converted into 5V direct current voltage signals through a 24V to 5V DCDC direct current voltage conversion chip, so that power is supplied to control chips (FPGA, ARM) and other logic chips (ADC and the like).

Chn0-Chn7 are external input signals, the standard signals of the signals are 4-20mA current signals, the signals enter the analog front end of an ADC (analog-digital converter) after passing through a multi-way switch array, the ADC samples and quantizes the input signals, and the AD values of the results are converted into corresponding signals through a digital isolation sub-module and then are output to the FPGA. (incidentally: the purpose of digital isolation is to prevent the abnormal short circuit of the external signal from causing impact damage to the internal circuit of the module).

The FPGA transmits the input AD value signal to the ARM chip, the ARM chip performs zero-position full scale calibration processing on the input AD signal, the processed signal is transmitted back to the FPGA, and the FPGA performs communication interaction on the optimized data and the controller through a communication data bus. In addition, the FPGA also assists in controlling a multi-way switch array at the front end, so that the ADC chip performs polling sampling on the input signal.

As shown in fig. 2, the specific structure of the multi-way switch array is as follows:

including U72, U53;

u72 is a 74AHCT138PW logic chip of TI company, U53 is an AC30F relay, the combination of the two realizes a multi-way switch array, wherein 74AHCT138 is A3-8 decoding chip and is controlled by signals output by FPGA, and input pins CHN _ A1, B1 and C1 of the multi-way switch array enable the level of the multi-way switch array to change alternately according to the logic set by FPGA, so that the 74AHCT138PW chip polls and outputs corresponding channels to be low level to control the corresponding relays to attract, thereby enabling the selected input signal channels to be conducted, and realizing the function that the input signals of 8 channels enter ADC sampling in sequence;

in the context of figure 2, it is shown,

CHN _ A1, B1, C1 and D1 are control signals from the FPGA, wherein CHN _ D1 is an enable pin, and CHN _ A1, B1 and C1 are control pins;

SW2Ch0-Ch7 is the output pin, default high, and the selected signal output is low. The U72 outputs the selected channel as the only low level according to the input CHN _ a1, B1, C1 signals.

U53 has two normally open contacts, wherein xsbout +, xsbout-pin is connected to ADC module, AIX +, AIX-pin is external input signal pin corresponding to ChnX (X ═ 0-7), VCC is 5V dc voltage. In practice there are 8 identical U53 circuits.

Taking SW2Ch7 as an example,

if the CHN _ a1, B1 and C1 are all at low level, the SW2Ch7 is selected to be at low level, the U53 relay is electrified, at this time, the

contacts

5 and 6 of the U53 are conducted with the

contacts

7 and 8, xswitch + is communicated with the AI7+, xswitch-is communicated with the AI7-, and then a signal received by the ADC is an input signal of the CHN 7; if the CHN _ AI, B1, C1 are other level type inputs, SW2Ch7 is low and U53 is powered down. The xSWout output selects the input signal according to other conducted relays, and channel polling of ADC sampling input signals can be realized by the method.

The LED indicator light is mainly used for visually displaying the current state of the whole analog input module and the relation between the current state and an external input signal. The LED indicator light module is controlled by the ARM chip. And after the processed AD value is judged in the ARM chip, a control instruction is output, and the state of the LED indicator lamp module is turned over.

In field practice, part of the input signal needs to be supplied with 24VDC to be able to operate. 24VC and 24VD are two power supplies independent of 24VA and 24VB, and the main function of the power supply is to supply 24V direct current power supply to an external system. The module can distribute 24VC and 24VD to 8 channels of Chn0-Chn7 external power supply, and can select a power supply mode or a non-power supply mode for each channel through an external wiring mode. The external power supply module is independent of other internal modules, and if any abnormality occurs in the external power supply system, the internal system of the module cannot be interfered or damaged.

The ARM chip is mainly responsible for processing data after AD sampling and quantization, adopts a 32-bit ARM M0 chip, specifically an M0516 singlechip of Nuvoton company, is programmed by C language, and exchanges data with the FPGA through an external bus. Additionally, the utility model discloses a microprocessor adopts high-speed magnetic medium to keep apart the chip, and it can keep apart the interference of field device to it, guarantees its normal work.

The FPGA adopts LCMXXO 2-2000 chips in MachXO2 series of LATTICE company, and is programmed by using Verilog language. The FPGA mainly completes the data transmission with the ADC and the communication with an upper controller, and in addition, the FPGA also controls a multi-way switch array and performs data interaction with the ARM.

The ADC employs a 16-bit conversion chip ADC 8320E. The analog-to-digital converter has an internal reference, and can quickly and accurately quantize and sample an input signal.

The digital isolation submodule adopts an ADum1200 isolation chip and has the excellent characteristics of low power consumption, small volume, high data transmission rate and high anti-interference performance. In the use process of the utility model, the function for realizing the conversion between the external signal and the internal circuit signal is realized.

An RS485 transceiver of the communication data bus is formed by an ISL81487 chip, has the characteristics of low power consumption and high communication rate, and meets the high-speed real-time data communication requirement between a field input module and a controller under a DCS.

The foregoing detailed description of the preferred embodiments of the present application. It should be understood that numerous modifications and variations can be devised by those skilled in the art in light of the present teachings without departing from the inventive concepts. Therefore, the technical solutions available to those skilled in the art through logic analysis, reasoning and limited experiments based on the concepts of the present application should be within the scope of protection defined by the claims.

Claims

1. An 8-channel analog input module, comprising:

the ADC is analog-to-digital conversion, and the submodule is used for performing analog-to-digital conversion on an input signal;

the multi-way switch array is used for switching polling between the ADC sub-module and different input channels;

the control chip is communicated with the LED indicator light, and the control chip is configured to control the display of the LED indicator light;

the control chip is communicated with the communication data bus, the communication data bus is communicated with the external DCS controller, and the control chip is configured to control communication of the communication data bus;

2. The analog input module of claim 1, wherein the power supply sub-modules include 24VA, 24VB, 24VC, and 24 VD; the 24VC and the 24VD are used for supplying power to field devices, and the 24VA and the 24VB are used for supplying power to the inside of the analog quantity input module after the inside 24V-to-5V DCDC direct-current voltage conversion module converts.

3. The analog input module of claim 1, wherein the control chip comprises an FPGA and an ARM chip.

4. The analog input module of claim 3, wherein the ARM chip is in communication with the LED indicator, the ARM chip configured to control the LED indicator.

5. The analog input module of claim 3, wherein the ARM chip is in communication with the FPGA, the ARM chip configured to receive signals from the FPGA and to transmit processed signals back to the FPGA.

6. The analog input module of claim 3, wherein the FPGA is in communication with the communication data bus, the FPGA configured to control the communication data bus; the FPGA is in direct communication with the multi-way switch array, and the FPGA is configured to control the channel selection of the multi-way switch array; the FPGA is further communicated with the multi-way switch array sequentially through the digital isolation sub-module and the ADC sub-module, and the FPGA is configured to receive input signals sequentially passing through the multi-way switch array, the ADC sub-module and the digital isolation sub-module.

7. The analog input module of claim 1, wherein the multi-way switch array comprises U72 and 8U 53; the U72 is configured as a 3-8 decoder and the U53 is configured as a relay.

8. The analog input module of claim 7, wherein the U72 includes 4 input pins CHN _ a1, CHN _ B1, CHN _ C1, and CHN _ D1; the 4 input pins of the U72 communicate with the FPGA and are configured to be controlled by signals output by the FPGA.

9. The analog input module of claim 8, wherein the U72 includes 8 output pins SW2Ch0-Ch7, the U72 is configured to select a certain output pin to output a low level according to signals of the input pins CHN _ a1, CHN _ B1, CHN _ C1.

10. The analog input module of claim 9, wherein each of the us 53 includes an output pin xspout +, xspout, and an input pin AIX +, AIX-; the output pins xspout +, xspout are connected to the ADC sub-module, and the input pins AIX +, AIX-are connected to an external signal source chX; the U53 is configured to turn on one of the corresponding signal sources Ch0-Ch7 to the output pins xspout +, xspout according to the output levels of the output pins SW2Ch0-Ch7 of the U72; wherein X represents a lane number, which is a number from 0 to 7.