CN213242549U

CN213242549U - Chip packaging structure

Info

Publication number: CN213242549U
Application number: CN202022587007.1U
Authority: CN
Inventors: 汤永长
Original assignee: Suzhou Xinjingteng Photoelectric Technology Co ltd
Current assignee: Suzhou Xinjingteng Photoelectric Technology Co ltd
Priority date: 2020-11-10
Filing date: 2020-11-10
Publication date: 2021-05-18
Anticipated expiration: 2030-11-10

Abstract

The utility model discloses a chip packaging structure, including the base plate and with base plate electric connection's wafer, be provided with the concave type window that supplies the wafer embedding on the base plate, the edge that the base plate was windowed along the recess is provided with the positive base plate pad of a plurality of outstanding base plates, the base plate pad run through the base plate and with the circuit electric connection at the base plate inside and the base plate back, the wafer is provided with the wafer pad that a plurality of outstanding wafers openly just correspond the setting with the base plate pad along the edge, wafer pad and base plate pad are through electrically conductive mounting fixed and electric connection. The cost of welding wires and the welding distance are saved, the size of a packaging plane is reduced, and the size and the thickness of the whole packaging structure are reduced. The existing common wire bonding machine can operate, the input cost is low, and the production efficiency is high.

Description

Chip packaging structure

Technical Field

The utility model relates to a chip processing technology field especially relates to a chip packaging structure.

Background

With the increasing development of electronic products, the industry is always going to improve the chip packaging density, improve the production efficiency and reduce the production line investment and production cost. However, the electronic product is limited by the thickness of the circuit board, the package thickness of the chip, the product structure, the process cost, and other factors during the design process. Although the volume can be smaller and thinner by the Flip-chip packaging process, the Flip-chip packaging process is limited by factors such as complex process, extremely high input equipment, difficulty in processing a bare chip, and weak compatibility with the SMT process during application. When the SMT process compatibility of the TSSOP (Thin surface mount Package) packaged chip and the printed circuit board in the market is good, the total thickness of the chip Package is reduced to 1.1-1.2mm, but the chip Package is difficult to reduce, and the problem that the chip Package needs to be broken through is solved.

As shown in fig. 1 and 2, the conventional chip package structure is configured such that the circuit connection between the die 2 ' and the substrate 1 ' is conducted through the bonding metal wire 3 ', the bonding machine first sinters the first bonding pad metal ball 31 ', then places the first bonding pad metal ball on the die pad 21 ', then moves the rising height of the bonding head Z of the bonding machine upward and the axis of the platform X, Y to form the wire loop height H2, then slowly lowers the rising height of the Z and the axis of the platform X, Y is directed to the second bonding pad, sinters the second bonding pad metal ball 33 ', and finally places the second bonding pad metal ball 33 ' on the substrate pad 11 ', and connects the die 2 ' and the substrate 1 ' through the metal wire 3 '. A large amount of bonding wires are needed in the welding process, the processing is complex, and the chip formed by packaging is large in size and small in thickness, so that the production requirement cannot be met.

SUMMERY OF THE UTILITY MODEL

In order to overcome the above disadvantages, an object of the present invention is to provide a chip package structure, which saves the cost of bonding wires, saves materials, forms a chip with small volume and thin thickness, and can be used for various electronic products in batch production.

In order to achieve the above purpose, the utility model discloses a technical scheme is: a chip packaging structure comprises a substrate and a wafer electrically connected with the substrate, and is characterized in that: be provided with the concave type window that supplies the wafer embedding on the base plate, the edge that the base plate followed concave type window is provided with the positive base plate pad of a plurality of outstanding base plates, the base plate pad run through the base plate and with the inside circuit electric connection at the base plate back, the wafer is provided with the positive wafer pad that just corresponds the setting with the base plate pad of a plurality of outstanding wafers along the edge, wafer pad and base plate pad are through fixed and electric connection of electrically conductive mounting.

The beneficial effects of the utility model reside in that: the wafer is embedded in the concave window of the substrate, the wafer bonding pad and the substrate bonding pad are correspondingly arranged on the wafer and the substrate, and the wafer bonding pad and the substrate bonding pad are directly fixed through the conductive fixing piece so as to realize the fixation and the electrical conduction of the wafer and the substrate. The cost of welding wires and the welding distance are saved, the size of a packaging plane is reduced, and the size and the thickness of the whole packaging structure are reduced. The existing common wire bonding machine can operate, the input cost is low, and the production efficiency is high.

Furthermore, the upper surface of the wafer bonding pad and the upper surface of the substrate bonding pad are located at the same height, so that the conductive fixing piece is convenient to arrange and operate.

Furthermore, the distance between the side edge of the wafer and the inner side wall of the concave windowing window is less than 0.1mm, namely the distance between the wafer bonding pad and the substrate bonding pad is less than 0.1mm, so that the conductive fixing piece is conveniently arranged, and the operation is convenient.

Further, one side of the substrate bonding pad, which faces the wafer bonding pad, is provided with an arc-shaped notch, and the conductive fixing piece covers the arc-shaped notch, so that the conductive fixing piece can conveniently cover the arc-shaped notch, and the fixation and the electrical conduction are realized.

Furthermore, the surface of the substrate bonding pad is plated with nickel to form a conductive nickel film, so that the conductivity is good, and the upper surface of the substrate bonding pad is also plated with gold or gold alloy positioned on the outer side of the conductive nickel film, so that the conductivity of the substrate bonding pad is increased, and the welding effect of the conductive fixing piece is improved.

Further, the glue for wrapping the wafer is filled in the concave windowing, the glue protects the surface of the wafer and the bonding pad, and the side wall of the substrate is provided with at least one drainage groove communicated with the concave windowing, so that the glue filling flowing effect is improved, and bubbles generated in the glue coating process are reduced.

Further, the front surface of the substrate is provided with at least two optical mark points. The die bonder distinguishes the position of an optical mark point through a PRS image recognition system of the die bonder, and accurately attaches the wafer to the concave window of the substrate by calculating relative coordinates.

Further, the conductive fixing part is one of a metal solder ball, a conductive paste and graphite, the metal solder ball is fixed on the upper surfaces of the wafer bonding pad and the substrate bonding pad in a welding mode, and the conductive paste or the graphite is solidified on the upper surfaces of the wafer bonding pad and the substrate bonding pad through heating.

Drawings

FIG. 1 is a top view of a prior art chip package structure;

FIG. 2 is a cross-sectional view of a prior art chip package structure;

fig. 3 is a top view of an embodiment of the present invention;

fig. 4 is a cross-sectional view of an embodiment of the invention;

FIG. 5 is a view taken from the point A in FIG. 4;

FIG. 6 is a schematic structural view of a drainage groove in an embodiment of the present invention;

fig. 7 is a schematic structural diagram of a substrate according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of a wafer according to an embodiment of the present invention.

In the figure:

1 ', 1-substrate, 11 ', 11-substrate pad, 111-arc notch, 2 ', 2-wafer, 21 ', 21-wafer pad, 3 ' -metal wire, 31 ' -first welding spot metal ball, 33 ' -second welding spot metal ball, 3-concave windowing, 31-drainage groove, 4-conductive fixing piece, 5-glue and 6-optical mark point.

Detailed Description

The following detailed description of the preferred embodiments of the present invention will be provided in conjunction with the accompanying drawings, so as to enable those skilled in the art to more easily understand the advantages and features of the present invention, and thereby define the scope of the invention more clearly and clearly.

Examples

Referring to fig. 3-8, the chip package structure of the present invention includes a substrate 1 and a wafer 2 electrically connected to the substrate 1, a concave window 3 for the wafer 2 to be embedded is disposed on the substrate 1, the substrate 1 is provided with a plurality of substrate pads 11 protruding from the front surface of the substrate 1 along the edge of the concave window, and the substrate pads 11 are disposed at intervals. The substrate pad 11 penetrates through the substrate 1 and is electrically connected with the circuit inside the substrate 1 and on the back surface of the substrate 1, and the surface of the substrate pad 11 is plated with nickel to form a conductive nickel film, so that the conductivity is good.

The wafer 2 is provided with a plurality of wafer bonding pads 21 which protrude from the front surface of the wafer 2 and are arranged corresponding to the substrate bonding pads 11 along the edge, the wafer bonding pads 21 are electrically connected with the circuits inside the wafer 2, and the wafer bonding pads 21 and the substrate bonding pads 11 are fixed and electrically connected through the conductive fixing parts 4.

The conductive fixing member 4 may be a metal solder ball, and the metal solder ball is soldered and fixed on the upper surfaces of the die pad 21 and the substrate pad 11. The conductive fixing member 4 may also be made of conductive paste or graphite, which is coated on the surfaces of the die pad 21 and the substrate pad 11 by printing or electrostatic spraying, and then cured on the upper surfaces of the die pad 21 and the substrate pad 11 by heating, so as to fix the conductive fixing member and the substrate 1 and the die 2.

The upper surface of the die bonding pad 21 and the upper surface of the substrate bonding pad 11 are located at the same height, so that the conductive fixing piece 4 is convenient to arrange and operate. The distance between the side edge of the wafer 2 and the inner side wall of the concave windowing is less than 0.1mm, namely the distance between the wafer bonding pad 21 and the substrate bonding pad 11 is less than 0.1mm, so that the conductive fixing piece 4 is convenient to set and operate. One side of the substrate bonding pad 11 facing the wafer bonding pad 21 is provided with an arc-shaped notch 111, and the conductive fixing member 4 covers the arc-shaped notch 111, so that the conductive fixing member 4 can conveniently cover, and fixation and electrical conduction are realized.

The upper surface of the substrate bonding pad 11 is also plated with gold or gold alloy positioned outside the electric nickel film, so that the conductivity of the substrate bonding pad 11 is increased, and the welding effect of the conductive fixing piece 4 is improved.

The glue 5 for wrapping the wafer 2 is filled in the concave windowing 3, the glue 5 protects the surface of the wafer 2 and the bonding pad, the side wall of the substrate 1 is provided with at least one drainage groove 31 communicated with the concave windowing, the filling flowing effect of the glue 5 is improved, and bubbles generated in the glue coating process are reduced.

The front side of the substrate 1 is further provided with at least two optical marker spots 6. The die bonder distinguishes the position of the optical mark point 6 through a PRS image recognition system of the die bonder, and accurately attaches the wafer 2 to the concave window of the substrate 1 through calculating relative coordinates.

The wafer 2 is embedded in the concave window 3 of the substrate 1, the wafer pad 21 and the substrate pad 11 are correspondingly arranged on the wafer 2 and the substrate 1, and the wafer pad 21 and the substrate pad 11 are directly fixed through the conductive fixing piece 4, so that the wafer 2 and the substrate 1 are fixed and electrically conducted. The cost of welding wires and the welding distance are saved, the size of a packaging plane is reduced, and the size and the thickness of the whole packaging structure are reduced. The existing common wire bonding machine can operate, the input cost is low, and the production efficiency is high.

The above embodiments are only for illustrating the technical concept and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and implement the present invention, so as not to limit the protection scope of the present invention, and all equivalent changes or modifications made according to the spirit of the present invention should be covered in the protection scope of the present invention.

Claims

1. A chip packaging structure comprises a substrate (1) and a wafer (2) electrically connected with the substrate (1), and is characterized in that: be provided with concave type windowing (3) that supply wafer (2) to imbed on base plate (1), base plate (1) is provided with a plurality of outstanding base plate (1) positive base plate pad (11) along the edge of concave type windowing (3), base plate pad (11) run through base plate (1) and with the inside circuit electric connection at the back with base plate (1), wafer (2) are provided with a plurality of outstanding wafer along the edge openly and correspond wafer pad (21) that set up with base plate pad (11), wafer pad (21) and base plate pad (11) are fixed and electric connection through electrically conductive mounting (4).

2. The chip packaging structure according to claim 1, wherein: the upper surface of the wafer bonding pad (21) and the upper surface of the substrate bonding pad (11) are positioned at the same height.

3. The chip packaging structure according to claim 1, wherein: the distance between the side edge of the wafer (2) and the inner side wall of the concave window (3) is less than 0.1 mm.

4. The chip packaging structure according to claim 1, wherein an arc notch (111) is formed on a side of the substrate bonding pad (11) facing the die bonding pad (21).

5. The chip packaging structure according to claim 1, wherein: the surface of the substrate bonding pad (11) is plated with nickel to form a conductive nickel film, and the upper surface of the substrate bonding pad (11) is also plated with gold or a gold alloy positioned on the outer side of the conductive nickel film.

6. The chip packaging structure according to claim 1, wherein: the glue (5) for wrapping the wafer is filled in the concave windowing (3), and at least one drainage groove (31) communicated with the concave windowing (3) is formed in the side wall of the substrate (1).

7. The chip packaging structure according to claim 1, wherein: the front surface of the substrate (1) is also provided with at least two optical mark points (6).

8. The chip packaging structure according to claim 1, wherein: the conductive fixing piece (4) is one of a metal solder ball, conductive paste and graphite, the metal solder ball is welded and fixed on the upper surfaces of the wafer bonding pad (21) and the substrate bonding pad (11), and the conductive paste or the graphite is heated and solidified on the upper surfaces of the wafer bonding pad (21) and the substrate bonding pad (11).