CN213213417U

CN213213417U - Temperature compensated phase-locked crystal oscillator

Info

Publication number: CN213213417U
Application number: CN202022182441.1U
Authority: CN
Inventors: 唐立
Original assignee: Chengdu Hengjing Technology Co ltd
Current assignee: Chengdu Hengjing Technology Co ltd
Priority date: 2020-09-29
Filing date: 2020-09-29
Publication date: 2021-05-14
Anticipated expiration: 2030-09-29

Abstract

The utility model relates to a crystal oscillator technical field, concretely relates to temperature compensation phase-locked crystal oscillator, including temperature compensation crystal oscillator, phase-locked module, high frequency voltage-controlled crystal oscillator, temperature compensation crystal oscillator output stable reference frequency to phase-locked module, the phase-locked module carries out the phase comparison to the frequency of phase-locked module and high frequency voltage-controlled crystal oscillator, outputs voltage-controlled voltage to high frequency voltage-controlled crystal oscillator, voltage-controlled voltage control high frequency voltage-controlled crystal oscillator's output frequency follows the frequency stability of temperature compensation crystal oscillator, and high frequency voltage-controlled crystal oscillator outputs low phase noise high frequency clock, the phase-locked module includes FPGA and passive second order filter, the reference frequency of temperature compensation crystal oscillator and high frequency voltage-controlled crystal oscillator input is carried out the frequency division respectively by FPGA, and the signal after the frequency division carries out the phase discrimination through the logic gate, then outputs to high frequency voltage-controlled crystal oscillator after the filtering; the utility model discloses can provide the high frequency, the steady index of high temperature, the output clock of low phase noise. The module is simple in structure, low in cost and convenient to later-stage evolution and upgrade.

Description

Temperature compensated phase-locked crystal oscillator

Technical Field

The utility model relates to a crystal oscillator technical field, concretely relates to temperature compensation phase-locked crystal oscillator.

Background

Some electronic devices require ac signals with highly stable frequencies, and LC oscillators have poor stability and easily drift in frequency. A highly stable signal can be generated by using a quartz crystal in an oscillator, which is called a crystal oscillator. Due to the technical development in the field of communication and navigation, the frequency stability of the working clock of the equipment is required on one hand, and the phase noise of the clock is required on the other hand, especially for high-frequency clocks such as 100M and the like. If the high-frequency clock crystal is directly adopted to vibrate to obtain high-phase noise, then the temperature compensation is directly carried out, or the requirements on an oscillating circuit and a temperature compensation device are high, the technical difficulty is high, and the cost is high.

The crystal oscillator which requires high frequency, low phase noise and high temperature stability at present generally adopts a high-frequency constant-temperature crystal oscillator, and the stability of output frequency is ensured through constant temperature. The constant temperature crystal oscillator has larger power consumption, and uses SC cut crystal with high price.

Based on this, the utility model designs a temperature compensation phase-locked crystal oscillator to solve above-mentioned problem.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a temperature compensation phase-locked crystal oscillator to solve the problem that proposes among the above-mentioned background art.

In order to achieve the above object, the utility model provides a following technical scheme: the temperature compensation phase-locked crystal oscillator comprises a temperature compensation crystal oscillator, a phase-locked module and a high-frequency voltage-controlled crystal oscillator, wherein the temperature compensation crystal oscillator outputs stable reference frequency to the phase-locked module, the frequencies of the temperature compensation crystal oscillator and the high-frequency voltage-controlled crystal oscillator are compared in phase by the phase-locked module, and voltage-controlled voltage is output to the high-frequency voltage-controlled crystal oscillator, the voltage-controlled voltage controls the output frequency of the high-frequency voltage-controlled crystal oscillator to follow the frequency stability of the temperature compensation crystal oscillator, the high-frequency voltage-controlled crystal oscillator outputs frequency to the phase-locking module, the high-frequency voltage-controlled crystal oscillator outputs a low-phase-noise high-frequency clock, the phase-locking module comprises an FPGA and a passive second-order filter, the FPGA is provided with a logic gate, the reference frequency input by the temperature compensation crystal oscillator and the high-frequency voltage-controlled crystal oscillator is divided by the FPGA respectively, and the signals after frequency division are subjected to phase discrimination through a logic gate and then filtered by a passive second-order filter and output to the high-frequency voltage-controlled crystal oscillator.

Further, the logic gate comprises a first and gate, a second and gate, a third and gate and a fourth and gate, signals of the temperature compensation crystal oscillator after frequency division are input to the first and gate and the second and gate, signals of the high-frequency voltage control crystal oscillator after frequency division are input to the first and gate and the third and gate, an output pin of the first and gate is connected with input pins of the second and gate and the third and gate, and output pins of the second and gate and the third and gate are connected with the passive second-order filter.

Further, the passive second-order filter comprises a capacitor C1, a capacitor C2 and a resistor R1, wherein the capacitor C1 is grounded, and the capacitor C2 and the resistor R1 are grounded in series.

Furthermore, the frequency dividing ratio of the FPGA to the temperature compensation crystal oscillator is 1: 1000.

Furthermore, the frequency dividing ratio of the FPGA to the high-frequency voltage-controlled crystal oscillator is 1: 10000.

Compared with the prior art, the beneficial effects of the utility model are that: the utility model discloses can provide the high frequency, the steady index of high temperature, the output clock of low phase noise. The module is simple in structure, low in cost and convenient to later-stage evolution and upgrade.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a schematic diagram of the module structure of the present invention;

fig. 2 is a schematic structural diagram of the phase-locked module of the present invention;

FIG. 3 is a schematic diagram of the chip structure of the present invention;

fig. 4 is the schematic diagram of the whole actual measurement index of the present invention (100 MHz).

In the drawings, the components represented by the respective reference numerals are listed below:

1. temperature compensation crystal oscillator; 2. a phase-locking module; 201. an FPGA; 202. a first AND gate; 203. A second AND gate; 204. a third AND gate; 205. a fourth AND gate; 206. a passive second order filter; 3. high-frequency voltage controlled crystal oscillator.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.

Referring to fig. 1-4, the present invention provides a technical solution: the temperature compensation phase-locked crystal oscillator comprises a temperature compensation crystal oscillator 1, a phase-locked module 2 and a high-frequency voltage-controlled crystal oscillator 3, wherein the temperature compensation crystal oscillator 1 outputs stable reference frequency to the phase-locked module 2, the temperature compensation crystal oscillator 1 can adopt a 5 × 7mm SMD +/-0.05 ppm @ 40-85 ℃ 10MHz temperature compensation crystal oscillator of a Hemson Technology company as a reference clock, and the high-frequency voltage-controlled crystal oscillator 3 can adopt a 5 × 7mm SMD voltage-controlled +/-30 ppm 0-3V of the Hemson Technology company Limited; -145dBc/Hz @1 KHz; the frequency of the temperature compensation crystal oscillator 1 and the frequency of the high-frequency voltage control crystal oscillator 3 are compared through the phase locking module 2, and voltage control voltage is output to the high-frequency voltage control crystal oscillator 3, the voltage control voltage controls the output frequency of the high-frequency voltage control crystal oscillator 3 to follow the frequency stability of the temperature compensation crystal oscillator 1, the high-frequency voltage control crystal oscillator 3 outputs frequency to the phase locking module 2, the high-frequency voltage control crystal oscillator 3 outputs a low-phase-noise high-frequency clock, the phase locking module 2 comprises an FPGA201 and a passive second-order filter 206, a logic gate is arranged on the FPGA201, the reference frequencies input by the temperature compensation crystal oscillator 1 and the high-frequency voltage control crystal oscillator 3 are respectively divided by the FPGA201, and the divided signals are phase-discriminated through the logic gate and then are filtered by the passive second-order filter 206 and output to the high-frequency voltage.

The logic gate comprises a first and gate 202, a second and gate 203, a third and gate 204 and a fourth and gate 205, the frequency-divided signal of the temperature compensation crystal oscillator 1 is input to the first and gate 202 and the second and gate 203, the frequency-divided signal of the high-frequency voltage control crystal oscillator 3 is input to the first and gate 202 and the third and gate 204, the output pin of the first and gate 202 is connected with the input pins of the second and gate 203 and the third and gate 204, and the output pins of the second and gate 203 and the third and gate 204 are connected with a passive second-order filter 206.

The passive second-order filter (206) comprises a capacitor C1, a capacitor C2 and a resistor R1, wherein the capacitor C1 is grounded, and the capacitor C2 and the resistor R1 are grounded in series.

The frequency dividing ratio of the FPGA (201) to the temperature compensation crystal oscillator (1) is 1: 1000.

The frequency dividing ratio of the FPGA (201) to the high-frequency voltage-controlled crystal oscillator (3) is 1: 10000.

As shown in fig. 3, the utility model comprises a power supply, a temperature compensation crystal oscillator 1(VCTCXO source crystal oscillator), a high frequency voltage controlled crystal oscillator 3(VCXO), a user interface and an FPGA201, wherein the high frequency voltage controlled crystal oscillator 3(VCXO) is selected from 100 MHz; no. 1 pin of power and FPGA 201's No. 9 pin electric connection, provide 1.2V's power for FPGA201, temperature compensation crystal oscillator 1(VCTCXO source crystal oscillator)'s No. 1 pin electric connection and user interface's No. 1 pin electric connection, temperature compensation crystal oscillator 1(VCTCXO source crystal oscillator)'s No. 3 pin and FPGA 201's No. 32 pin electric connection, high frequency voltage control crystal oscillator 3 (VCXO)'s No. 1 pin and FPGA 201's No. 30 pin electric connection, high frequency voltage control crystal oscillator 3 (VCXO)'s No. 3 pin and FPGA 201's No. 31 pin electric connection, user interface's No. 4 pin, No. 5 pin, No. 6 pin, No. 7 pin, No. 1 pin, No. 31 pin electric connection with FPGA 201's No. 32 pin electric connection No. 3 pin, No. 6 pin, No. 7 pin, No. 1 pin, No. 31 pin electric connection respectively.

The utility model provides a product model is only for the use that this technical scheme goes on according to the structural feature of product, and its product can be adjusted and reform transform after purchasing, makes it match more and accord with the utility model belongs to technical scheme, it is the technical scheme of an optimal application of this technical scheme, and the model of its product can be replaced and reform transform according to the technical parameter of its needs, and it is familiar for technical staff that belongs to in the field, consequently, what technical staff that belongs to in the field can be clear passes through the utility model provides a technical scheme obtains corresponding result of use.

In the description herein, references to the description of "one embodiment," "an example," "a specific example," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

The preferred embodiments of the present invention disclosed above are intended only to help illustrate the present invention. The preferred embodiments are not exhaustive and do not limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best understand the invention for and utilize the invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. Temperature compensation phase-locked crystal oscillator, including temperature compensation crystal oscillator (1), phase-locked module (2), high frequency voltage control crystal oscillator (3), its characterized in that: the temperature compensation crystal oscillator (1) outputs stable reference frequency to the phase locking module (2), the frequency of the temperature compensation crystal oscillator (1) and the frequency of the high-frequency voltage-controlled crystal oscillator (3) are compared through the phase locking module (2) to output voltage-controlled voltage to the high-frequency voltage-controlled crystal oscillator (3), the voltage-controlled voltage controls the output frequency of the high-frequency voltage-controlled crystal oscillator (3) to follow the frequency stability of the temperature compensation crystal oscillator (1), the high-frequency voltage-controlled crystal oscillator (3) outputs frequency to the phase locking module (2), the high-frequency voltage-controlled crystal oscillator (3) outputs a low-phase-noise high-frequency clock, the phase locking module (2) comprises an FPGA (201) and a passive second-order filter (206), a logic gate is arranged on the FPGA (201), the reference frequency input by the temperature compensation crystal oscillator (1) and the high-frequency voltage-controlled crystal oscillator (3) is divided by the FPGA (201), and the divided signals are phase-discriminated through, then the high-frequency voltage-controlled crystal oscillator is filtered by a passive second-order filter (206) and then output to a high-frequency voltage-controlled crystal oscillator (3).

2. The temperature-compensated phase-locked crystal oscillator of claim 1, wherein: the logic gate comprises a first AND gate (202), a second AND gate (203), a third AND gate (204) and a fourth AND gate (205), signals of the temperature compensation crystal oscillator (1) after frequency division are input into the first AND gate (202) and the second AND gate (203), signals of the high-frequency voltage control crystal oscillator (3) after frequency division are input into the first AND gate (202) and the third AND gate (204), an output pin of the first AND gate (202) is connected with input pins of the second AND gate (203) and the third AND gate (204), and output pins of the second AND gate (203) and the third AND gate (204) are connected with a passive second-order filter (206).

3. The temperature-compensated phase-locked crystal oscillator of claim 1, wherein: the passive second-order filter (206) comprises a capacitor C1, a capacitor C2 and a resistor R1, wherein the capacitor C1 is grounded, and the capacitor C2 and the resistor R1 are grounded in series.

4. The temperature-compensated phase-locked crystal oscillator of claim 1, wherein: the frequency dividing ratio of the FPGA (201) to the temperature compensation crystal oscillator (1) is 1: 1000.

5. The temperature-compensated phase-locked crystal oscillator of claim 1, wherein: the frequency dividing ratio of the FPGA (201) to the high-frequency voltage-controlled crystal oscillator (3) is 1: 10000.