CN213183602U

CN213183602U - DDR3 memory

Info

Publication number: CN213183602U
Application number: CN202021835752.7U
Authority: CN
Inventors: 颜军; 占连样; 颜志宇; 龚永红; 王烈洋; 汤凡; 陈像; 蒲光明; 陈伙立; 骆征兵
Original assignee: Zhuhai Orbita Aerospace Technology Co ltd
Current assignee: Zhuhai Orbita Aerospace Technology Co ltd
Priority date: 2020-08-28
Filing date: 2020-08-28
Publication date: 2021-05-11
Anticipated expiration: 2030-08-28

Abstract

The utility model discloses a DDR3 memory, include: function board, bottom plate and embedment layer. The functional board is provided with a plurality of DDR3 chips and a plurality of resistors, data group signal lines, clock signal lines, address signal lines and control signal lines of the DDR3 chips are respectively connected in parallel correspondingly, and the address signal lines and the control signal lines of the DDR3 chips are respectively and electrically connected with terminal voltage through the resistors. The bottom plate sets up in the function board below, and the welding of bottom plate bottom surface has a plurality of pins. The plurality of lead bridges are respectively arranged on the function board and the bottom board and are correspondingly and electrically connected with the plurality of DDR3 chips, the plurality of resistors and the plurality of pins. The bottom plate and the function plate are encapsulated in the encapsulating layer, and the pins extend out of the surface of the encapsulating layer. According to the DDR3 memory of the technical scheme, the address signal line and the control signal line are internally pulled up to the terminal voltage, and the address signal line and the control signal line are not required to be externally pulled up by setting resistors when the DDR3 memory is used, so that the wiring difficulty is reduced, and the design time is saved.

Description

DDR3 memory

Technical Field

The utility model relates to a memory field, in particular to DDR3 memory.

Background

The DDR3 memory is widely used as an operating memory in a high-speed electronic system, and during use of the DDR3 memory, an address signal line and a control signal line of the DDR3 memory need to be pulled up to a terminal voltage through a resistor, so as to ensure that a written data address is accurate. With the increasing capacity and bit width requirements of DDR3, more and more signals need to be pulled up to the termination voltage through resistors, and wiring is difficult to use.

SUMMERY OF THE UTILITY MODEL

The utility model discloses aim at solving one of the technical problem that exists among the prior art at least. Therefore, the utility model provides a DDR3 memory, the address signal line and the control signal line of a plurality of DDR3 chips come to the terminal voltage on the function board through a plurality of resistance, need not to increase resistance pull-up signal alone during the use again, use the wiring convenient.

According to the utility model discloses a DDR3 memory of embodiment includes: the functional board is provided with a plurality of DDR3 chips and a plurality of resistors, data group signal lines, clock signal lines, address signal lines and control signal lines of the DDR3 chips are respectively connected in parallel correspondingly, and the address signal lines and the control signal lines of the DDR3 chips are respectively and electrically connected with the terminal voltage interface through the resistors; the bottom plate is arranged below the function plate, and a plurality of pins are welded on the bottom surface of the bottom plate; the plurality of lead bridges are respectively arranged on the function board and the bottom board and are respectively and correspondingly and electrically connected with the DDR3 chip, the resistor and the pins; and the encapsulating layer encapsulates the bottom plate and the function plate, and the pins extend out of the surface of the encapsulating layer.

According to the utility model discloses DDR3 memory has following beneficial effect at least: DDR3 chip and resistance all set up on the function board, and the address signal line and the control signal line of a plurality of DDR3 chips correspond parallelly connected earlier, again respectively through a plurality of resistances and terminal voltage interface connection, can be through a plurality of lead wire bridge electric connection between function board and the bottom plate, draw out each signal from a plurality of pins on the bottom plate. The DDR3 memory's that draws forth through the bottom plate pin address signal line and the control signal line have already been inside through resistance pull-up to terminal voltage, need not to arrange resistance outside the memory again and pull-up the signal, reduce and use the wiring degree of difficulty, practice thrift design time.

According to the utility model discloses a some embodiments, still be equipped with a plurality of electric capacities on the function board, it is a plurality of the one end of electric capacity connect respectively in resistance with connecting node between the terminal voltage interface corresponds electric connection, and the other end all is connected with ground signal line electric connection.

According to some embodiments of the invention, the pin is a BGA pin.

According to some embodiments of the invention, the potting layer is a resin layer.

According to the utility model discloses a some embodiments, the one end of lead bridge is extended the surface of encapsulating, the encapsulating layer surface is provided with the metallic coating, be equipped with a plurality of groove on the metallic coating, the groove will a plurality of regions that do not communicate each other are cut apart into to the metallic coating, the lead bridge passes through the metallic coating corresponds electric connection.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a schematic cross-sectional view of an embodiment of the present invention;

fig. 2 is a schematic circuit diagram of an embodiment of the present invention;

fig. 3 is a schematic view of a metal plating layer and a scribed line according to an embodiment of the present invention.

Reference numerals:

a performance board 100, a DDR3 chip 110, a resistor 120, a capacitor 130,

the number of the base plate 200, the pins 210,

the lead bridge (300) is provided with a plurality of lead wires,

the potting layer (400) is formed on the substrate,

metal plating 500, scribe lines 510.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present invention, and should not be construed as limiting the present invention.

In the description of the present invention, it should be understood that the orientation or positional relationship indicated with respect to the orientation description, such as up, down, front, rear, left, right, etc., is based on the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.

In the description of the present invention, a plurality of means are one or more, a plurality of means are two or more, and the terms greater than, less than, exceeding, etc. are understood as not including the number, and the terms greater than, less than, within, etc. are understood as including the number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.

In the description of the present invention, unless there is an explicit limitation, the words such as setting, installation, connection, etc. should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above words in combination with the specific contents of the technical solution.

Referring to fig. 1 and 2, a DDR3 memory according to an embodiment of the present invention includes a function board 100, a bottom board 200, and a potting layer 400. The functional board 100 is provided with a plurality of DDR3 chips 110 and a plurality of resistors 120, data group signal lines, clock signal lines, address signal lines and control signal lines of the DDR3 chips 110 are respectively and correspondingly connected in parallel, the address signal lines and the control signal lines of the DDR3 chips 110 are also electrically connected with a terminal voltage interface through the resistors 120 after being connected in parallel, the address signal lines and the control signal lines of the DDR3 chips 110 are pulled up to a terminal voltage, and signal errors are prevented. The bottom board 200 is disposed under the performance board 100, a plurality of pins 210 are soldered to the bottom surface of the bottom board 200, and signals of the DDR3 chips 110 that need to be connected to the outside are all electrically connected to an external circuit through the pins 210. The function board 100 and the backplane 200 are both provided with a plurality of lead bridges 300, the lead bridges 300 are mainly used for electrical connection between the function board 100 and the backplane 200, and connection between each DDR3 chip 110 in the function board 100 and the plurality of resistors 120 can also be realized through the lead bridges 300. The encapsulating layer 400 encapsulates the performance board 100 and the bottom board 200 to protect devices on the performance board 100, and the pins 210 on the bottom board 200 extend out of the surface of the encapsulating layer 400, so as to facilitate the electrical connection between the DDR3 memory and an external circuit. According to the DDR3 memory of the technical scheme, the address signal lines and the control signal lines of each DDR3 chip 110 are internally pulled up to the terminal voltage, and the resistors 120 do not need to be arranged outside to pull up the address signal lines and the control signal lines of the DDR3 memory when the DDR3 memory is used, so that the wiring difficulty in use is reduced, and the design time is saved. It is understood that the lead bridges 300 can be electrically connected by metal leads or tin posts.

Referring to fig. 1 and 3, in some embodiments, one end of the lead bridge 300 extends out of the surface of the encapsulation layer 400, the metal plating layer 500 is disposed on the surface of the encapsulation layer 400, a plurality of scribe lines 510 are disposed on the metal plating layer 500, and the metal plating layer 500 can be divided into a plurality of regions that are not connected to each other by the plurality of scribe lines 510. One end of the plurality of lead bridges 300 extending out of the surface of the potting layer 400 is in contact with the metal plating layer 500, and the lead bridges 300 in contact with the metal plating layer 500 in the same region can be electrically connected through the metal plating layer 500. By dividing the lead bridges 300 to be electrically connected into the metal plating layer 500 in the same area through the scribe lines 510, the lead bridges 300 can be electrically connected according to the design, so as to lead the signals of the DDR3 chip 110 to the corresponding leads 210.

A DDR3 memory according to an embodiment of the present invention is described in detail below with reference to fig. 1 to 3 as a specific embodiment. It is to be understood that the following description is illustrative only and is not intended as a specific limitation on the invention.

Referring to fig. 1 and 3, in the present embodiment, the DDR3 memory is a BGA (ball grid array) package, the plurality of pins 210 on the bottom board 200 are BGA pins 210, and the BGA package has short pins, excellent electrical performance, high integration level, many pins, and good pin coplanarity. In the present embodiment, 199 pins 210 are soldered to the bottom surface of the bottom plate 200. Referring to fig. 2, in the present embodiment, 5 DDR3 chips 110 are disposed on the function board 100, a data group signal line, a clock signal line, an address signal line, and a control signal line of each DDR3 chip 110 are connected in parallel, and are led to a corresponding pin 210 on the backplane 200 through a lead bridge 300 and a metal plating 500, and a data signal of each DDR3 chip 110 is separately led to the corresponding pin 210 through the lead bridge 300 and the metal plating 500. The address signal lines and the control signal lines of the 5 DDR3 chips 110 are respectively electrically connected to the terminal voltage VTT through a plurality of resistors 120 after being parallel, the connection nodes between the resistors 120 and the terminal voltage, which are connected to the address signal lines and the control signal lines after being parallel, are also respectively grounded through a capacitor 130, and the plurality of capacitors 130 are used for filtering the terminal voltage of each address signal line and the control signal line. Referring to fig. 1, in the present embodiment, 5 DDR3 chips 110 are disposed on both upper and lower surfaces of a performance board 100, and a resistor 120 and a capacitor 130 are disposed on the lower surface of the performance board 100.

In the present embodiment, the functional board 100 and the chassis base 200 are potted with resin, and the potting layer 400 is a resin layer. The scribe lines 510 on the metal plating layer 500 divide the metal plating layer 500 into a plurality of rectangular areas arranged side by side, and as shown in fig. 3, the signals to be connected to each other are led to the lead bridges 300 located in the same column, so that the signals can be electrically connected.

According to the utility model discloses DDR3 memory, the inside pull-up of address signal line and control signal line is to terminal voltage and carry out the filtering to terminal voltage, need not the outside of DDR3 memory during the use and arranges resistance and electric capacity and come pull-up address signal line and control signal line, reduces the wiring complexity, practices thrift the design time.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention within the knowledge of those skilled in the art.

Claims

1. A DDR3 memory, comprising:

the functional board is provided with a plurality of DDR3 chips and a plurality of resistors, data group signal lines, clock signal lines, address signal lines and control signal lines of the DDR3 chips are respectively connected in parallel correspondingly, and the address signal lines and the control signal lines of the DDR3 chips are respectively and electrically connected with the terminal voltage interface through the resistors;

the bottom plate is arranged below the function plate, and a plurality of pins are welded on the bottom surface of the bottom plate;

the plurality of lead bridges are respectively arranged on the function board and the bottom board and are respectively and correspondingly and electrically connected with the DDR3 chip, the resistor and the pins;

and the encapsulating layer encapsulates the bottom plate and the function plate, and the pins extend out of the surface of the encapsulating layer.

2. The DDR3 memory of claim 1, wherein the functional board further comprises a plurality of capacitors, one end of each of the capacitors is electrically connected to a corresponding connection node between the resistor and the terminal voltage interface, and the other end of each of the capacitors is electrically connected to a ground signal line.

3. The DDR3 memory of claim 1 or 2, wherein the pins are BGA pins.

4. The DDR3 memory of claim 1 or 2, wherein the encapsulation layer is a resin layer.

5. The DDR3 memory of claim 1 or 2, wherein one end of the lead bridge extends out of the surface of the encapsulation layer, a metal plating layer is disposed on the surface of the encapsulation layer, a plurality of scribe lines are disposed on the metal plating layer, the scribe lines divide the metal plating layer into a plurality of areas that are not communicated with each other, and the lead bridge is electrically connected with the metal plating layer correspondingly.