CN213182261U - Display substrate and electronic device - Google Patents

Abstract

An embodiment of the present disclosure provides a display substrate, including: a substrate including a display region and a peripheral region; at least one binding piece used for being electrically connected with an external component is arranged in the peripheral area, the binding piece comprises a first conducting layer, a second conducting layer and an insulating layer located between the second conducting layer and the first conducting layer, the first conducting layer comprises a metal oxide conducting lead, and the second conducting layer comprises a metal conducting lead; one or more through holes are arranged in the region, corresponding to the metal oxide conductive lead, on the insulating layer; the metal conductive leads and the metal oxide conductive leads are connected in a one-to-one corresponding mode and are electrically connected through the one or more through holes; the binding further includes a via protection layer disposed on the metal oxide conductive leads in an area corresponding to the via. The embodiment of the disclosure also provides a reflective liquid crystal display panel and an electronic device.

Description

Display substrate and electronic device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a display substrate and an electronic device.

Background

The thin film transistor liquid crystal display device has been widely used in the field of display devices due to its characteristics of small size, low power consumption, etc. Transmissive liquid crystal display panels and reflective liquid crystal display panels are two common types of liquid crystal display panels. The reflective liquid crystal display panel can reflect light entering the display panel to serve as a light source required by image display to realize a display function, so that a special backlight source can be omitted, power consumption can be reduced, and the reflective liquid crystal display panel can be used for applications such as electronic books and outdoor advertisements. In the reflective liquid crystal display panel, a bonding region may be generally provided in the peripheral region for electrical connection with external electronic components.

SUMMERY OF THE UTILITY MODEL

An embodiment of the present disclosure provides a display substrate, including: a substrate base including a display area and a peripheral area surrounding the display area; wherein at least one binding piece for electrically connecting with an external component is arranged in the peripheral zone, the binding piece comprises a first conductive layer, and the first conductive layer comprises a metal oxide conductive lead; the binding further comprises a second conductive layer between the first conductive layer and the substrate base plate, the second conductive layer comprising a metal conductive lead; the binding further comprises an insulating layer between the second conductive layer and the first conductive layer, wherein one or more vias are provided in an area of the insulating layer corresponding to at least one metal oxide conductive lead, and the at least one metal oxide conductive lead comprises a portion of the insulating layer in contact with the insulating layer and a portion extending into a via in the insulating layer; the metal conductive leads and the metal oxide conductive leads are connected in a one-to-one correspondence manner and are electrically connected through the one or more through holes; the binding piece further comprises a via hole protection layer disposed on the metal oxide conductive lead in an area corresponding to the via hole.

In some embodiments, in the same binding, an area of an orthogonal projection of the via protection layer on the substrate base plate is smaller than an area of an orthogonal projection of a surface of the first conductive layer not covered by the via protection layer on the substrate base plate, the surface of the first conductive layer not covered by the via protection layer being a contact surface electrically connected with an external component.

In some embodiments, the via hole protection layer includes at least one metal layer, and the display substrate further includes a reflective electrode located in the display area, wherein the reflective electrode is made of the same material as the at least one metal layer.

In some embodiments, the at least one metal layer is a double-layer metal layer, which is a metal adhesion layer and a reflective metal layer disposed in a stacked manner.

In some embodiments, a plurality of sub-pixel units are arranged on the display area, a pixel electrode layer is arranged in each sub-pixel unit, the pixel electrode layer is positioned on one side of the reflection electrode facing the substrate base plate and is electrically connected with the pixel electrode, the orthographic projection of the pixel electrode layer on the substrate base plate is in a block shape, and the minimum distance between the edge of the orthographic projection of the reflection electrode on the substrate base plate and the edge of the orthographic projection of the pixel electrode layer on the substrate base plate in the same sub-pixel unit of the display area is less than 10 micrometers.

In some embodiments, a plurality of data lines and a plurality of gate lines are disposed in the display area, the plurality of data lines and the plurality of gate lines cross each other, and a distance between an orthographic projection of an edge of the reflective electrode in a sub-pixel unit of the display area on the substrate and an orthographic projection of a data line closest to the reflective electrode on the substrate is less than 8 micrometers.

In some embodiments, an orthographic projection of the via on the substrate base falls within an orthographic projection of the via protection layer on the substrate base, and a minimum distance between an outer edge of the orthographic projection of the via on the substrate base and an outer edge of the orthographic projection of the via protection layer on the substrate base is less than 15 microns.

In some embodiments, a gate layer and a source drain layer are disposed in the display region, the gate layer includes a gate of the thin film transistor, the source drain layer includes a source and a drain of the thin film transistor, and the second conductive layer is made of the same material as the source drain layer in the display region or the same material as the gate layer in the display region.

In some embodiments, a gate layer and a source drain layer are disposed in the display area, the gate layer includes a gate of the thin film transistor, the source drain layer includes a source and a drain of the thin film transistor, the at least one binding includes a first group of binding members and a second group of binding members, and in the first group of binding members, the second conductive layer is the same as the source drain layer in the display area; in the second group of binding members, the second conductive layer is the same as a gate layer in the display region, and the first group of binding members and the second group of binding members are alternately arranged in the peripheral region.

In some embodiments, the angle of slope of the vias in the first set of bindings is greater than the angle of slope of the vias in the second set of bindings.

In some embodiments, the range of ramp angles of the vias in the first set of bindings is between 20 degrees and 80 degrees; the angle of the slope of the vias in the second set of bindings ranges between 10 degrees and 60 degrees.

In some embodiments, the via is circular; the through hole protection layer is circular;

the via hole protective layer and the via hole are non-concentric circles.

In some embodiments, the display substrate is a reflective display substrate; the display area of the display substrate comprises a pixel electrode and a metal reflecting electrode positioned on the pixel electrode; and a transistor located in the display region, the transistor including a gate electrode, a gate insulating layer, a source electrode, and a drain electrode;

the second conductive layer of the peripheral region comprises a gate lead of the gate and a source lead of the source;

the first conducting layer of the peripheral area comprises a transparent metal oxide layer which is formed by the same material and process as the pixel electrode;

the insulating layer disposed between the transparent metal oxide layer and the gate lead or the source lead includes the gate insulating layer; the through hole is formed in the gate insulating layer; the grid lead or the source lead is connected with the transparent metal oxide layer through the through hole;

the grid lead or the source lead is a metal lead;

and forming a metal through hole protection layer which is made of the same material as the metal reflection electrode on the transparent metal oxide layer of the binding device area corresponding to the through hole area of the gate insulation layer.

Embodiments of the present disclosure further provide an electronic device including the display substrate according to any of the above embodiments.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it should be understood that the drawings described below relate only to some embodiments of the present disclosure, and not to limit the present disclosure, wherein:

fig. 1 illustrates a schematic view of a display substrate according to some embodiments of the present disclosure;

fig. 2 illustrates a schematic top view of a binding in a peripheral region of a display substrate, according to some embodiments of the present disclosure;

FIG. 3 shows a schematic cross-sectional view taken along line A-A as shown in FIG. 2;

FIG. 4 shows a schematic cross-sectional view taken along line B-B as shown in FIG. 2;

fig. 5 illustrates a schematic top view of a binding in a peripheral region of a display substrate according to further embodiments of the present disclosure;

FIG. 6 illustrates a schematic diagram of a sub-pixel cell in a display substrate, according to some embodiments of the present disclosure;

FIG. 7 shows a schematic cross-sectional view of a sub-pixel cell in a display substrate according to some embodiments of the present disclosure;

FIG. 8 illustrates a schematic view of a reflective liquid crystal display panel according to some embodiments of the present disclosure;

FIG. 9 illustrates a schematic flow chart diagram of a method of fabricating a binder for a reflective liquid crystal display panel according to some embodiments of the present disclosure;

FIG. 10 schematically illustrates a schematic flow chart of a method of fabricating a display area film structure of a reflective liquid crystal display panel according to further embodiments of the present disclosure; and

fig. 11 schematically illustrates an exemplary structure of a via protection layer.

Detailed Description

To more clearly illustrate the objects, aspects and advantages of the present disclosure, embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It is to be understood that the following description of the embodiments is intended to illustrate and explain the general concepts of the disclosure and should not be taken as limiting the disclosure. In the specification and drawings, the same or similar reference numerals refer to the same or similar parts or components. The figures are not necessarily to scale and certain well-known components and structures may be omitted from the figures for clarity.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "a" or "an" does not exclude a plurality. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", "top" or "bottom", etc. are used merely to indicate relative positional relationships, which may change when the absolute position of the object being described changes. When an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

A reflective liquid crystal display panel may generally include an array substrate (display substrate) and a color filter substrate and a liquid crystal layer interposed between the display substrate and the color filter substrate. Fig. 1 shows a schematic view of a display substrate 100 used in a reflective liquid crystal display panel. The display substrate 10 may be an array substrate, for example. The display substrate 100 may include a substrate 10. A display area AA and a peripheral area P are provided on the substrate base plate 10. The peripheral area P surrounds the display area AA. There may be a plurality of sub-pixels PX and a plurality of data lines 51 in the display area AA. One or more binding members 21 for electrical connection with external components (e.g., a flexible circuit board, an external integrated circuit board, etc.) may be provided in the peripheral region 20. The binding 21 may comprise, for example, a pad. As an example, some of the binding members 21 may be directly or indirectly connected to the plurality of data lines 51 or the gate lines described above. Of course, the binding 21 is not limited to transmitting a signal for the data line 51, but may transmit any other signal required for the operation of the display panel. The area of the plurality of peripheral zones 20 in which the binding 21 is arranged may also be referred to as a "binding zone" 22. Fig. 2 shows an example of the planar shape of the binding 21. As can be seen in fig. 2 and 3, the binding 21 may include a first conductive layer 31, a second conductive layer 32 between the first conductive layer 31 and the substrate base 10, and an insulating layer 33 between the second conductive layer 32 and the first conductive layer 31. The first conductive layer 31 may be made of, for example, metal oxide such as Indium Tin Oxide (ITO). The first conductive layer 31 may include a metal oxide conductive lead. The second conductive layer 32 may include a metal conductive lead. The insulating layer 33 may be, for example, a passivation layer, which may separate the first conductive layer 31 and the second conductive layer 32. The second conductive layer 32 may be electrically connected to the first conductive layer 31, for example, through a via 34 penetrating the insulating layer 33. Specifically, in some embodiments, one or more vias 34 are provided on the insulating layer 33 in regions corresponding to at least one metal oxide conductive lead, each metal oxide conductive lead including a portion on the insulating layer 33 in contact with the insulating layer and a portion extending into a via 34 on the insulating layer 33. The metal conductive leads and the metal oxide conductive leads are connected in a one-to-one correspondence, and the metal conductive leads and the metal oxide conductive leads are electrically connected through the one or more vias 34. The binding 21 may further include a via hole protection layer 35, the via hole protection layer 35 being disposed on the metal oxide conductive leads at an area corresponding to the via hole. The via protection layer 35 may be located on a side of the first conductive layer 31 remote from the substrate base plate 10 and cover the via 34. As an example, the first conductive layer 31 has a non-covered surface 36. The uncovered surface 36 is not covered by the via protection layer 35. The non-covered surface 36 may serve as a contact surface for electrical connection with external components.

To simplify the process, the first conductive layer 31, the second conductive layer 32, and the insulating layer 33 may be disposed in the same layer as, i.e., formed of the same material in the same process, some film structures in the display area AA of the display substrate. In some embodiments, as shown in fig. 7, on the substrate base plate 10, there are provided in the display area AA of the display base plate: a gate electrode layer 41, a gate insulating layer 42, a source-drain electrode layer 43, a passivation layer 44, a pixel electrode layer 45, and a reflective layer 46. The gate insulating layer 42 is disposed on a side of the gate electrode layer 41 away from the substrate base plate 10, the source-drain electrode layer 43 is disposed on a side of the gate insulating layer 42 away from the substrate base plate 10, the passivation layer 44 is disposed on a side of the source-drain electrode layer 43 away from the substrate base plate 10, the pixel electrode layer 45 is disposed on a side of the passivation layer 44 away from the substrate base plate 10, and the reflective layer 46 is disposed on a side of the pixel electrode layer 45 away from the substrate base plate 10. The reflective layer 46 covers the pixel electrode layer 45. The gate layer 41 may comprise the gate of a thin film transistor TFT 1. The source-drain layer 43 may include a source 431 and a drain 432 of the thin film transistor TFT 1. In some embodiments, the first conductive layer 31 may be made of the same material in the same process as the pixel electrode layer 45. Note that fig. 7 shows only an exemplary case where the thin film transistor TFT1 has a bottom gate type structure. However, embodiments of the present disclosure are not limited thereto, for example, the thin film transistor TFT1 may also adopt a top gate type structure, and in the case of adopting a thin film transistor of a top gate type structure for the display substrate, the gate layer 41 will be located on the side of the source-drain layer 43 away from the substrate 10.

Since the reflective electrode 46 is further provided on the side of the pixel electrode layer 45 away from the substrate base plate 10 in the film structure of the display substrate, when the bonding member 21 is manufactured, the material of the reflective electrode 46 on the side of the first conductive layer 31 away from the substrate base plate 10 needs to be etched away to expose at least a portion of the outer surface of the first conductive layer 31 to be electrically connected to external components. However, if the material of the reflective electrode 46 on the side of the first conductive layer 31 remote from the base substrate 10 is completely etched away, the etching liquid may corrode to the second conductive layer 32 through the via hole 34. The first conductive layer 31 serves to receive an electrical signal of an external component, and the second conductive layer 32 serves to transmit the electrical signal received from the first conductive layer 31 to the display region. Therefore, once the second conductive layer 32 is damaged, the transmission of the electrical signal may be unstable or even interrupted, which may seriously affect the stability of the screen display. In the embodiment of the present disclosure, the via hole 34 is covered with the via hole protection layer 35, thereby preventing damage of the etching solution to the second conductive layer 32. As an example, the via hole protection layer 35 may be made of the same material in the same process as the reflective electrode 46. Since the material of the reflective electrode 46 is generally composed of aluminum or an aluminum-molybdenum stack and aluminum may be oxidized at high temperature to cause a decrease in conductivity, if the via hole protection layer 35 completely covers the surface of the first conductive layer 31, the via hole protection layer 35 may be oxidized (a binding operation may be performed at high temperature) to affect signal transmission. Thus, in the embodiment of the present disclosure, the via hole protection layer 35 covers both the via hole 34 and the metal oxide conductive lead in the first conductive layer 31, and the contact surface of the first conductive layer 31 can be exposed while preventing the second conductive layer 32 from being damaged by the etching solution, so as to ensure stable transmission of the electrical signal.

In some embodiments, as shown in fig. 11, the via protection layer 35 may include at least one metal layer. As an example, the at least one metal layer may be a double metal layer. The two-layer metal layer may be a metal adhesion layer 352 and a metal reflection layer 351 for reflecting, which are stacked. The metal reflective layer 351 may be made of, for example, aluminum or an aluminum neodymium alloy. The metal adhesion layer 352 may be made of molybdenum, for example. Such a structure is advantageous for realizing the reflective electrode 46 in the display area AA. Such a structure is advantageous in that the via hole protective layer 35 and the reflective electrode 46 are formed in the same process. That is, the reflective electrode 46 and the via hole protection layer 35 are made of the same material in the display substrate. And such a structure can also well block the etching liquid to protect the via hole 34. As a further example, the at least one metal layer may also comprise, for example, only one metal layer (e.g., an aluminum layer).

In an embodiment of the present disclosure, the via hole protection layer 35 and the reflective electrode 46 may be made of, for example, an aluminum layer, a laminate of aluminum and molybdenum, or a laminate of an aluminum-neodymium alloy and molybdenum.

Fig. 3 and 4 show two different embodiments of the binding 21. In the embodiment shown in fig. 3, the second conductive layer 32 and the source and drain layers 43 in the display area AA are formed of the same material in the same process. In the display substrate, the second conductive layer 32 and the source/drain layer 43 in the display area AA have the same material. In the embodiment shown in fig. 4, the second conductive layer 32' is formed of the same material in the same process as the gate layer 41 in the display area AA. In the display substrate, the second conductive layer 32 and the gate layer 41 in the display area AA have the same material. In some embodiments, the at least one binding 21 comprises a first set of bindings 211 and a second set of bindings 212. In the first set of bonding members 211, the second conductive layer 32' is formed of the same material in the same process as the source and drain layers 43 in the display area AA; and in the second set of binding 212, the second conductive layer 32 is formed of the same material in the same process as the gate layer 41 in the display area AA. In other words, in the first group of bonding members 211, the second conductive layer 32' and the source/drain layer 43 in the display area AA have the same material; in the second set of binding members 212, the second conductive layer 32 and the gate layer 41 in the display area AA have the same material. As an example, the first and second sets of bindings 211, 212 are alternately arranged in the peripheral area P. With such a structure in which the first group of binding members 211 and the second group of binding members 212 are alternately arranged, the second conductive layers 32 and 32' in the adjacent binding members 21 can be prevented from being in different layers, which is advantageous for increasing the wiring density and saving the wiring space. This is also beneficial for reducing the spacing between adjacent bindings.

In some embodiments, as shown in fig. 3 and 4, the ramp angle α 1 of the vias in the first set of bindings 211 is greater than the ramp angle α 2 of the vias in the second set of bindings 212. This is because the second conductive layer 32' is closer to the uncovered surface 36 of the first conductive layer 31 and further away from the substrate base plate 10 for the first set of bindings 211 than for the second set of bindings 212. When the second conductive layer 32 is made of the same material and in the same process as the gate layer 41, the insulating layer 33 between the second conductive layer 32 and the first conductive layer 31 includes at least the passivation layer 44 and the gate insulating layer 42 at other positions where the via holes are removed, as shown in fig. 3. In contrast, as shown in fig. 4, when the second conductive layer 32 'and the source drain layer 43 are made of the same material and the same process, the insulating layer 33 between the second conductive layer 32' and the first conductive layer 31 includes at least the passivation layer 44 and does not include the gate insulating layer 42 at other positions where the via holes are removed. This results in a difference between the ramp angle α 1 of the vias in the first set of bindings 211 and the ramp angle α 2 of the vias in the second set of bindings 212. As an example, the ramp angle α 1 of the vias in the first set 211 ranges between 20 degrees and 80 degrees; the angle of slope α 2 of the vias in the second set of binding 212 ranges between 10 degrees and 60 degrees.

In some embodiments, as shown in fig. 2, the orthographic shape of the vias 34 of the binding 21 on the substrate base plate 10 is circular. A plurality of vias 34 may be provided in one binding 21. In other embodiments, as shown in fig. 5, the orthographic projection of the via 34 of the binding 21 on the substrate base plate 10 may be in the shape of a long strip. A single via 34 may be provided in one binding 21. In the example shown in fig. 2, the diameter of the via 34 (as may be measured at half height) may be, for example, a few microns to a few tens of microns. In the example shown in fig. 5, the width of the via 34 (as may be measured at half height) may be, for example, a few microns to a few tens of microns, such as around 10 microns. The embodiments of the present disclosure are not limited thereto, for example, the vias 34 may have other shapes, and the number of the vias 34 in each binding 21 may be set according to actual needs.

In some embodiments, the orthographic projection of the via 34 on the substrate base plate 10 falls within the orthographic projection of the via protection layer 35 on the substrate base plate 10. This can ensure that the via 34 is well covered by the via protective layer 35. The minimum distance h between the orthographic outer edge of the via 34 on the substrate base plate 10 and the orthographic outer edge of the via protection layer 35 on the substrate base plate 10 is for example less than 15 micrometer, such as less than 3 micrometer or 2 micrometer.

In some embodiments, the area of the orthographic projection of the via protection layer 35 on the substrate base 10 is smaller than the area of the orthographic projection of the uncovered surface 36 of the first conductive layer 31 on the substrate base 10 in the same binding. Since the non-covered surface 36 can be used as a contact surface for electrical connection with an external component, this can allow the first conductive layer 31 to have a sufficient contact surface for electrical connection with an external component to ensure stability of signals.

In some embodiments, an organic film layer 47 may be further disposed on the display area AA, as shown in fig. 7, the organic film layer 47 is located on a side of the source/drain layer 43 away from the substrate 10 and on a side of the passivation layer 44 away from the substrate 10. The thickness of the organic film layer 47 may be greater than that of the passivation layer 44. The organic film layer 47 may increase the distance between the pixel electrode layer 45 and the gate layer 41 and the source and drain layers 43 to reduce parasitic capacitance between the pixel electrode layer 45 and other conductive layers. As an example, the organic film layer 47 may be made of a material like a photoresist. In some embodiments, an active layer 48 may be further included on the display area AA, and the active layer 48 is located on a side of the gate insulating layer 42 away from the substrate base 10 and on a side of the source drain layer 43 facing the substrate base 10. The gate layer 41, the active layer 48, and the source-drain layer 43 described above may together form a thin film transistor structure. The connection vias 49 are shown in both fig. 6 and 7. The connection via 49 electrically connects the pixel electrode layer 45 and the source and drain electrode layer 43 (typically, a drain electrode) through the organic film layer 47 and the passivation layer 44, thereby achieving control of the thin film transistor for sub-pixel display.

In some embodiments, as shown in fig. 6, a plurality of sub-pixel units PX are disposed on the display area AA, and an orthographic projection of the pixel electrode layer 45 in each sub-pixel unit PX on the substrate 10 is in a block shape. In the same sub-pixel unit of the display area AA, the minimum distance b between the edge of the orthographic projection of the reflective electrode 46 on the substrate base plate 10 and the edge of the orthographic projection of the pixel electrode layer 45 on the substrate base plate 10 is less than 10 microns. This design can make the pixel electrode layer 45 have as large an area as possible to prevent the residual sand defect that may occur in the etching of the pixel electrode layer 45 from affecting the yield of the product.

In some embodiments, a plurality of data lines 51 and a plurality of gate lines 52 are disposed in the display area AA, the plurality of data lines 51 and the plurality of gate lines 52 cross each other, and a distance between an orthographic projection of an edge of the reflective electrode 46 in the sub-pixel unit PX of the display area AA on the substrate 10 and an orthographic projection of the data line 51 closest to the reflective electrode on the substrate 10 is less than 8 μm. This makes it possible to make the reflective electrode 46 have as large an area as possible and to avoid the generation of parasitic capacitance between the data line 51 and the reflective electrode 46. Only a part of one row of the sub-pixels is shown in fig. 6, and in fig. 6, overlapping the reflective electrode 46 at an upper portion of the sub-pixel is the gate line 52, and overlapping the reflective electrode 46 at a lower portion of the sub-pixel is the common electrode line 50. The common electrode applies a voltage to the liquid crystal layer together with the pixel electrode layer 45. The common electrode may be located on an opposite substrate (e.g., a color filter substrate) of the display substrate (e.g., an array substrate), for example. However, in order to increase the area of the common electrode on the circuit board to improve the signal stability, the common electrode line 50 may be disposed on the display substrate (e.g., an array substrate), and the common electrode line 50 is electrically connected to the common electrode on the opposite substrate (e.g., a color filter substrate), for example, the common electrode line 50 and the gate layer 41 may be made of the same material and by the same process, or the common electrode line 50 and the gate layer 41 may be made of the same material.

In some embodiments, the via is circular; the through hole protection layer is circular; the via hole protective layer and the via hole are non-concentric circles. The process difficulty can be reduced.

In some embodiments, the display substrate is a reflective display substrate; the display area of the display substrate comprises a pixel electrode and a metal reflecting electrode positioned on the pixel electrode; and a transistor located in the display region, the transistor including a gate electrode, a gate insulating layer, a source electrode, and a drain electrode;

the second conductive layer of the peripheral region comprises a gate lead of the gate and a source lead of the source;

the first conducting layer of the peripheral area comprises a transparent metal oxide layer which is formed by the same material and process as the pixel electrode;

the insulating layer disposed between the transparent metal oxide layer and the gate lead or the source lead includes the gate insulating layer; the through hole is formed in the gate insulating layer; the grid lead or the source lead is connected with the transparent metal oxide layer through the through hole;

the grid lead or the source lead is a metal lead;

and forming a metal through hole protection layer which is made of the same material as the metal reflection electrode on the transparent metal oxide layer of the binding device area corresponding to the through hole area of the gate insulation layer.

In some embodiments, the substrate may be a glass substrate, or may be a substrate made of other materials (e.g., plastic, resin, etc.).

As shown in fig. 8, an embodiment of the present disclosure also provides a reflective liquid crystal display panel 1000. The reflective liquid crystal display panel 1000 may include the display substrate 100 according to any of the foregoing embodiments, and may further include an opposite substrate (e.g., a color filter substrate) 200 and a liquid crystal layer 300 located between the display substrate 100 and the opposite substrate 200. The reflective liquid crystal display panel 1000 can be used in any display device, such as a smart phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a vehicle-mounted display, an electronic book, and the like. Embodiments of the present disclosure also provide an electronic device, which may include the display substrate 100 or the reflective liquid crystal display panel 1000 according to any of the foregoing embodiments. The electronic device may be any display device, such as a smart phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a vehicle-mounted display, an electronic book, and the like.

The embodiment of the present disclosure further provides a method for manufacturing a display substrate, including:

step S10: forming at least one binding piece for electrically connecting with an external component on a substrate in a peripheral area, wherein the binding piece comprises a first conductive layer, a second conductive layer positioned between the first conductive layer and the substrate, an insulating layer positioned between the second conductive layer and the first conductive layer, the first conductive layer comprises a metal oxide conductive lead, the second conductive layer comprises a metal conductive lead, one or more through holes are arranged on the insulating layer in an area corresponding to at least one metal oxide conductive lead, and the at least one metal oxide conductive lead comprises a part positioned on the insulating layer and a part extending into the through hole on the insulating layer; the metal conductive leads and the metal oxide conductive leads are connected in a one-to-one correspondence manner and are electrically connected through the one or more through holes; the binding piece further comprises a via hole protection layer disposed on the metal oxide conductive lead in an area corresponding to the via hole.

In some embodiments, as shown in fig. 9, the forming of the at least one binding in the peripheral region on the substrate base plate for electrical connection with the external component includes:

step S11: forming a second conductive layer in the peripheral region on the substrate base plate;

step S12: forming an insulating layer on one side of the second conducting layer far away from the substrate base plate and forming a through hole in the insulating layer;

step S13: forming a first conductive layer on one side of the insulating layer far away from the substrate base plate, wherein the first conductive layer is electrically connected with the second conductive layer through a through hole penetrating through the insulating layer; and

step S14: and forming a via hole protection layer on one side of the first conducting layer, which is far away from the substrate base plate, wherein the via hole protection layer covers the via hole.

Fig. 10 shows an example of a step of fabricating a film structure of a display region of a substrate base, which specifically includes:

step S21: forming a gate layer on a substrate;

step S22: sequentially forming a gate insulating layer and an active layer on one side of the gate layer away from the substrate;

step S23: forming a source drain layer on one side of the active layer far away from the substrate;

step S24: forming an organic film layer on one side of the source drain layer far away from the substrate;

step S25: forming a passivation layer on one side of the organic film layer far away from the substrate base plate;

step S26: forming a pixel electrode layer on one side of the passivation layer far away from the substrate; and

step S27: a reflective electrode is formed on a side of the pixel electrode layer remote from the substrate.

In order to simplify the process, the step of forming the binding in the peripheral region illustrated in fig. 9 may be performed together with the step of forming the film layer structure of the display region illustrated in fig. 10. In some embodiments, the second conductive layer may be made of the same material and process as the gate layer, that is, the step S11 may be performed simultaneously with the step S21 and combined into one step; in other embodiments, the second conductive layer and the source/drain layer may be made of the same material and by the same process, that is, the step S11 may be performed simultaneously with the step S23 and combined into one step. For another example, the first conductive layer and the pixel electrode layer may be made of the same material and by the same process, that is, the step S13 may be performed simultaneously with the step S26 and combined into one step. For another example, the via hole protection layer and the reflective electrode may be made of the same material and by the same process, that is, the step S14 may be performed simultaneously with the step S27 and combined into one step. In step S14, as an example, a stable and reliable electrical contact of the binding 21 with external components may be ensured by patterning the portion of the metal layer laid on the same layer as the reflective electrode 46 covering the binding 21, leaving the portion of the metal layer covering the via hole to form the via hole protection layer 35 and removing most of the portion of the metal layer covering the first conductive layer 31.

However, it will be understood by those skilled in the art that the method of manufacturing the display substrate shown in fig. 10 is merely exemplary, and in this example, the thin film transistor TFT1 in the display region employs a bottom gate type structure. However, embodiments of the present disclosure are not limited thereto, and for example, the thin film transistor TFT1 may also adopt a top gate type structure, and in the case of a thin film transistor in which the display substrate adopts a top gate type structure, a gate layer will be formed after a source drain layer. The specific steps for fabricating the thin film transistor with the top gate structure are well known to those skilled in the art and will not be described herein.

As can be seen from the above description, according to the display substrate of the embodiment of the present disclosure, the step of forming the film layer structure of the bonding member can be incorporated into the step of forming the film layer structure of the display area, and no new process step needs to be added.

In some embodiments, as described above, the at least one binding 21 includes a first set of binding 211 and a second set of binding 212, the second conductive layer 32 in the first set of binding 211 is formed of the same material in the same process as the source and drain layers 43 in the display area, the second conductive layer 32 in the second set of binding 212 is formed of the same material in the same process as the gate layer 41 in the display area, and the first set of binding 211 and the second set of binding 212 are alternately arranged in the peripheral area.

Embodiments of the present disclosure also provide an electronic device, including the transparent display panel 100, 100', 100 ″ of any of the foregoing embodiments. The electronic device can be any display device, such as a smart phone, a wearable smart watch, smart glasses, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a vehicle-mounted display, an electronic book, and the like.

Although the present disclosure is described in connection with the accompanying drawings, the embodiments disclosed in the drawings are intended to be illustrative of the embodiments of the disclosure, and should not be construed as a limitation of the disclosure. The dimensional proportions in the drawings are merely schematic and are not to be understood as limiting the disclosure.

The foregoing embodiments are merely illustrative of the principles and configurations of this disclosure and are not to be construed as limiting thereof, it being understood by those skilled in the art that any variations and modifications of the disclosure may be made without departing from the general concept of the disclosure. The protection scope of the present disclosure shall be subject to the scope defined by the claims of the present application.

Claims (14)

1. A display substrate, comprising:

a substrate base including a display area and a peripheral area surrounding the display area; wherein at least one binding piece for electrically connecting with an external component is arranged in the peripheral zone, the binding piece comprises a first conductive layer, and the first conductive layer comprises a metal oxide conductive lead;

the binding further comprises a second conductive layer between the first conductive layer and the substrate base plate, the second conductive layer comprising a metal conductive lead;

the binding further comprises an insulating layer between the second conductive layer and the first conductive layer, wherein one or more vias are provided in an area of the insulating layer corresponding to at least one metal oxide conductive lead, and the at least one metal oxide conductive lead comprises a portion of the insulating layer in contact with the insulating layer and a portion extending into a via in the insulating layer;

the metal conductive leads and the metal oxide conductive leads are connected in a one-to-one correspondence manner and are electrically connected through the one or more through holes;

the binding piece further comprises a via hole protection layer disposed on the metal oxide conductive lead in an area corresponding to the via hole.

2. The display substrate according to claim 1, wherein in the same binding, an area of an orthogonal projection of the via hole protection layer on the substrate is smaller than an area of an orthogonal projection of a surface of the first conductive layer not covered by the via hole protection layer on the substrate, the surface of the first conductive layer not covered by the via hole protection layer being a contact surface electrically connected with an external component.

3. The display substrate of claim 1,

the via hole protection layer comprises at least one metal layer, the display substrate further comprises a reflection electrode located in the display area, and the reflection electrode is made of the same material as the at least one metal layer.

4. The display substrate of claim 3,

the at least one metal layer is a double-layer metal layer which is a metal adhesion layer arranged in a laminated manner and a metal reflection layer with a reflection effect.

5. The display substrate according to claim 3, wherein a plurality of sub-pixel units are arranged on the display area, a pixel electrode layer is arranged in each sub-pixel unit, the pixel electrode layer is positioned on one side of the reflection electrode facing the substrate and is electrically connected with the pixel electrode, the orthographic projection of the pixel electrode layer on the substrate is in a block shape, and the minimum distance between the edge of the orthographic projection of the reflection electrode on the substrate and the edge of the orthographic projection of the pixel electrode layer on the substrate in the same sub-pixel unit of the display area is less than 10 micrometers.

6. The display substrate according to claim 5, wherein a plurality of data lines and a plurality of gate lines are provided in the display area, the plurality of data lines and the plurality of gate lines cross each other, and a distance between an orthographic projection of an edge of the reflective electrode in a sub-pixel unit of the display area on the substrate and an orthographic projection of a data line closest to the reflective electrode on the substrate is less than 8 μm.

7. The display substrate of claim 1, wherein an orthographic projection of the via on the substrate base falls within an orthographic projection of the via protection layer on the substrate base, and a minimum distance between an outer edge of the orthographic projection of the via on the substrate base and an outer edge of the orthographic projection of the via protection layer on the substrate base is less than 15 microns.

8. The display substrate according to claim 1, wherein a gate layer and a source drain layer are disposed in the display region, the gate layer includes a gate of the thin film transistor, the source drain layer includes a source and a drain of the thin film transistor, and the second conductive layer is made of the same material as the source drain layer in the display region or the same material as the gate layer in the display region.

9. The display substrate according to claim 1, wherein a gate layer and a source drain layer are disposed in the display area, the gate layer includes a gate electrode of a thin film transistor, the source drain layer includes a source electrode and a drain electrode of the thin film transistor, the at least one binding includes a first group of binding members in which the second conductive layer is the same material as the source drain layer in the display area, and a second group of binding members in which the second conductive layer is the same material as the source drain layer in the display area; in the second group of binding members, the second conductive layer is the same as a gate layer in the display region, and the first group of binding members and the second group of binding members are alternately arranged in the peripheral region.

10. The display substrate of claim 9, wherein a slope angle of the vias in the first set of bindings is greater than a slope angle of the vias in the second set of bindings.

11. The display substrate of claim 10, wherein the angle of slope of the vias in the first set of bonds ranges between 20 degrees and 80 degrees; the angle of the slope of the vias in the second set of bindings ranges between 10 degrees and 60 degrees.

12. The display substrate of any one of claims 1 to 11, wherein the via is circular; the through hole protection layer is circular;

the via hole protective layer and the via hole are non-concentric circles.

13. The display substrate of claim 1, wherein the display substrate is a reflective display substrate; the display area of the display substrate comprises a pixel electrode and a metal reflecting electrode positioned on the pixel electrode; and a transistor located in the display region, the transistor including a gate electrode, a gate insulating layer, a source electrode, and a drain electrode;

the second conductive layer of the peripheral region comprises a gate lead of the gate and a source lead of the source;

the first conducting layer of the peripheral area comprises a transparent metal oxide layer which is formed by the same material and process as the pixel electrode;

the insulating layer disposed between the transparent metal oxide layer and the gate lead or the source lead includes the gate insulating layer; the through hole is formed in the gate insulating layer; the grid lead or the source lead is connected with the transparent metal oxide layer through the through hole;

the grid lead or the source lead is a metal lead;

and forming a metal through hole protection layer which is made of the same material as the metal reflection electrode on the transparent metal oxide layer of the binding device area corresponding to the through hole area of the gate insulation layer.

14. An electronic device comprising the display substrate of any one of claims 1-13.

Images