CN213125620U

CN213125620U - External solid state hard disk circuit of camera

Info

Publication number: CN213125620U
Application number: CN202022003029.9U
Authority: CN
Inventors: 刘文刚
Original assignee: Kandao Technology Co Ltd
Current assignee: Kandao Technology Co Ltd
Priority date: 2020-09-14
Filing date: 2020-09-14
Publication date: 2021-05-04
Anticipated expiration: 2030-09-14

Abstract

The utility model discloses an external solid state hard drives circuit of camera, this circuit including be used for connecting external solid state hard drives the USB interface, be used for discerning whether the USB interface has external solid state hard drives male USB control circuit, be used for enabling the USB control circuit work enable circuit, be used for USB power supply circuit and the treater for the USB interface power supply, the USB interface respectively with USB control circuit and USB power supply circuit be connected and communicate with the treater, USB control circuit and USB power supply circuit and enable circuit connection and be connected and communicate with the treater. The utility model discloses realize the dilatation of camera memory, and portable, can guarantee simultaneously that the data furthest who transmits to external solid state hard disk preserves video details, provides the best assurance for later stage video processing effect. The utility model discloses still have characteristics such as with low costs, simple structure.

Description

External solid state hard disk circuit of camera

[ technical field ] A method for producing a semiconductor device

The utility model relates to a camera technical field especially relates to an external solid state hard drive circuit of camera.

[ background of the invention ]

A camera is an apparatus for forming an image using an optical imaging principle and recording the image using a negative film, and is well favored by professional or amateur photographers. The image shot by the existing camera is stored in a memory card in the camera, but the memory card has limited storage space and can not meet the requirements of photographers. In order to copy the image data of the camera, it is usually necessary to connect a computer, however, it is inconvenient for the photographer to carry the computer. The mobile solid state disk has the characteristics of high read-write speed, low power consumption, small volume, large capacity and the like, and is widely applied to storage media. However, the existing camera cannot directly exchange data with the solid state disk, and needs to use a computer as an intermediary for data exchange, which is not only troublesome, but also inconvenient for carrying the computer. Therefore, if the image data in the camera can be directly transmitted to the external hard disk for storage, the problem of limited memory of the camera is solved.

[ Utility model ] content

The utility model aims at solving the above problem, and provide an external solid state hard drive circuit of camera that can expand camera memory capacity, portable and with low costs.

In order to achieve the above object, the utility model provides an external solid state hard drives circuit of camera, this circuit including be used for connecting external solid state hard drives the USB interface, be used for discerning whether the USB interface has external solid state hard drives male USB control circuit, be used for enabling USB control circuit work enable circuit, be used for USB power supply circuit and the treater for the USB interface power supply, the USB interface is connected with USB control circuit and USB power supply circuit respectively and is connected and communicate with the treater, USB control circuit and USB power supply circuit and enable circuit connection and be connected and communicate with the treater.

The USB interface is a TYPE-C port.

The USB control circuit includes a first chip U1, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, and an eighth capacitor C8, wherein one end of each of the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7, and the eighth capacitor C8 is connected to a thirty-second pin, a seventh pin, a thirty-first pin, an eighth pin, a thirty-ninth pin, and a twenty-ninth pin of the first chip U1, respectively, and the other end of each of the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7, and the eighth capacitor C8 is grounded, and the first chip U1 is a chip of an IP model 2716.

The enabling circuit comprises a second MOS tube Q2, a third MOS tube Q3, a fourth MOS tube Q4, a fifth MOS tube Q5, a sixth transistor Q6, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11 and a twelfth resistor R12, wherein one end of the twelfth resistor R12 is connected with the processor, the other end of the twelfth resistor R12 is connected with the base of the sixth transistor Q6, the collector of the sixth transistor Q6 is respectively connected with one end of the eighth resistor R8, the gate of the third MOS tube Q8 and the gate of the fifth MOS tube Q8, the emitter of the sixth transistor Q8, the source of the third MOS tube Q8 and the source of the fifth MOS tube Q8 are grounded, the drain of the third MOS tube Q8 is connected with one end of the ninth resistor R8, the other end of the ninth resistor R8 is connected with the gate of the second MOS tube Q8 and the source of the seventh MOS tube Q8, the drain of the first resistor is connected to the thirty-second pin of the first chip U1, the other end of the seventh resistor R7 and the other end of the sixth resistor R6 are respectively connected to an output power supply of the USB power supply circuit, the drain of the fifth MOS transistor Q5 is connected to one end of the eleventh resistor R11, the other end of the eleventh resistor R11 is respectively connected to one end of the tenth resistor R10 and the gate of the fourth MOS transistor Q4, the drain of the fourth MOS transistor Q4 is connected to the thirty-first pin of the first chip U1, and the source of the fourth MOS transistor Q4, the other end of the tenth resistor R10 and the other end of the eighth resistor R8 are respectively connected to the system power supply.

Further, the sixth transistor Q6 is an NPN transistor, the second MOS transistor Q2 and the fourth MOS transistor Q4 are P-channel MOS transistors, the third MOS transistor Q3 and the fifth MOS transistor Q5 are N-channel MOS transistors, and the system power supply is 3.3V.

The power supply circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first capacitor C1, a second capacitor C2 and a first MOS transistor Q1, wherein a source of the first MOS transistor Q1 is respectively connected with one end of the second resistor R2 and one end of the third resistor R3, a gate of the first MOS transistor Q1 is respectively connected with the other end of the third resistor R3 and the fourth and fifth pins of the first chip U1, a drain of the first MOS transistor Q1 is respectively connected with one end of the fourth resistor R4 and one end of the first resistor R1, the other end of the second resistor R2 is connected with the third pin of the first chip U1, the other end of the fourth resistor R4 is respectively connected with one end of the second capacitor C2 and the second pin of the first chip U1, the other end of the second capacitor C2 is respectively connected with the first pin of the first resistor R2, and the other end of the first resistor R2 are respectively connected with the first pin of the first resistor R2, One end of the first capacitor C1 is respectively connected with the output power supply of the USB power supply circuit, and the other end of the first capacitor C1 is grounded.

Further, the first MOS transistor Q1 is a P-channel MOS transistor.

The USB control circuit communicates with the processor via the communication circuit via I2C.

The communication circuit comprises a seventh MOS tube Q7, an eighth transistor Q8, a sixteenth resistor R16, an eighteenth resistor R18, a twentieth resistor R20, a twenty-first resistor R21 and a twenty-second resistor R22, one end of the eighteenth resistor R18 is connected with the processor 50, the other end of the eighteenth resistor R18 is connected with the base of the eighth transistor Q8, the emitter of the eighth transistor Q8 and one end of the twentieth resistor R20 are grounded, the collector of the eighth transistor Q8 is respectively connected with one end of the sixteenth resistor R16 and the gate of the seventh MOS tube Q7, the other end of the sixteenth resistor R16 and the source of the seventh MOS tube Q7 are respectively connected with the system power supply, the drain of the seventh MOS tube Q7 is respectively connected with the other end of the twentieth resistor R20, one end of the twenty-first resistor R21 and one end of the twenty-second resistor R22, the other end of the twenty-first resistor R21 is connected with the twenty-first pin of the first chip 1, the other end of the twenty-second resistor R22 is connected with the twenty-first pin of the first chip U1.

The processor employs a Hi3559A chip.

The utility model has the advantages that: the utility model discloses a USB control circuit discerns the USB interface and has external solid state hard disk to insert the back, be external solid state hard disk power supply by USB supply circuit, then through the data transmission of treater with the camera to external solid state hard disk, thereby realize on the basis of not changing current camera USB interface, make camera USB interface not only joinable computer, still can connect external solid state hard disk and realize data transmission, with the dilatation of realizing the camera memory, and portable is particularly useful for the photographic worker of going out. In addition, the camera starts a high-coding-rate coding mode in the data transmission process, so that the data transmitted to the external solid state disk can be guaranteed to store video details to the maximum extent, and the best guarantee is provided for the later-stage video processing effect. The utility model discloses still have characteristics such as with low costs, simple structure.

[ description of the drawings ]

Fig. 1 is a schematic block diagram of the present invention.

Fig. 2 is a schematic circuit diagram of the present invention.

[ detailed description ] embodiments

The following examples are further to explain and supplement the present invention, and do not constitute any limitation to the present invention.

As shown in fig. 1, the external solid state disk circuit of the camera of the present invention includes a USB interface 10, a USB control circuit 20, an enable circuit 30, a USB power supply circuit 40, a processor 50, and a communication circuit 60. The circuit is used for transmitting data stored in the camera to the external solid state disk so as to realize the capacity expansion of the memory of the camera. The solid state disk in the embodiment is a customized m.2nvme solid state disk cartridge.

As shown in fig. 1 and fig. 2, the USB interface 10 is a USB interface of a camera, and is connected to a processor 50 of the camera for connecting to an external solid state disk. The USB interface in this embodiment is a TYPE-C port that is connected to the processor 50 and communicates through a PIC-E. The USB interface 10 is further connected to a USB control circuit 20, and the USB control circuit 20 is configured to identify whether an external solid state disk is inserted into the USB interface 10. Specifically, as shown in fig. 2, the USB control circuit 20 includes a first chip U1, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, and an eighth capacitor C8. One end of the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7 and the eighth capacitor C8 is connected to the thirty-second pin, the seventh pin, the thirty-first pin, the eighth pin, the thirty-ninth pin and the twenty-ninth pin of the first chip U1, and the other end of the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7 and the eighth capacitor C8 is grounded. The first chip U1 in this embodiment is a chip model IP2716, and the processor 50 employs a Hi3559A chip.

As shown in fig. 1, USB control circuit 20 is enabled by enable circuit 30, and enable circuit 30 has an input connected to processor 50 and an output connected to USB control circuit 20. Specifically, as shown in fig. 2, the enable circuit 30 includes a second MOS transistor Q2, a third MOS transistor Q3, a fourth MOS transistor Q4, a fifth MOS transistor Q5, a sixth transistor Q6, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, and a twelfth resistor R12. Wherein, one end of the twelfth resistor R12 is connected to the processor 50, the other end is connected to the base of the sixth transistor Q6, the collector of the sixth transistor Q6 is connected to one end of the eighth resistor R8, the gate of the third MOS transistor Q3 and the gate of the fifth MOS transistor Q5, respectively, the emitter of the sixth transistor Q6, the source of the third MOS transistor Q3 and the source of the fifth MOS transistor Q5 are grounded, the drain of the third MOS transistor Q3 is connected to one end of the ninth resistor R9, the other end of the ninth resistor R9 is connected to one end of the seventh resistor R7 and the gate of the second MOS transistor Q2, the source of the second MOS transistor Q2 is connected to one end of the sixth resistor R6, the drain thereof is connected to the thirty-second pin of the first chip U1, the other end of the seventh resistor R7 and the other end of the sixth resistor R6 are connected to the output power supply of the USB power supply circuit 40, the eleventh drain of the fifth transistor Q67 5 is connected to one end of the fifth transistor Q11, the other end of the eleventh resistor R11 is connected to one end of the tenth resistor R10 and the gate of the fourth MOS transistor Q4, respectively, the drain of the fourth MOS transistor Q4 is connected to the thirty-first pin of the first chip U1, and the source thereof, the other end of the tenth resistor R10, and the other end of the eighth resistor R8 are connected to the system power supply, respectively. In this embodiment, the sixth transistor Q6 is an NPN transistor, the second MOS transistor Q2 and the fourth MOS transistor Q4 are P-channel MOS transistors, and the third MOS transistor Q3 and the fifth MOS transistor Q5 are N-channel MOS transistors. The system power supply is a 3.3V power supply output by the power panel.

As shown in fig. 2, when the PD _ EN of the processor 50 outputs a high level, the sixth transistor Q6 is turned on, the voltage at the collector of the sixth transistor Q6 is low, the third MOS transistor Q3 and the fifth MOS transistor Q5 are both turned off, and the second MOS transistor Q2 and the fifth MOS transistor Q5 are also turned off, so that the thirty-first pin and the thirty-second pin of the first chip U1 have no voltage, and at this time, the first chip U1 does not operate. When the PD _ EN of the processor 50 outputs a low level, the sixth transistor Q6 is turned off, the collector voltage of the sixth transistor Q6 is at a high level, the third MOS transistor Q3 and the fifth MOS transistor Q5 are both turned on, and the second MOS transistor Q2 and the fourth MOS transistor Q4 are also turned on, so that the thirty-first pin of the first chip U1 has a voltage of 3.3V, the thirty-second pin of the first chip U1 is connected to the USB power supply through the sixth resistor R6, and at this time, the first chip U1 operates.

As shown in fig. 1, the USB control circuit 20 supplies power to the USB interface 10 through a USB power supply circuit 40, wherein an input terminal of the USB power supply circuit 40 is connected to the USB control circuit 20, and an output terminal thereof is connected to the USB interface 10. Specifically, the USB power supply circuit 40 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first capacitor C1, a second capacitor C2, and a first MOS transistor Q1. A source of the first MOS transistor Q1 is connected to one end of the second resistor R2 and one end of the third resistor R3, a gate of the first MOS transistor Q1 is connected to the other end of the third resistor R3 and the fourth and fifth pins of the first chip U1, a drain of the first MOS transistor Q1 is connected to one end of the fourth resistor R4 and one end of the first resistor R1, the other end of the second resistor R2 is connected to the third pin of the first chip U1, the other end of the fourth resistor R4 is connected to one end of the second capacitor C2 and the second pin of the first chip U1, the other end of the second capacitor C2 is connected to one end of the fifth resistor R5 and the first pin of the first chip U1, the other end of the fifth resistor R5 is connected to the other end of the first resistor R1 and one end of the first capacitor C1 are connected to the output power supply of the USB power supply circuit 40, and the other end of the first capacitor C1 is grounded. The first MOS transistor Q1 in this embodiment is a P-channel MOS transistor.

As shown in fig. 2, when the first chip U1 detects that the external solid state disk is inserted through the seventh pin and the eighth pin, the fourth pin and the fifth pin of the first chip U1 output a low level, the first MOS transistor Q1 is turned on, and the output POWER USB _ POR of the USB POWER supply circuit is connected to the POWER USBIN _ POWER through the first resistor R1 to supply POWER to the external solid state disk. Wherein, USBIN _ POWER is a 5V POWER supply output by the POWER panel. The first resistor R1 is a current sampling resistor, the fourth resistor R4, the fifth resistor R5 and the second capacitor C2 constitute a filter circuit, and the filter circuit is used for sampling the current flowing through the first resistor R1 by the first pin and the second pin of the first chip U1 through the filter circuit and controlling the maximum current of the USB _ POR to the external solid state disk. When the first chip U1 does not detect the insertion of the external solid state disk, the fourth pin and the fifth pin of the first chip U1 output a high level, the first MOS transistor Q1 is turned off, and the USB _ POR voltage is zero at this time.

As shown in fig. 1, the USB control circuitry 20 communicates with the processor 50 through communication circuitry 60. In this embodiment, the USB control circuit 20 performs I2C communication with the processor 50 through the communication circuit 60. Specifically, as shown in fig. 2, the communication circuit 60 includes a seventh MOS transistor Q7, an eighth transistor Q8, a sixteenth resistor R16, an eighteenth resistor R18, a twentieth resistor R20, a twenty-first resistor R21, and a twenty-second resistor R22. One end of the eighteenth resistor R18 is connected to the processor 50, the other end is connected to the base of the eighth transistor Q8, the emitter of the eighth transistor Q8 and one end of the twentieth resistor R20 are grounded, the collector of the eighth transistor Q8 is connected to one end of the sixteenth resistor R16 and the gate of the seventh MOS transistor Q7, respectively, the other end of the sixteenth resistor R16 and the source of the seventh MOS transistor Q7 are connected to the system power supply, which is the 3.3V power supply output by the power panel. The drain of the seventh MOS transistor Q7 is connected to the other end of the twentieth resistor R20, one end of the twenty-first resistor R21, and one end of the twenty-second resistor R22, respectively, the other end of the twenty-first resistor R21 is connected to the twentieth pin of the first chip U1, and the other end of the twenty-second resistor R22 is connected to the twenty-first pin of the first chip U1. In this embodiment, the seventh MOS transistor Q7 is a P-channel MOS transistor, and the eighth transistor Q8 is an NPN transistor.

As shown in fig. 2, when the PD _ I2C _ EN pin of the processor 50 outputs a high level, the eighth transistor Q8 is turned on, the collector output voltage thereof is low, the seventh MOS transistor Q7 is turned on, the twentieth and twenty-first pins of the first chip U1 are connected to the system power supply through the twenty-first resistor R21 and the twenty-second resistor R22, respectively, and the I2C communication circuit is enabled. When the PD _ I2C _ EN pin of the processor 50 outputs a low level, the eighth transistor Q8 is turned off, the collector output voltage thereof is a high level, the seventh MOS transistor Q7 is turned off, the twentieth and twenty-first pins of the first chip U1 are connected to ground through the twenty-first resistor R21, the twenty-second resistor R22 and the twentieth resistor R20, respectively, and the I2C communication circuit is disabled.

As shown in fig. 1, the working principle of the present invention is: the processor 50 enables the USB control circuit 20 to operate through the enabling circuit 30, and establishes a communication relationship with the USB control circuit 20 through the communication circuit 60. When the external solid state disk is inserted into the USB interface 10, the USB control circuit 20 detects that the external solid state disk is inserted into the USB interface 10 through the detection pin, and the USB control circuit 20 supplies power to the external solid state disk through the USB power supply circuit 40. Meanwhile, the processor 50 controls the relevant data channel of the USB interface 10 to switch to the pci-e high-speed data transmission mode, and then the camera starts the encoder to save the video details to the maximum extent, so as to provide the best guarantee for the later video processing effect, thereby realizing the transmission of the high-bit-rate data stored in the camera to the external solid state disk.

Although the present invention has been described in connection with the above embodiments, the scope of the present invention is not limited thereto, and modifications, replacements, and the like to the above members are all within the scope of the claims of the present invention without departing from the concept of the present invention.

Claims

1. The external solid state disk circuit of the camera is characterized by comprising a USB interface (10) used for being connected with an external solid state disk, a USB control circuit (20) used for identifying whether the external solid state disk is inserted into the USB interface (10), an enabling circuit (30) used for enabling the USB control circuit (20) to work, a USB power supply circuit (40) used for supplying power to the USB interface and a processor (50), wherein the USB interface (10) is respectively connected with the USB control circuit (20) and the USB power supply circuit (40) and connected with and communicated with the processor (50), and the USB control circuit (20) is connected with the USB power supply circuit (40) and the enabling circuit (30) and connected with and communicated with the processor (50).

2. The external solid state disk circuit of claim 1, wherein the USB interface (10) is a TYPE-C port.

3. The external solid state disk circuit of claim 1, wherein the USB control circuit (20) comprises a first chip U1, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, and an eighth capacitor C8, wherein one end of the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7, and the eighth capacitor C8 is connected to a thirty-second pin, a seventh pin, a thirty-first pin, an eighth pin, a thirty-third pin, and a twenty-ninth pin of the first chip U1, and the other end of the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7, and the eighth capacitor C8 is grounded, and the first chip U1 is an IP chip model No. 2716.

4. The external solid state disk circuit of claim 3, wherein the enable circuit (30) comprises a second MOS transistor Q2, a third MOS transistor Q3, a fourth MOS transistor Q4, a fifth MOS transistor Q5, a sixth transistor Q6, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11 and a twelfth resistor R12, one end of the twelfth resistor R12 is connected to the processor (50), the other end is connected to the base of the sixth transistor Q6, the collector of the sixth transistor Q6 is connected to one end of the eighth resistor R8, the gate of the third MOS transistor Q3 and the gate of the fifth MOS transistor Q5, the emitter of the sixth transistor Q6, the source of the third MOS transistor Q3 and the source of the fifth MOS transistor Q5 are grounded, the gate of the third MOS transistor Q6 is connected to the gate of the ninth MOS transistor Q3, the drain of the ninth MOS transistor Q3 is connected to the gate of the ninth MOS transistor Q3, the source of the second MOS transistor Q2 is connected to one end of a sixth resistor R6, the drain of the second MOS transistor Q2 is connected to the thirty-second pin of the first chip U1, the other end of the seventh resistor R7 and the other end of the sixth resistor R6 are respectively connected to an output power supply of the USB power supply circuit (40), the drain of the fifth MOS transistor Q5 is connected to one end of an eleventh resistor R11, the other end of the eleventh resistor R11 is respectively connected to one end of a tenth resistor R10 and the gate of the fourth MOS transistor Q4, the drain of the fourth MOS transistor Q4 is connected to the thirty-first pin of the first chip U1, and the source of the fourth MOS transistor Q4, the other end of the tenth resistor R10 and the other end of the eighth resistor R8 are respectively connected to a system power supply.

5. The external solid state disk circuit of claim 4, wherein the sixth transistor Q6 is an NPN transistor, the second MOS transistor Q2 and the fourth MOS transistor Q4 are P-channel MOS transistors, the third MOS transistor Q3 and the fifth MOS transistor Q5 are N-channel MOS transistors, and the system power supply is 3.3V.

6. The external solid state disk circuit of claim 3, wherein the USB power supply circuit (40) comprises a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first capacitor C1, a second capacitor C2 and a first MOS transistor Q1, the source of the first MOS transistor Q1 is connected to one end of the second resistor R2 and one end of the third resistor R3, the gate thereof is connected to the other end of the third resistor R3 and the fourth and fifth pins of the first chip U1, the drain of the first MOS transistor Q1 is connected to one end of the fourth resistor R4 and one end of the first resistor R1, the other end of the second resistor R2 is connected to the third pin of the first chip U1, the other end of the fourth resistor R4 is connected to one end of the second capacitor C2 and one end of the first resistor R1, the other end of the first resistor R2 is connected to the first pin U1, the other end of the fifth resistor R5 is respectively connected with the other end of the first resistor R1 and one end of the first capacitor C1 are respectively connected with an output power supply of the USB power supply circuit (40), and the other end of the first capacitor C1 is grounded.

7. The external solid state disk circuit of claim 6, wherein the first MOS transistor Q1 is a P-channel type MOS transistor.

8. The external solid state disk circuit of claim 3, wherein the USB control circuit (20) is in I2C communication with the processor (50) through the communication circuit (60).

9. The external solid state disk circuit of claim 8, wherein the communication circuit (60) comprises a seventh MOS transistor Q7, an eighth transistor Q8, a sixteenth resistor R16, an eighteenth resistor R18, a twentieth resistor R20, a twenty-first resistor R21 and a twenty-second resistor R22, one end of the eighteenth resistor R18 is connected to the processor (50), the other end of the eighteenth resistor R18 is connected to the base of the eighth transistor Q8, the emitter of the eighth transistor Q8 and one end of the twentieth resistor R20 are grounded, the collector of the eighth transistor Q8 is connected to one end of the sixteenth resistor R16 and the gate of the seventh MOS transistor Q7, the other end of the sixteenth resistor R16 and the source of the seventh MOS transistor Q7 are connected to the system power supply, the drain of the seventh MOS transistor Q7 is connected to the other end of the twentieth resistor R20, the one end of the first resistor R21 and the twenty-second resistor R22, the other end of the twenty-first resistor R21 is connected with the twentieth pin of the first chip U1, and the other end of the twenty-second resistor R22 is connected with the twenty-first pin of the first chip U1.

10. The external solid state disk circuit of claim 1, wherein the processor (50) is a Hi3559A chip.