CN213122748U - Clock dynamic switching circuit - Google Patents
Clock dynamic switching circuit Download PDFInfo
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- CN213122748U CN213122748U CN202022507394.3U CN202022507394U CN213122748U CN 213122748 U CN213122748 U CN 213122748U CN 202022507394 U CN202022507394 U CN 202022507394U CN 213122748 U CN213122748 U CN 213122748U
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Abstract
The utility model relates to a circuit design technical field, concretely relates to clock dynamic switching circuit, it includes first AND gate, second AND gate, first clock enable signal line, second clock enable signal line, first feedback signal line, second feedback signal line, first clock signal line, second clock signal line, level synchronization circuit, clock gate control circuit and or gate circuit. The level synchronization circuit is respectively used for synchronizing the first clock enabling signal line and the first clock signal, the second clock enabling signal line and the second clock signal are synchronized, the clock gating circuit is used for controlling the on-off of the clock signals, the clock gating circuit is introduced into the circuit in the application, so that all triggering of devices in the circuit uses the positive edge of the clock, the half-period path does not exist, the highest running frequency of the circuit is improved, the occurrence of the clock glitch is avoided through a feedback mechanism, and the signals output by the circuit are free of burrs.
Description
Technical Field
The utility model relates to a circuit design technical field, concretely relates to clock dynamic switching circuit.
Background
The chip usually has multiple paths of clocks with different frequencies, and when the chip is applied to different power consumption modes, the clocks can be dynamically switched according to needs. For example, when the chip runs with low power consumption, the clock is switched to a low-frequency clock; when the chip runs at full power, the clock is switched to the high-frequency clock. The frequencies of the high and low frequency clocks may not be related or may be multiples of each other. The problem to be noticed when dynamically switching the clock is to avoid the occurrence of clock glitch (see note 1), and if the unexpected clock glitch occurs, it may cause the fatal abnormal error of the chip (see note 2), which is absolutely not allowed in the product use.
Note 1: the clock glitch refers to a high-level pulse or a low-level pulse having a higher frequency than the clock.
Note 2: the digital circuit has the limitation of the highest operation clock frequency, can only stably operate under the condition that the operation clock frequency is less than or equal to the highest clock frequency, and if the unexpected clock glitch shows that the frequency of the current clock glitch is higher than the preset clock frequency in the circuit, the circuit is abnormal.
SUMMERY OF THE UTILITY MODEL
In order to solve the problem of clock glotch in dynamic clock switching, the following technical scheme is provided in the application.
A dynamic clock switching circuit, comprising: the clock gating circuit comprises a first AND gate, a second AND gate, a first clock enable signal line, a second clock enable signal line, a first feedback signal line, a second feedback signal line, a first clock signal line, a second clock signal line, a level synchronization circuit, a clock gating circuit and an OR gate circuit;
wherein the level synchronization circuit includes a first level synchronization unit and a second level synchronization unit;
the output end of the second feedback signal line and the first clock enable signal line are respectively connected with the input end of the first AND gate, the output end of the first AND gate is connected with the input end of the first level synchronization unit, and the output end of the first level synchronization unit is connected with the input end of the first feedback signal line;
the output end of the first feedback signal line and the second clock enable signal line are respectively connected with the input end of the second AND gate, the output end of the second AND gate is connected with the input end of the second level synchronization unit, and the output end of the second level synchronization unit is connected with the input end of the second feedback signal line;
the first clock enable signal line is connected with a signal input end of the first level synchronization unit, the second clock enable signal line is connected with a signal input end of the second level synchronization unit, and the first clock enable signal line and the second clock enable signal line are respectively used for inputting level signals required to be synchronized to the first level synchronization unit and the second level synchronization unit;
the first clock enable signal line and the second clock enable signal line are respectively used for inputting a first clock enable signal and a second clock enable signal to the first AND gate and the second AND gate; the first clock enable signal and the second clock enable signal have opposite phases, and the level synchronization circuit is used for synchronizing the first clock enable signal and the second clock enable signal, so that the first level synchronization unit and the second level synchronization unit respectively output a first clock enable level synchronization signal and a second clock enable level synchronization signal;
the clock gating circuit comprises a first clock gating unit and a second clock gating unit, wherein the output end of the first level synchronization unit is connected with the gating enable end of the first clock gating unit, and the first clock signal line is also connected with the clock input end of the first clock gating unit; the output end of the second level synchronization unit is connected with the gating enabling end of the second clock gating unit, and the second clock enabling signal line is also connected with the clock input end of the second clock gating unit; the first clock gating unit and the second clock gating unit respectively use a first clock enabling level synchronizing signal and a second clock enabling level synchronizing signal to control the connection and disconnection of a first clock signal line and a second clock signal line;
the output ends of the first clock gating unit and the second clock gating unit are respectively connected with the input end of the OR gate circuit, and the OR gate circuit is used for carrying out OR gate operation on the signals output by the first clock gating unit and the second clock gating unit to obtain target pulse signals.
In one embodiment, the signal feedback circuit comprises a first feedback unit and a second feedback unit;
the output end of the first level synchronization unit is connected with the input end of the first feedback unit, and the input end of the first feedback signal line is connected with the output end of the first feedback unit; the output end of the second level synchronization unit is connected with the input end of the second feedback unit, and the input end of the second feedback signal line is connected with the output end of the second feedback unit; the feedback circuit is used for eliminating the overlapping of the first clock enable level synchronous signal and the second clock enable level synchronous signal after synchronization.
In another embodiment, further comprising an inverter;
the second clock enabling signal line is further connected with the first clock enabling signal line through the phase inverter and is used for inverting a second clock enabling signal on the second clock enabling signal line to obtain the first clock enabling signal.
In another embodiment, the first level synchronization unit includes a first register and a second register, an input terminal of the first register is an input terminal of the first level synchronization unit, a non-inverting output terminal of the first register is connected to an input terminal of the second register, a non-inverting output terminal of the second register is an output terminal of the first level synchronization unit, and the first clock signal line is respectively connected to clock terminals of the first register and the second register;
the second level synchronization unit comprises a third register and a fourth register, the input end of the third register is the input end of the second level synchronization unit, the positive phase output end of the third register is connected with the input end of the fourth register, the positive phase output end of the fourth register is the output end of the second level synchronization unit, and the second clock signal line is respectively connected with the clock ends of the third register and the fourth register.
In another embodiment, the first feedback unit includes a fifth register, a non-inverting output terminal of the second register is connected to an input terminal of the fifth register, an input terminal of the first feedback signal line is connected to an inverting output terminal of the fifth register, and the first clock signal line is further connected to a clock terminal of the fifth register;
the second feedback unit comprises a sixth register, a positive phase output end of the fourth register is connected with an input end of the sixth register, an input end of the second feedback signal line is connected with an inverted phase output end of the sixth register, and the second clock signal line is further connected with a clock end of the sixth register.
The clock dynamic switching circuit according to the above embodiment includes: the clock gating circuit comprises a first AND gate, a second AND gate, a first clock enable signal line, a second clock enable signal line, a first feedback signal line, a second feedback signal line, a first clock signal line, a second clock signal line, a level synchronization circuit, a clock gating circuit and an OR gate circuit; the level synchronization circuit comprises a first level synchronization unit and a second level synchronization unit; the output end of the second feedback signal line and the first clock signal line are respectively connected with the input end of a first AND gate, the output end of the first AND gate is connected with the input end of a first level synchronization unit, and the output end of the first level synchronization unit is connected with the input end of the first feedback signal line; the output end of the first feedback signal line and the second clock signal line are respectively connected with the input end of a second AND gate, the output end of the second AND gate is connected with the input end of a second level synchronization unit, and the output end of the second level synchronization unit is connected with the input end of the second feedback signal line; the first clock enable signal line is connected with the input end of the first level synchronization unit, the second clock enable signal line is connected with the input end of the second level synchronization unit, and the first clock enable signal line and the second clock enable signal line are respectively used for inputting level signals required to be synchronized to the first level synchronization unit and the second level synchronization unit; the first clock enable signal line and the second clock enable signal line are respectively used for inputting a first clock enable signal and a second clock enable signal to the first AND gate and the second AND gate; the first clock enable signal and the second clock enable signal have opposite phases, and the level synchronization circuit is used for synchronizing the first clock enable signal and the second clock enable signal, so that the first level synchronization unit and the second level synchronization unit respectively output a first clock enable level synchronization signal and a second clock enable level synchronization signal; the clock gating circuit comprises a first clock gating unit and a second clock gating unit, wherein the output end of the first level synchronization unit is connected with the gating enable end of the first clock gating unit, and a first clock signal line is also connected with the clock input end of the first clock gating unit; the output end of the second level synchronization unit is connected with the gating enabling end of the second clock gating unit, and the second clock signal line is also connected with the clock input end of the second clock gating unit; the first clock gating unit and the second clock gating unit respectively use a first clock enabling level synchronizing signal and a second clock enabling level synchronizing signal to control the connection and disconnection of a first clock signal line and a second clock signal line; the output ends of the first clock gating unit and the second clock gating unit are respectively connected with the input end of an OR gate circuit, and the OR gate circuit is used for carrying out OR gate operation on the signals output by the first clock gating unit and the second clock gating unit to obtain a target pulse signal. The clock gating circuit is introduced into the circuit, so that the triggering of devices in the circuit completely uses the positive edge of the clock, and a half-period path does not exist, the highest running frequency of the circuit is improved, the occurrence of the clock glitch is avoided, and the signal output by the circuit is free of burrs through a feedback mechanism.
Drawings
FIG. 1 is a schematic diagram of a dynamic clock switching circuit according to an embodiment of the present disclosure;
fig. 2 is a timing diagram of a dynamic clock switching circuit according to an embodiment of the present disclosure.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.
Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.
The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).
The clock dynamic switching circuit introduces a clock gating circuit on the basis of the existing commonly used circuit, so that registers in the circuit all use the positive edge of a clock, and the circuit has no half-cycle path, the highest running frequency of the circuit is improved, and the occurrence of clock glitch is avoided.
Furthermore, in another embodiment, the dynamic clock switching circuit further comprises a signal feedback circuit, wherein the signal feedback circuit is specially used for the feedback of the clock signal, so that the problem of the glitch which may be generated when a plurality of asynchronous clocks are switched is solved. The synchronous clock refers to that the edges of the clock are at the same time, and is usually a source clock and a frequency division clock thereof; asynchronous clocks, meaning that the edges of the clocks are not at the same time.
The first embodiment is as follows:
referring to fig. 1, the present embodiment provides a dynamic clock switching circuit, which includes: the clock signal line comprises a first AND gate 10, a second AND gate 11, a first clock signal line 14, a second clock signal line 15, a first clock enable signal line 17, a second clock enable signal line 16, a first feedback signal line 13, a second feedback signal line 12, a level synchronization circuit 20, a clock gating circuit 21 and an OR gate circuit 23. The level synchronization circuit 20 includes a first level synchronization unit and a second level synchronization unit, for example, in fig. 1, the upper half of the level synchronization circuit 20 is the first level synchronization unit, and the lower half is the second level synchronization unit; the output end of the second feedback signal line 12 and the first clock enable signal line 17 are respectively connected with the input end of the first and gate 10, the output end of the first and gate 10 is connected with the input end of the first level synchronization unit, and the output end of the first level synchronization unit is connected with the input end of the first feedback signal line 13. The output end of the first feedback signal line 13 and the second clock enable signal line 16 are respectively connected with the input end of the second and gate 11, the output end of the second and gate 11 is connected with the input end of the second level synchronization unit, and the output end of the second level synchronization unit is connected with the input end of the second feedback signal line 12. The first clock signal line 14 is connected with a clock end of the first level synchronization unit, the second clock signal line 15 is connected with a clock end of the second level synchronization unit, and the first clock signal line 14 and the second clock signal line 15 are respectively used for inputting clock signals to the first level synchronization unit and the second level synchronization unit to control the operation of the first level synchronization unit and the second level synchronization unit. The first and second clock enable signal lines 17 and 16 are used to input a first and second clock enable signal to the first and second and gates 10 and 11, respectively, as shown in fig. 1, the first clock enable signal is sel _ clka, the second clock enable signal is sel _ clkb, the first and second clock enable signals are in opposite phases, and the level synchronization circuit is used to synchronize the first and second clock enable signals, so that the first and second level synchronization units output the first and second clock enable level synchronization signals sel _ clka _ d2 and sel _ clkb _ d2, respectively. The clock gating circuit 22 includes a first clock gating unit and a second clock gating unit, for example, in fig. 1, the upper half of the clock gating circuit 22 is the first clock gating unit 221, and the lower half is the second clock gating unit 222, an output end of the first level synchronization unit is connected to a gating enable end EN of the first clock gating unit 221, and the first clock signal line 14 is further connected to a clock end CK of the first clock gating unit 221; the output end of the second level synchronization unit is connected to the gate enable end EN of the second clock gate control unit 221, and the second clock signal line 16 is further connected to the clock end CK of the second clock gate control unit; the first clock gating unit 221 and the second clock gating unit 222 use the first clock enable level synchronization signal and the second clock enable level synchronization signal, respectively, for controlling the on/off of the first clock signal line 14 and the second clock signal line 15. The output end ECK of the first clock gating unit 221 and the second clock gating unit 222 is connected to the input end of the or gate circuit 23, and the or gate circuit 23 is configured to perform an or gate operation on the signals output by the first clock gating unit 221 and the second clock gating unit 222 to obtain a target pulse signal clk _ out. The clock dynamic switching circuit of the embodiment introduces a clock gating circuit on the basis of the existing commonly used circuit, so that registers in the circuit all use the positive edge of a clock, and the circuit does not have a half-period path, thereby improving the highest operating frequency of the circuit and avoiding the occurrence of clock jitter.
The clock gating circuit of the present embodiment is provided by a library unit of a digital circuit standard, and generally includes four signals of EN, CK, ECK, and TE, where CK is an input clock, ECK is an output clock, and EN and CK must be synchronous signals. When EN is high, CK is transmitted to the ECK end without burr output after the delay of one CK clock period, TE signal is the test enable of DFT, and when TE is high, ECK is equal to CK.
Further, in another embodiment, the clock dynamic switching circuit further includes a signal feedback circuit 21, where the signal feedback circuit 21 includes a first feedback unit 211 and a second feedback unit 212; an output end Q of the first level synchronization unit is connected with an input end D of the first feedback unit 221, and an input end of the first feedback signal line 13 is connected with an inverted output end of the first feedback unit 211; an output end Q of the second level synchronization unit is connected with an input end D of the second feedback unit 212, and an input end of the second feedback signal line 12 is connected with an inverted output end of the second feedback unit 212; the signal feedback circuit 21 is specially used for feedback of the clock signal, and the feedback circuit 21 is used for eliminating overlapping of the first clock enable level synchronous signal and the second clock enable level synchronous signal after synchronization, so that the problem of the glitch possibly generated when a plurality of asynchronous clocks are switched is solved.
The clock dynamic switching circuit in this embodiment further includes an inverter 18; the second clock enable signal line 16 is further connected to the first clock enable signal line 17 through an inverter 18, and is configured to invert the second clock enable signal sel _ clkb on the second clock enable signal line to obtain the first clock enable signal sel _ clka.
The first level synchronization unit in this embodiment includes a first register 201 and a second register 202, an input end D of the first register 201 is an input end of the first level synchronization unit, a non-inverting output end Q of the first register 201 is connected to an input end D of the second register 202, a non-inverting output end Q of the second register 202 is an output end of the first level synchronization unit, and the first clock signal line 14 is respectively connected to clock ends of the first register 201 and the second register 202. The second level synchronization unit comprises a third register 203 and a fourth register 204, an input end D of the third register 203 is an input end of the second level synchronization unit, a non-inverting output end thereof is connected with an input end of the fourth register 204, a non-inverting output end Q of the fourth register 204 is an output end of the second level synchronization unit, and a second clock signal line 15 is respectively connected with clock ends of the third register 203 and the fourth register 204.
The first feedback unit includes a fifth register, the non-inverting output terminal of the second register 202 is connected to the input terminal D of the fifth register, the input terminal of the first feedback signal line 13 is connected to the inverting output terminal of the fifth register, and the first clock signal line 14 is further connected to the clock terminal of the fifth register. The second feedback unit 212 includes a sixth register, a non-inverting output terminal of the fourth register 202 is connected to an input terminal of the sixth register, an input terminal of the second feedback signal line 12 is connected to an inverting output terminal of the sixth register, and the second clock signal line 15 is further connected to a clock terminal of the sixth register.
The sel _ clka _ d2/sel _ clkb _ d2 signals are generated after synchronizing the sel _ clka and sel _ clkb signals using level synchronizing circuit 20 in this embodiment, so that sel _ clka _ d2 is synchronized with clka and sel _ clkb _ d2 is synchronized with clkb. Clock gating circuit 21 is then used to gate clka and clkb, with the EN signal of clock gating circuit 21 being the synchronized sel _ clka _ d2/sel _ clkb _ d2 signals. Of positive-edge-triggered feedback circuits 21 after level-locked circuits 20
The terminal output is used as a feedback signal. The feedback circuit 21 is to eliminate the delay of one clock cycle introduced by the clock gating circuit 21.
FIG. 2 is a timing diagram of the switching circuit of FIG. 1. it can be seen from FIG. 2 that when sel _ clkb goes from low to high, the arrow in curve A represents the change of the signal from the low frequency clock to the high frequency clock; when sel _ clkb changes from high to low, the arrow in curve B represents the switch from high frequency clock to low frequency clock, and it can be seen from fig. 2 that no clock glitch occurs in the whole process, and the registers are all the timing triggered by positive edge.
In the embodiment, the sel _ clka/sel _ clkb signal is fed back to the input and AND gate after being synchronized by the two stages of positive edge registers and beaten by the one stage of positive edge register under the clka/clkb clock, and the clock to be switched is turned on after the current clock is turned off through feedback, so that only one clock is turned over at the input end of the or gate, and meanwhile, the registers of the whole clock switching circuit are triggered by the positive edge of the clock, thereby solving the problem of clock half-cycle paths, improving the highest running frequency of the circuit and solving the problem of glitch possibly generated when a plurality of asynchronous clocks are switched. In addition, registers of the whole clock switching circuit are triggered by adopting a positive clock edge, so that a back-end tool can be inserted into a Scan chain (Scan chain test), and the Scan chain can judge whether a chip is defective or not by moving in and out data under the control of an external clock edge.
It is right to have used specific individual example above the utility model discloses expound, only be used for helping to understand the utility model discloses, not be used for the restriction the utility model discloses. To the technical field of the utility model technical personnel, the foundation the utility model discloses an idea can also be made a plurality of simple deductions, warp or replacement.
Claims (5)
1. A dynamic clock switching circuit, comprising: the clock gating circuit comprises a first AND gate, a second AND gate, a first clock enable signal line, a second clock enable signal line, a first feedback signal line, a second feedback signal line, a first clock signal line, a second clock signal line, a level synchronization circuit, a clock gating circuit and an OR gate circuit;
wherein the level synchronization circuit includes a first level synchronization unit and a second level synchronization unit;
the output end of the second feedback signal line and the first clock enable signal line are respectively connected with the input end of the first AND gate, the output end of the first AND gate is connected with the input end of the first level synchronization unit, and the output end of the first level synchronization unit is connected with the input end of the first feedback signal line;
the output end of the first feedback signal line and the second clock enable signal line are respectively connected with the input end of the second AND gate, the output end of the second AND gate is connected with the input end of the second level synchronization unit, and the output end of the second level synchronization unit is connected with the input end of the second feedback signal line;
the first clock enable signal line is connected with a signal input end of the first level synchronization unit, the second clock enable signal line is connected with a signal input end of the second level synchronization unit, and the first clock enable signal line and the second clock enable signal line are respectively used for inputting level signals required to be synchronized to the first level synchronization unit and the second level synchronization unit;
the first clock enable signal line and the second clock enable signal line are respectively used for inputting a first clock enable signal and a second clock enable signal to the first AND gate and the second AND gate; the first clock signal enable phase and the second clock signal enable phase are opposite, and the level synchronization circuit is used for synchronizing the first clock enable signal and the second clock enable signal, so that the first level synchronization unit and the second level synchronization unit respectively output a first clock enable level synchronization signal and a second clock enable level synchronization signal;
the clock gating circuit comprises a first clock gating unit and a second clock gating unit, wherein the output end of the first level synchronization unit is connected with the gating enable end of the first clock gating unit, and the first clock signal line is also connected with the clock input end of the first clock gating unit; the output end of the second level synchronization unit is connected with the gating enabling end of the second clock gating unit, and the second clock enabling signal line is also connected with the clock input end of the second clock gating unit; the first clock gating unit and the second clock gating unit respectively use the output end of a first clock enabling level synchronizing signal and the output end of a second clock enabling level synchronizing signal and are used for controlling the connection and disconnection of a first clock signal line and a second clock signal line;
the output ends of the first clock gating unit and the second clock gating unit are respectively connected with the input end of the OR gate circuit, and the OR gate circuit is used for carrying out OR gate operation on the signals output by the first clock gating unit and the second clock gating unit to obtain target pulse signals.
2. The clock dynamics switching circuit of claim 1, further comprising a signal feedback circuit comprising a first feedback unit and a second feedback unit;
the output end of the first level synchronization unit is connected with the input end of the first feedback unit, and the input end of the first feedback signal line is connected with the output end of the first feedback unit; the output end of the second level synchronization unit is connected with the input end of the second feedback unit, and the input end of the second feedback signal line is connected with the output end of the second feedback unit; the feedback circuit is used for eliminating the overlapping of the first clock enable level synchronous signal and the second clock enable level synchronous signal after synchronization.
3. The clock dynamics switching circuit of claim 1, further comprising an inverter;
the second clock enabling signal line is further connected with the first clock enabling signal line through the phase inverter and is used for inverting a second clock enabling signal on the second clock enabling signal line to obtain the first clock enabling signal.
4. The clock dynamic switching circuit of claim 2, wherein the first level synchronizing unit comprises a first register and a second register, the input terminal of the first register is the input terminal of the first level synchronizing unit, the non-inverting output terminal of the first register is connected to the input terminal of the second register, the non-inverting output terminal of the second register is the output terminal of the first level synchronizing unit, and the first clock signal line is respectively connected to the clock terminals of the first register and the second register;
the second level synchronization unit comprises a third register and a fourth register, the input end of the third register is the input end of the second level synchronization unit, the positive phase output end of the third register is connected with the input end of the fourth register, the positive phase output end of the fourth register is the output end of the second level synchronization unit, and the second clock signal line is respectively connected with the clock ends of the third register and the fourth register.
5. The clock dynamics switching circuit of claim 4, wherein the first feedback unit includes a fifth register, a non-inverting output of the second register is coupled to an input of the fifth register, an input of the first feedback signal line is coupled to an inverting output of the fifth register, and the first clock signal line is further coupled to a clock terminal of the fifth register;
the second feedback unit comprises a sixth register, a positive phase output end of the fourth register is connected with an input end of the sixth register, an input end of the second feedback signal line is connected with an inverted phase output end of the sixth register, and the second clock signal line is further connected with a clock end of the sixth register.
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| CN202022507394.3U CN213122748U (en) | 2020-11-03 | 2020-11-03 | Clock dynamic switching circuit |
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| CN202022507394.3U CN213122748U (en) | 2020-11-03 | 2020-11-03 | Clock dynamic switching circuit |
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Address after: 518000 Room 201, building A, No. 1, Qian Wan Road, Qianhai Shenzhen Hong Kong cooperation zone, Shenzhen, Guangdong (Shenzhen Qianhai business secretary Co., Ltd.) Patentee after: Shenzhen Pengxin Data Technology Co.,Ltd. Address before: 518000 Room 201, building A, 1 front Bay Road, Shenzhen Qianhai cooperation zone, Shenzhen, Guangdong Patentee before: Shenzhen Panhai Data Technology Co.,Ltd. |