CN213041954U - Signal integrity testing device - Google Patents

Abstract

The utility model discloses a signal integrality testing arrangement, including operation calibrator, noise signal generator, the first operating signal end of being connected with this operation calibrator and the noise signal output end of being connected with this noise signal generator, wherein, the operation calibrator includes operation controller and data calibrator, the data calibrator is signal integrality verifier. Therefore, the noise interference signal can be output from the noise signal output end while the control operation is carried out through the first operation signal end, so that the signal integrity of the device under the condition of external noise interference is tested, and the signal integrity is ensured. The testing device can test the signal integrity of the device at any time, the testing operation is simple, and the cost can be saved.

Description

Signal integrity testing device

Technical Field

The utility model relates to a chip field generally, it is specific, relate to a signal integrality testing arrangement.

Background

Signal integrity refers to the quality of a signal on a transmission path, which may be a common metal wire, an optical device, or other medium. A signal having good signal integrity means that it has the voltage level value that it must achieve when it is needed. Poor signal integrity is not caused by a single factor, but is caused by multiple factors in the system design.

Signal integrity is a series of metrics on the quality of an electronic signal. In digital circuits, a series of binary signal streams is represented by a waveform of voltage (or current). However, the signals of nature are analog in nature, not digital, and all are affected by noise, distortion, and loss. In the case of short distances, low bit rates, a simple conductor can faithfully transmit the signal. While long distance, high bit rate signals may degrade signal reliability by a variety of effects if passed over several different conductors, such that the system or device may not function properly. Signal integrity engineering is a task to analyze and mitigate the above mentioned negative effects, and is a very important activity in all levels of electronic packaging and assembly, such as the internal connections of integrated circuits, integrated circuit packaging, printed circuit boards, and the like.

Signal integrity is an important indicator of chip quality and reliability. In practical applications, external noise can affect the signal integrity of the chip or memory, thereby affecting data integrity. The existing signal integrity test generally does not introduce a test flow, only carries out simulation verification in an IC design stage, and can not test the signal integrity of a chip in other stages, thereby seriously affecting the quality of the chip.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a signal integrality testing arrangement to the signal integrality of test device under the external noise interference condition.

The utility model provides a signal integrality testing arrangement, include: the noise signal verifying device comprises a noise signal generator, an operation checker, a noise signal output end connected with the noise signal generator and a first operation signal end connected with the operation checker, wherein the operation checker comprises an operation controller and a data checker, and the data checker is a signal integrity verifier.

Further preferably, the testing device is an MCU.

Further preferably, the device further comprises a device, the device comprises a second operation signal terminal and a test signal terminal, the second operation signal terminal is connected with the first operation signal terminal, and the test signal terminal is connected with the noise signal output terminal.

Further preferably, the device is a memory.

It is further preferred that the noise signal generator comprises a time-varying digital signal generator and a signal converter connected to an output of the time-varying digital signal generator, an output of the signal converter being connected to the noise signal output.

Further preferably, the signal converter is a digital-to-analog converter.

Further preferably, the test signal terminal is a ground terminal.

Further preferably, the memory includes one of Nor Flash, NAND Flash, and Dram.

Further preferably, the first operation signal terminal and the second operation signal terminal are SPIs.

The utility model has the advantages that: the signal integrity testing device comprises a noise signal generator, an operation checker, a noise signal output end connected with the noise signal generator, and a first operation signal end connected with the operation checker, wherein the operation checker comprises an operation controller and a data checker, and the data checker is a signal integrity verifier. The testing device can test the signal integrity of the device at any time or stage so as to ensure the signal integrity; the device simple structure can provide analog noise signal when operating the device, and the test procedure is simple, saves the cost.

Drawings

The technical solution and other advantages of the present invention will become apparent from the following detailed description of the embodiments of the present invention with reference to the accompanying drawings.

Fig. 1 is a signal integrity testing apparatus provided by an embodiment of the present invention;

fig. 2 is a signal integrity testing apparatus according to a further embodiment of the present invention.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the embodiments described are only some embodiments of the invention, and not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by the skilled in the art without creative work belong to the protection scope of the present invention.

Referring to fig. 1, fig. 1 is a signal integrity testing apparatus according to an embodiment of the present invention, the testing apparatus 10 includes: the operation checker 11, the noise signal generator 12, a first operation signal terminal 13 connected with the operation checker 11, and a noise signal output terminal 14 connected with the noise signal generator 12. The operation checker 11 is configured to provide an operation control signal to the first operation signal terminal 13, and may check operation data returned by the first operation signal terminal 13. The noise signal generator 12 is configured to provide a noise signal to a noise signal output 14. The testing device 10 may be an MCU.

In the present embodiment, the operation checker 11 may include an operation controller 112 and a data checker 111. The operation controller 112 is used to perform an operation on an external device, and the data checker 111 is used to receive test data of the external device and check the integrity of the data. The data verifier 111 is a signal integrity verifier, and can verify the integrity of the signal of the external device by comparing preset reference data with test data. If the comparison data are different or the ratio of the comparison result with errors is larger than the set standard, the signal integrity of the external device is poor.

The embodiment of the utility model provides a testing arrangement 10 can send noise interference through noise signal output end 14 at noise signal generator 12 as outside "device" testing arrangement, and operation controller 112 carries out operation control through first operating signal end 13, and data calibrator 111 carries out the data verification to the operation data that outside device execution operation returned, and then verifies the integrality of operation data.

Referring to fig. 2, fig. 2 is a schematic diagram of a signal integrity testing apparatus according to a further embodiment of the present invention. The test apparatus 20 further comprises a device 21, the device 21 may be an electronic device, a semiconductor device, an integrated circuit, etc., the device 21 comprises a second operation signal terminal 22 and a test signal terminal 23, the second operation signal terminal 22 is connected to the first operation signal terminal 13, and the test signal terminal 23 is connected to the noise signal output terminal 14. The first operation signal terminal 13 and the second operation signal terminal 22 are preferably SPIs, which are Serial Peripheral interfaces (Serial Peripheral interfaces), and are high-speed, full-duplex, synchronous communication buses, which can save space and provide convenience for the layout of a PCB.

Therefore, the present embodiment can form two signal paths including the operation signal path 24 and the noise signal path 25, and the two signal paths can simultaneously transmit signals, so that the noise signal generator 12 can be controlled to emit noise interference to the device 21 while the operation checker 11 performs operation control on the device 21. Meanwhile, the operation signal channel 24 may also transmit operation data, specifically, the operation checker 11 performs a functional operation on the device 21, and receives a data signal returned by the device 21 performing the operation through the operation signal channel 24. The verifier 11 is then operated to verify the returned data and obtain a verification result, so that the signal integrity of the device 21 in case of noise interference can be tested.

In this embodiment, the noise signal generator 12 may include a time-varying digital signal generator 121 and a signal converter 122 connected to an output 1211 of the time-varying digital signal generator 121, an output 1221 of the signal converter 122 is connected to the noise signal output terminal 14, and the signal converter 122 may be specifically a digital-to-analog converter. Specifically, the time-varying digital signal generator 121 may generate digital noise signals of different frequencies, and the signal converter 122 converts the digital noise signals into analog noise signals to output the analog noise signals to the device 21.

In this embodiment, the device 21 may be a memory such as Nor Flash, NAND Flash, Dram, or the like. The operation controller 112 may perform read and write operations on the memory. The test apparatus 20 further comprises a data memory to store data for read and write operations. The written data is the reference data, and the read data is the test data. Specifically, the data checker 111 compares the read data with the read data, and when the data written for a plurality of times or within a certain test time T is the same as the read data, for example, "1" is written to read "1" or "0" is written to read "0", it indicates that the tested memory has good signal integrity.

While the operation controller 112 performs read and write operations on the memory, a variety of digital noise signals may be generated by the time-varying digital signal generator 121, and the signal converter 122 converts the variety of digital noise signals into a variety of analog noise signals and transmits them to the memory. For example, during a certain test time T, an analog noise signal with a frequency f1 is generated in the first time period, an analog noise signal with a frequency f2 is generated in the second time period, an analog noise signal with a frequency f3 is generated in the third time period, and analog noise signals with different frequencies are generated to generate different noise interferences on the test signal terminal 23.

In the actual application scenario of the chip, noise interference to the ground terminal (GND) is likely to occur, so in this embodiment, the test signal terminal 23 may be GND, and the signal output terminal 14 is connected in series with GND, so that the influence of the noise interference of GND on the signal integrity of the memory can be tested. If the duty ratio of the read data and the write data verified by the data verifier 111 is greater than a set criterion (e.g., 5%), the GND is disturbed by noise, and the memory has poor signal integrity. If the read data and the write data verified by the data verifier 111 are the same, i.e. the data has integrity, within a certain test time T, the memory has good signal integrity.

The embodiment of the utility model provides a signal integrality testing arrangement 20, this testing arrangement 20 are including operation calibrator 11 and noise signal generator 12, and wherein operation controller 112 carries out the control operation to device 21 through first operation signal end 13, and data calibrator 111 verifies data. The operation controller 112 performs a control operation, and at the same time, the time-varying digital signal generator 121 generates digital noise with different frequencies, the digital noise is converted into an analog noise signal by the signal converter 122, and then a noise interference signal is input to the device 21 through the noise signal output terminal 14, so that the testing apparatus 20 can test the signal integrity of the device 21 under the external noise interference condition. The test device 20 can test the signal integrity of the device at any time or stage to ensure the signal integrity; the testing device 20 has a simple structure, is simple in testing operation, and can save cost.

The above description of the embodiments is only used to help understand the technical solution and the core idea of the present invention; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present invention in its various embodiments.

Claims (9)

1. A signal integrity testing device, comprising: the noise signal verifying device comprises a noise signal generator, an operation checker, a noise signal output end connected with the noise signal generator and a first operation signal end connected with the operation checker, wherein the operation checker comprises an operation controller and a data checker, and the data checker is a signal integrity verifier.

2. The signal integrity testing device of claim 1, wherein the testing device is an MCU.

3. The signal integrity testing device of claim 1, further comprising a device including a second operational signal terminal and a test signal terminal, the second operational signal terminal being connected to the first operational signal terminal, the test signal terminal being connected to the noise signal output terminal.

4. The signal integrity testing device of claim 3, wherein the device is a memory.

5. The signal integrity testing device of claim 1, wherein the noise signal generator comprises a time-varying digital signal generator and a signal converter coupled to an output of the time-varying digital signal generator, an output of the signal converter being coupled to the noise signal output.

6. The signal integrity testing device of claim 5, wherein the signal converter is a digital-to-analog converter.

7. The signal integrity testing device of claim 3, wherein the test signal terminal is a ground terminal.

8. The signal integrity testing device of claim 4, wherein the memory comprises one of Nor Flash, NAND Flash, and Dram.

9. The signal integrity testing device of claim 3, wherein the first and second operating signal terminals are SPIs.

Images