CN212934665U

CN212934665U - Display panel

Info

Publication number: CN212934665U
Application number: CN202022056054.3U
Authority: CN
Inventors: 陈宇怀
Original assignee: Fujian Huajiacai Co Ltd
Current assignee: Fujian Huajiacai Co Ltd
Priority date: 2020-09-18
Filing date: 2020-09-18
Publication date: 2021-04-09
Anticipated expiration: 2030-09-18

Abstract

The utility model discloses a display panel, include: a buffer layer is arranged on the surface of the substrate; a first metal reflecting layer is arranged on the buffer layer and comprises a first side wall and a second side wall which are inclined to the surface of the substrate, an included angle between the first side wall and the second side wall is 90 degrees, and the first metal reflecting layer is used for reflecting light; a thin film transistor is arranged on the buffer layer; a second insulating layer is arranged on the thin film transistor and the first metal reflecting layer; an anode is arranged on the second insulating layer; a pixel defining layer is arranged on the anode, and a first hole is arranged on the pixel defining layer; a first light emitting layer disposed in the first aperture; a cathode is disposed on the pixel defining layer. The technical scheme can improve the reflection efficiency, the display effect and the visual angle of the display panel.

Description

Display panel

Technical Field

The utility model relates to a display panel field especially relates to a display panel.

Background

A dual-sided display is a device capable of displaying images on both sides of a display device, and has a wide range of applications, for example, applications to the communication industry, airports, digital cameras, video cameras, electronic products, and the like. The traditional double-sided display panel is mostly formed by oppositely placing two display panels, so that one display panel can be seen from two sides respectively. Although the double-sided display is achieved, the two single-sided display panels are overlapped, and the defects of large occupied space, large power consumption and the like are inevitably brought. The novel double-sided display panel can realize double-sided display only by using one display panel, and has the advantages of thinner panel, lower power consumption and the like compared with the traditional double-sided display device, so that the novel double-sided display panel can be applied to small electronic products.

For example, CN201811037109.7, entitled display panel, method for manufacturing the same, and display device, the metal reflective layer disposed on one side of the light emitting layer is mostly of a planar or concave-convex structure, and the effect of the metal reflective layer of the planar or concave-convex structure for reflecting light is still insufficient, so that the visual effect and the display effect of the display panel are affected.

SUMMERY OF THE UTILITY MODEL

Therefore, it is desirable to provide a display panel that solves the problem of insufficient efficiency of the metal reflective layer of the display panel to reflect light.

To achieve the above object, the present embodiment provides a display panel including:

a buffer layer is arranged on the surface of the substrate;

a first metal reflection layer is arranged on the buffer layer and comprises a first side wall and a second side wall which are inclined to the surface of the substrate, an included angle between the first side wall and the second side wall is 90 degrees, an opening formed between the first side wall and the second side wall faces upwards, and the first side wall and the second side wall are used for reflecting incident light;

a thin film transistor is arranged on the buffer layer and is positioned on one side of the first metal reflecting layer;

a second insulating layer is arranged on the thin film transistor and the first metal reflecting layer;

an anode is arranged on the second insulating layer and is a light-transmitting anode, and the anode is connected with a source electrode or a drain electrode of the thin film transistor through a hole in the second insulating layer;

a pixel defining layer is arranged on the anode, and a first hole is arranged on the pixel defining layer;

a first light-emitting layer is arranged in the first hole and is positioned above the first metal reflecting layer;

and a cathode is arranged on the pixel defining layer, is a light-transmitting cathode and is connected with the first light-emitting layer.

Further, the LED lamp also comprises a second luminous layer and a second metal layer reflecting layer;

the pixel defining layer is provided with a second hole, and the second light emitting layer is arranged in the second hole; the metal film further comprises a second metal reflecting layer;

the cathode is provided with a second metal reflecting layer, the second metal reflecting layer is positioned above the second light emitting layer and positioned on one side of the first light emitting layer, the second metal reflecting layer is used for reflecting light of the second light emitting layer, and a structure right below the second light emitting layer is a light transmitting structure.

Further, the projection of the conductive channel of the thin film transistor is located in the projection of the second metal reflection layer, and the projection direction is perpendicular to the substrate.

Further, the structure of the second metal reflective layer is the same as that of the first metal reflective layer.

Further, the second metal layer and the cathode are respectively located in different areas of the same layer.

Further, the thin film transistor includes a gate electrode, a first insulating layer, an active layer, a source electrode, and a drain electrode;

the grid electrode is arranged on the buffer layer;

the first insulating layer is arranged on the grid electrode;

the active layer is arranged on the first insulating layer and is positioned above the grid electrode;

the source electrode and the drain electrode are arranged on the active layer;

the second insulating layer is arranged on the source electrode and the drain electrode and used for protecting the thin film transistor below the second insulating layer.

Further, the light-transmitting capacitor comprises a lower plate and an upper plate;

the lower polar plate is arranged on the buffer layer and is positioned on one side of the grid;

the upper polar plate is arranged on the first insulating layer and connected with a source electrode or a drain electrode of the thin film transistor, and the upper polar plate is arranged above the lower polar plate.

Further, the second insulating layer includes a passivation layer and a planarization layer;

the passivation layer is arranged on the source electrode and the drain electrode;

the planarization layer is disposed on the passivation layer;

the flat layer is provided with a hole on the second insulating layer, the hole on the second insulating layer penetrates through the flat layer and the passivation layer, and the bottom of the hole on the second insulating layer is the source electrode or the drain electrode.

Further, the first metal reflection layer further comprises a bottom wall parallel to the surface of the substrate, and the bottom wall is arranged between the first side wall and the second side wall.

Different from the prior art, the first metal reflecting layer with the first and second perpendicular side walls reflects light by using the principle of vertical mirror reflection, so that incident light is reflected in a direction perpendicular to the surface of the substrate, the first metal reflecting layer reflects light of the first light emitting layer with high efficiency, a top-emitting or bottom-emitting display panel is formed, and the reflection efficiency, the display effect and the visual angle of the display panel can be improved.

Drawings

FIG. 1 is a schematic cross-sectional view illustrating a buffer layer formed on a substrate according to the present embodiment;

FIG. 2 is a schematic cross-sectional view illustrating a transparent conductive layer and a metal film layer formed on a substrate according to the present embodiment;

FIG. 3 is a schematic cross-sectional view illustrating the exposure of a photoresist on a substrate using a half-tone mask according to the present embodiment;

FIG. 4 is a schematic diagram of a structure of light transmittance on the halftone mask according to the present embodiment;

FIG. 5 is a schematic cross-sectional view illustrating the etching of a metal layer and a transparent conductive layer uncovered by a photoresist on a substrate according to the present embodiment;

FIG. 6 is a schematic cross-sectional view illustrating the removal of the photoresist on the lower plate region on the substrate according to the present embodiment;

FIG. 7 is a schematic cross-sectional view illustrating the substrate with the metal film layer removed and the transparent conductive layer remaining thereon;

fig. 8 is a schematic cross-sectional structure diagram of the gate, the bottom plate and the first metal reflective layer in this embodiment;

FIG. 9 is a schematic cross-sectional view of a first metal reflective layer of the first structure according to the present embodiment;

FIG. 10 is a schematic cross-sectional view of a first metal reflective layer of a second structure according to the present embodiment;

FIG. 11 is a schematic cross-sectional view of a prismatic vertical structure of a buffer layer according to the present embodiment;

FIG. 12 is a schematic cross-sectional view illustrating a first insulating layer formed on a substrate according to the present embodiment;

FIG. 13 is a schematic cross-sectional view illustrating an active layer formed on a substrate according to the present embodiment;

FIG. 14 is a schematic cross-sectional view illustrating the fabrication of a source, a drain and an upper plate on a substrate according to this embodiment;

FIG. 15 is a schematic cross-sectional view illustrating a second insulating layer formed on a substrate according to the present embodiment;

FIG. 16 is a schematic cross-sectional view illustrating the fabrication of a passivation layer and a planarization layer on a substrate according to the present embodiment;

FIG. 17 is a schematic cross-sectional view illustrating an anode fabricated on a substrate according to the present embodiment;

FIG. 18 is a schematic cross-sectional view illustrating a pixel defining layer formed on a substrate according to the present embodiment;

fig. 19 is a schematic cross-sectional view illustrating a first light-emitting layer and a second light-emitting layer formed on a substrate according to the present embodiment;

FIG. 20 is a schematic cross-sectional view illustrating a cathode fabricated on a substrate according to this embodiment;

FIG. 20a is a schematic cross-sectional view illustrating the fabrication of a first cathode and a second cathode on a substrate according to this embodiment;

FIG. 21 is a schematic cross-sectional view illustrating a second metal reflective layer formed on a substrate according to the present embodiment;

fig. 22 is a schematic structural diagram of a dual-sided display panel according to the present embodiment;

fig. 23 is a schematic cross-sectional structure diagram of the first metal reflective layer reflecting light of the first light-emitting layer and the second metal reflective layer reflecting light of the second light-emitting layer in this embodiment;

FIG. 24 is a schematic cross-sectional view illustrating a cover plate covering a substrate according to the present embodiment;

fig. 25 is a schematic cross-sectional view illustrating a second metal reflective layer formed on a cover plate according to the present embodiment.

Description of reference numerals:

1. a substrate;

2. a buffer layer; 21. a prismatic vertical structure;

3. a transparent conductive layer;

4. a metal film layer;

5. a thin film transistor; 51. a gate electrode; 52. an active layer; 53. a source electrode; 54. a drain electrode;

6. a first metal reflective layer; 61. a first side wall; 62. a second side wall;

7. a capacitor; 71. a lower polar plate; 72. an upper polar plate;

8. a first insulating layer;

9. a second insulating layer; 91. a passivation layer; 92. a planarization layer;

10. an anode;

11. a pixel defining layer; 111. a first hole; 112. a second hole;

12. a first light-emitting layer;

13. a second light emitting layer;

14. a cathode; 141. a first cathode; 142. a second cathode;

15. a second metal reflective layer;

16. a cover plate;

PR, photo resist.

Detailed Description

To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.

Referring to fig. 1 to 25, the present embodiment provides a display panel, which includes the following steps: manufacturing a buffer layer on the surface of the substrate; specifically, a buffer layer 2 is formed on the surface of the substrate 1 by chemical vapor deposition to plate a buffer layer material, and the structure is shown in fig. 1. The buffer layer material may be Polyethylene terephthalate (abbreviated as PET), Polyethylene naphthalate (abbreviated as PEN), Polyimide (abbreviated as PI), an organic photosensitive material, silicon oxide (SiOx), silicon nitride (SiNx), aluminum oxide, titanium oxide, or the like, which have similar characteristics. On the one hand, the buffer layer 2 is used for bearing a first metal reflecting layer 6 for reflecting action; on the other hand, the buffer layer 2 is used to absorb external impact and reduce external force applied to the substrate 1 itself.

Manufacturing a plurality of prismatic vertical structures 21 on the buffer layer 2, wherein the prismatic vertical structures 21 on the buffer layer 2 are covered by the first metal reflecting layer 6; specifically, a plurality of grooves are etched by developing, etching or nano-imprinting technology, and a plurality of prismatic vertical structures are formed on the buffer layer. A prismatic vertical structure comprises a first side wall and a second side wall, wherein the first side wall and the second side wall are inclined to the surface of a substrate, an included angle between the first side wall and the surface of the substrate is 45 degrees, an included angle between the first side wall and the second side wall is 90 degrees, and the structure is shown in figure 11.

It should be noted that the cross section of the etched groove is triangular, that is, the top of the first sidewall is connected with the top of the second sidewall, so that the prismatic vertical structure is a triangular prism, the buffer layer comprises a plurality of prismatic vertical structures of such triangular prisms, two adjacent prismatic vertical structures are connected with each other, and the structure of the first metal reflective layer 6 covering the shape is as shown in fig. 9; for example, the etched groove is trapezoidal, a space is also formed between two adjacent prismatic vertical structures, a space is formed between the top of the first side wall (the waist of the trapezoid) and the top of the second side wall (the waist of the trapezoid), a wall parallel to the surface of the substrate is formed between the top of the first side wall and the top of the second side wall, and the structure of the first metal reflective layer 6 covering the shape is as shown in fig. 10.

Manufacturing a grid 51, a lower electrode plate 71 of the transparent capacitor 7 and a first metal reflecting layer 6; specifically, a transparent conductive layer material and a metal film layer material are sequentially plated in an evaporation or sputtering manner, and a transparent conductive layer 3 and a metal film layer 4 are formed on the substrate, and the structure is shown in fig. 2. The transparent conductive layer 3 is disposed on the buffer layer, and the metal film layer 4 is disposed on the transparent conductive layer 3. The transparent conductive layer is made of Indium Tin Oxide (ITO), zinc oxide (ZnO), tin oxide (SnO2), carbon nanotube or graphene, and the metal film is made of one or more of aluminum, molybdenum, titanium, nickel, copper, silver, chromium and other metals with excellent conductivity, and alloys.

Next, a layer of photoresist PR is coated, and exposure is performed using a half-color mask, so that the light transmittance of the portion of the half-color mask aligned with the lower plate 71 region of the capacitor is 50%, the light transmittance of the portion of the half-color mask aligned with the gate 51 region is 0%, the light transmittance of the portion of the half-color mask aligned with the first metal reflective layer 6 region is 0%, and the light transmittance of the remaining portion of the half-color mask is 100%, which is shown in fig. 3 (only the capacitor region and the gate region are shown in fig. 3). After exposure, developing by using a developing solution, reserving the photoresist on the first metal reflecting layer region, reserving the photoresist on the gate region, reserving the photoresist on the lower polar plate region, wherein the thickness of the photoresist PR on the lower polar plate region is smaller than that of the photoresist PR on the gate region, and removing all the photoresist on the rest parts. It should be noted that the photoresist on the bottom plate region is thinned, i.e. the photoresist in the 50% transmittance region is thinner than the photoresist in the 0% transmittance region, and the structure is shown in fig. 4.

After the development, the metal film layer and the transparent conductive layer which are not covered by the photoresist are etched by using the photoresist as a mask, and the structure is shown in fig. 5. The photoresist on the lower plate region is removed by ashing, and the structure is shown in fig. 6. Because the thickness of the photoresist on the first metal reflecting layer region and the gate region is greater than that of the photoresist on the lower plate region, after ashing treatment, the photoresist on the first metal reflecting layer region and the gate region can be thinned but not removed, and the metal film layer below can be protected.

After the ashing treatment, the metal film layer on the lower plate region is removed by controlling the etching time or the selectivity of the etching solution, and the transparent conductive layer on the lower plate region is retained, which has the structure shown in fig. 7. Finally, removing all the photoresist, forming a lower plate on the lower plate region, forming a gate on the gate region, and forming a first metal reflective layer on the first metal reflective layer region, wherein the structure is shown in fig. 8. The lower plate 71 includes a transparent conductive layer, so that the lower plate 71 is a transparent lower plate 71, and light can pass through the transparent lower plate 71. The first metal reflective layer 6 and the gate 51 each include a transparent conductive layer 3 and a metal film layer 4. The lower plate 71 may be connected to the gate 51, and the lower plate 71 or the gate 51 is located at one side of the first metal reflective layer 6.

The first metallic reflective layer 6, which comprises first and

second sidewalls

61, 62 inclined to the surface of the substrate, covers the prismatic vertical structures 21 on the buffer layer. The first side wall 61 of the first metal reflecting layer is attached to the first side wall of the buffer layer, and the second side wall 62 of the first metal reflecting layer is attached to the second side wall of the buffer layer. The included angle between the first side wall and the surface of the substrate is 45 degrees, the included angle between the first side wall and the second side wall is 90 degrees, and an opening formed between the first side wall and the second side wall faces upwards.

In a first configuration, the cross-section of one set of the first and second sidewalls is triangular, as shown in fig. 9; in the second structure, the cross section of one set of the first side wall and the second side wall is trapezoidal, and the first metal reflective layer further includes a wall parallel to the surface of the substrate, and the structure is shown in fig. 10. When the first light emitting layer above emits light onto the first sidewall, the direction of the incident light is perpendicular to the surface of the substrate, after the incident light is reflected by the first sidewall, the direction of the incident light is parallel to the surface of the substrate, and the incident angle between the incident light and the second sidewall is also 45 degrees, then after the second sidewall reflects the incident light, the direction of the incident light is parallel to the surface of the substrate, and the structure is shown in fig. 23. The first metal reflective layer can reflect the incident light in a direction perpendicular to the substrate surface, so that the first metal reflective layer reflects the light of the first light emitting layer with high efficiency, and a top emission display panel is formed, and the structure is shown in fig. 22. The first metal reflecting layer can improve the reflection efficiency, the display effect and the visual angle of the display panel.

It should be noted that the included angle between the first sidewall and the substrate surface is not only 45 degrees, but also may be any other degrees, such as 30 degrees, 50 degrees, 80 degrees, and the like.

Preferably, a projection of the first light emitting layer is located within a projection of the first metal reflecting layer, and the projection direction is perpendicular to the substrate. So that the light emitted from the first light-emitting layer can be totally reflected by the first metal reflective layer to a direction away from the substrate.

In order to isolate the contact between the metals, a first insulating layer 8 is manufactured; specifically, a first insulating layer is formed on the buffer layer, the gate electrode, the first metal reflective layer, and the bottom plate by chemical vapor deposition of insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), aluminum oxide, or titanium oxide, and the structure is as shown in fig. 12. The first insulating layer covers the buffer layer, the grid electrode, the first metal reflecting layer and the lower polar plate, and short circuit formed by connection of metal and other circuits is avoided.

Next, the active layer 52 is fabricated; the active layer is located above the gate, the active layer is made of materials such as polysilicon, oxide semiconductor, graphene, carbon nanotube, organic semiconductor, and the like, and the structure is shown in fig. 13. After the active layer 52 is manufactured, manufacturing a source electrode 53, a drain electrode 54 and an upper electrode plate 72; this step is the same as the step of fabricating the first metal reflective layer, the gate electrode and the bottom plate, and similarly, the transparent conductive layer and the metal film layer are sequentially fabricated and then etched, which is not repeated herein, and the structure is shown in fig. 14. The active layer region between the source electrode 53 and the drain electrode 54 is a conductive channel of a thin film transistor. Then, the source electrode 53 is connected to the active layer 52, and the drain electrode 54 is connected to the active layer 52. The source electrode 53, the drain electrode 54, the active layer 52, the gate electrode 51, and a portion of the first insulating layer 8 form a Thin Film Transistor 5 (TFT), which functions as a switch to turn on a circuit.

The source electrode and the drain electrode comprise a transparent conductive layer and a metal film layer, and the upper electrode plate comprises a transparent conductive layer. The upper polar plate is connected with the source electrode or the drain electrode, and the upper polar plate is arranged above the lower polar plate. The upper polar plate is also transparent, the upper polar plate and the lower polar plate are parallel to each other, and a first insulating layer between the upper polar plate and the lower polar plate is used as a dielectric layer of the capacitor to play a role in isolating the electric connection between the upper polar plate and the lower polar plate.

In order to protect the underlying thin film transistor, a second insulating layer 9 is formed; specifically, the passivation layer 91 is formed on the thin film transistor (source, drain, and active layers) by first plating an insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), aluminum oxide, or titanium oxide by chemical vapor deposition. Then, an insulating material such as polyimide, silicon nitride (SiNx) or silicon oxide (SiOx) is first plated by chemical vapor deposition, and a planarization layer 92 is formed on the passivation layer 91, as shown in fig. 16. It is noted that the passivation layer serves to isolate the electrical connections between the metals and to avoid short circuits. The upper surface of the flat layer is a plane, and the flat layer has the effect of flattening the surface inner section difference caused by various different layers of patterns on the substrate of the display device, so that the subsequent film layers can be well overlapped, and the display effect is improved. Or in some embodiments, by increasing the thickness of the passivation layer, it can also act as a planarization layer to spread the film layer with high and low unevenness on the substrate, as shown in fig. 15.

Etching a hole in the second insulating layer to connect the anode and the thin film transistor; specifically, a photoresist is coated and patterned, i.e., exposed and developed, to open the portions to be etched. Then, a photoresist is used as a mask to etch the planarization layer to the source or the drain, and a hole on the second insulating layer is formed, as shown in fig. 15 or 16. And after the hole on the second insulating layer is manufactured, removing the photoresistance. The hole in the second insulating layer penetrates through the flat layer and the passivation layer, the bottom of the hole in the second insulating layer is the source electrode or the drain electrode, and if the anode is connected with the source electrode, the bottom of the hole in the second insulating layer is the source electrode; if the anode is to be connected to the drain, the bottom of the hole in the second insulating layer is the drain.

Next, an anode 10 is fabricated, and the anode 10 is connected to the source 53 or the drain 54 of the thin film transistor 5 through a hole in the second insulating layer, as shown in fig. 17. Preferably, the material of the anode is Indium Tin Oxide (ITO), that is, the anode is a light-transmitting anode, so that light can penetrate through the anode. Then, a pixel defining layer is fabricated, the pixel defining layer being disposed on the anode and the planarization layer. Meanwhile, a first hole 111 and a second hole 112 are formed in the pixel defining layer 11, and the bottom of the first hole 111 and the bottom of the second hole 112 are both the anode 10. The first hole is located above the first metal reflective layer, and the second hole is located at one side of the first hole (or the first metal reflective layer), as shown in fig. 18. Then, a first light emitting layer 12 is formed in the first hole, and a second light emitting layer 13 is formed in the second hole, as shown in fig. 19. The first light emitting layer 12 and the second light emitting layer 13 each include a hole injection layer HIL, a hole transport layer HTL, an organic light emitting layer EM, an electron transport layer ETL, and an electron injection layer EIL. The first light emitting layer and the second light emitting layer may emit light required for the display panel to the outside, but these are too dispersed, so that the first metal reflective layer and the second metal reflective layer are required for regulation.

A cathode 14 is formed on the pixel defining layer, and the cathode 14 covers the first light emitting layer 12 in the first hole and the second light emitting layer 13 in the second hole, as shown in fig. 20. The cathode may be a magnesium silver alloy or the like, such that the cathode is a light-transmissive cathode. Finally, a second metal reflective layer 15 is formed on the cathode, the second metal reflective layer 15 is located above the second light-emitting layer 13, the second metal reflective layer 15 is located on one side of the first light-emitting layer 12, and the second metal reflective layer is used for reflecting light of the second light-emitting layer to the substrate, and the structure is as shown in fig. 21. The second light emitting layer is bottom emitting (please refer to the upward and downward arrow in fig. 21), the first light emitting layer is top emitting (please refer to the upward arrow in fig. 21), and the display panel has a double-sided display function, and the structure is shown in fig. 22. Each RGB sub-pixel has two light emitting modes of top light emitting and bottom light emitting at the same time, and is controlled by the same group of TFT drive circuit. Preferably, the first light-emitting layer and the second light-emitting layer do not interfere with each other when top emission or bottom emission is realized.

The conductive channel of a thin film transistor is affected by light, resulting in performance anomalies at some point. Preferably, a projection of the conductive channel of the thin film transistor is located in a projection of the second metal reflective layer, the projection direction is perpendicular to the substrate, and the structure is as shown in fig. 21. The second metal reflecting layer shields ambient light, protects a conducting channel of the thin film transistor from being influenced by the ambient light, and is favorable for improving the working stability of the thin film transistor. It should be noted that the structure right below the second light emitting layer is a light-transmitting structure, so that light can transmit through the structure right below the second light emitting layer.

In some embodiments, the first light emitting layer and the second light emitting layer are not fabricated simultaneously, and the cathode is not fabricated simultaneously, and the process flow is as follows: second light-emitting layer 13 (bottom emission) → second cathode 142 (opaque and having high reflectance) → first light-emitting layer 12 (top emission) → first cathode 141 (light-transmitting), the structure is as shown in fig. 20 a. Wherein the first cathode 141 and the second cathode 142 constitute the cathode 14 described above. The first light-emitting layer and the second light-emitting layer are manufactured separately, so that the performance optimization of the light-emitting device is facilitated. Preferably, a projection of the conductive channel of the thin film transistor is located within a projection of the second cathode, and the projection direction is perpendicular to the substrate.

After the cathode and the second metal reflective layer are manufactured, the cover plate 16 is covered on the cathode 14 and the second metal reflective layer 15, and the second metal reflective structure is a planar structure, as shown in fig. 21 and 24. Preferably, the second metal reflective layer has the same structure as the first metal reflective layer, and has a sidewall inclined with respect to the surface of the substrate. At this time, a buffer layer with a prismatic vertical structure is also arranged on the cover plate, the second metal reflective layer covers the buffer layer with the prismatic vertical structure, an insulating layer covering the second metal reflective layer may also be arranged on one side of the second metal reflective layer away from the buffer layer, and the cover plate is covered on the cathode through the second metal reflective layer, and the structure is as shown in fig. 25.

The present embodiment also provides a display panel, including: a buffer layer 2 is provided on the surface of the substrate 1, and the structure is shown in fig. 1. The buffer layer 2 is made of a material having similar characteristics, such as Polyethylene terephthalate (abbreviated PET), Polyethylene naphthalate (abbreviated PEN), Polyimide (abbreviated PI), an organic photosensitive material, silicon oxide (SiOx), silicon nitride (SiNx), aluminum oxide, or titanium oxide. On one hand, the buffer layer is used for bearing the first metal reflecting layer; on the other hand, the buffer layer is used for absorbing external impact and reducing external force applied to the substrate.

A plurality of prismatic vertical structures 21 are provided on the buffer layer 2. A prismatic vertical structure comprises a first side wall and a second side wall, wherein the first side wall and the second side wall are inclined to the surface of a substrate, an included angle between the first side wall and the surface of the substrate is 45 degrees, an included angle between the first side wall and the second side wall is 90 degrees, and the structure is shown in figure 11. It is noted that the top of the first sidewall is connected to the top of the second sidewall, so that the prismatic vertical structure is a triangular prism, the buffer layer includes a plurality of prismatic vertical structures of such triangular prisms, two adjacent prismatic vertical structures are connected to each other, and the structure of the first metal reflective layer covering the shape is as shown in fig. 9; and a space is also formed between two adjacent prismatic vertical structures, a space is formed between the top of the first side wall and the top of the second side wall, a wall parallel to the surface of the substrate is formed between the top of the first side wall and the top of the second side wall, and the first metal reflecting layer covering the shape is structured as shown in FIG. 10.

Be provided with first metal reflection stratum 6 on buffer layer 2, first metal reflection stratum 6 is including the first lateral wall 61 and the second lateral wall 62 of the surface of slope in the base plate, first lateral wall 61 with the contained angle between the surface of base plate is 45 degrees, the contained angle between first lateral wall 61 and the second lateral wall 62 is 90 degrees, the opening that forms between first lateral wall and the second lateral wall is upwards, first metal reflection stratum 6 is used for reflecting the light of first luminescent layer. The first metal reflective layer 6 covers the prismatic vertical structures 21 on the buffer layer. The first side wall 61 of the first metal reflecting layer is attached to the first side wall of the buffer layer, and the second side wall 62 of the first metal reflecting layer is attached to the second side wall of the buffer layer.

Preferably, the projection of the first light emitting layer 12 is located within the projection of the first metal reflecting layer 6, and the projection direction is perpendicular to the substrate. So that the light emitted from the first light-emitting layer can be totally reflected by the first metal reflective layer to a direction away from the substrate.

And a thin film transistor 5 is arranged on the buffer layer, and the thin film transistor 5 is positioned on one side of the first metal reflecting layer. Meanwhile, a capacitor 7 may be provided at one side of the thin film transistor 5. The thin film transistor includes a gate electrode 51, a first insulating layer 8, an active layer 52, a source electrode 53, and a drain electrode 54.

The gate 51 is disposed on the buffer layer, the lower plate 71 of the capacitor 7 is disposed on the buffer layer, the lower plate 71 can be selectively connected to the gate 51 according to the situation of the compensation circuit, and the lower plate 71 or the gate 51 is located on one side of the first metal reflective layer 6, as shown in fig. 8. Preferably, the lower plate 71 includes a transparent conductive layer 3, so that the lower plate 71 is a transparent lower plate 71, and light can pass through the transparent lower plate 71. The first metal reflective layer 6 and the gate 51 each include a transparent conductive layer 3 and a metal film layer 4. The metal film layer 4 of the gate electrode 51 (or the first metal reflective layer 6) is disposed on the transparent conductive layer 3. The transparent conducting layer of the lower polar plate, the transparent conducting layer of the first metal reflecting layer and the transparent conducting layer of the grid electrode are arranged on the same layer.

The transparent conductive layer is made of Indium Tin Oxide (ITO), zinc oxide (ZnO), tin oxide (SnO2), carbon nanotube or graphene, and the metal film is made of one or more of aluminum, molybdenum, titanium, nickel, copper, silver, chromium and other metals with excellent conductivity, and alloys.

In order to isolate the contact between the metals, the first insulating layer 8 is arranged on the grid; the first insulating layer 8 covers the buffer layer 2, the gate 51, the first metal reflective layer 6 and the bottom plate 71 to prevent the metal from being connected with other circuits to form a short circuit, and the structure is shown in fig. 12. The first insulating layer is made of insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), aluminum oxide, or titanium oxide.

The active layer 52 is arranged on the first insulating layer, the active layer 52 is located above the gate electrode 51, and the structure is as shown in fig. 13; the active layer material is polysilicon, oxide semiconductor, graphene, carbon nanotube, organic semiconductor, etc.

The source electrode 53 and the drain electrode 54 are disposed on the active layer 52; the source electrode 53 is connected to the active layer 52, and the drain electrode 54 is connected to the active layer 52, as shown in fig. 14. The source electrode 53, the drain electrode 54, the active layer 52, the gate electrode 51, and a portion of the first insulating layer form a Thin Film Transistor 5 (TFT), and the Thin Film Transistor 5 functions as a switch to turn on a circuit. The active layer region between the source and the drain is the conductive channel of the thin film transistor 5.

The upper plate 72 is disposed on the first insulating layer 8, and the upper plate 72 is connected to the source electrode 53 or the drain electrode 54 to communicate the capacitor with the thin film transistor. The upper plate 72 is above the lower plate 71. Preferably, the source electrode and the drain electrode both include a transparent conductive layer and a metal film layer, the upper electrode plate includes a transparent conductive layer, and the transparent conductive layers of the source electrode and the drain electrode and the transparent conductive layer of the upper electrode plate are disposed in the same layer. The upper polar plate is connected with the source electrode or the drain electrode, and the upper polar plate is arranged above the lower polar plate. The upper polar plate is also transparent, the upper polar plate and the lower polar plate are parallel to each other, and a first insulating layer between the upper polar plate and the lower polar plate is used as a dielectric layer of the capacitor to play a role in isolating the electric connection between the upper polar plate and the lower polar plate.

In order to protect the underlying thin film transistor, a second insulating layer 9 is provided on the thin film transistor and the first metal reflective layer; the second insulating layer 9 is used for protecting the thin film transistor below; the second insulating layer 9 includes a passivation layer 91 and a planarization layer 92, which are sequentially disposed, and the structure is as shown in fig. 16. The passivation layer 91 is disposed on the source electrode 53 and the drain electrode 54, and the passivation layer 91 serves to isolate electrical connections between metals and prevent short circuits from being formed. The planarization layer 92 is disposed on the passivation layer 91, and an upper surface of the planarization layer is a plane. The flat layer has the effect of flattening the surface inner section difference caused by various different layer patterns on the substrate of the display device, thereby facilitating the good superposition of subsequent films and improving the display effect. Or in some embodiments, by increasing the thickness of the passivation layer, it can also act as a planarization layer to spread the film layer with high and low unevenness on the substrate, as shown in fig. 15.

The passivation layer is made of an insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), aluminum oxide, or titanium oxide, and the planarization layer is made of an insulating material such as polyimide, silicon nitride (SiNx), or silicon oxide (SiOx).

Note that a hole in the second insulating layer is formed in the planarization layer, the hole in the second insulating layer penetrates through the planarization layer and the passivation layer, and a bottom of the hole in the second insulating layer is the source electrode or the drain electrode, which is shown in fig. 15 or fig. 16.

A light-transmitting anode 10 is arranged on the second insulating layer, and the anode 10 is connected with the source 53 or the drain 54 of the thin film transistor through a hole on the second insulating layer, and the structure is shown in fig. 17; the hole in the second insulating layer penetrates through the flat layer and the passivation layer, the bottom of the hole in the second insulating layer is the source electrode or the drain electrode, and if the anode is connected with the source electrode, the bottom of the hole in the second insulating layer is the source electrode; if the anode is to be connected to the drain, the bottom of the hole in the second insulating layer is the drain.

A pixel defining layer 11 is disposed on the anode, and a first hole 111 is disposed on the pixel defining layer; the bottom of the first hole 111 is the anode 10. A first light-emitting layer 12 is disposed in the first hole 111, and the first light-emitting layer 12 is located above the first metal reflective layer 6, as shown in fig. 18 and 19.

In some embodiments, the display panel is a double-sided display panel, the pixel defining layer 11 is provided with a second hole 112, and the bottom of the second hole 112 is the anode 10. The second hole 112 is located at one side of the first hole 111 (or the first metal reflective layer), and the structure is as shown in fig. 18 and 19. Each RGB sub-pixel has two light emitting modes of top light emitting and bottom light emitting at the same time, and is controlled by the same group of TFT drive circuit.

The first light emitting layer 12 and the second light emitting layer 13 each include a hole injection layer HIL, a hole transport layer HTL, an organic light emitting layer EM, an electron transport layer ETL, and an electron injection layer EIL. The first light emitting layer and the second light emitting layer may emit light required for the display panel to the outside, but these are too dispersed, so that the first metal reflective layer and the second metal reflective layer are required for regulation.

A light-transmitting cathode 14 is disposed on the pixel defining layer 11, and the cathode 14 covers the first light-emitting layer 12 in the first hole and the second light-emitting layer 13 in the second hole, as shown in fig. 20. The cathode may be a magnesium silver alloy or the like, such that the cathode is a light-transmissive cathode.

A second metal reflective layer 15 is disposed on the cathode, the second metal reflective layer 15 is located above the second light-emitting layer 13, the second metal reflective layer 15 is located on one side of the first light-emitting layer 12, and the second metal reflective layer 15 is configured to reflect light of the second light-emitting layer to the substrate, and the structure is shown in fig. 21. The second light emitting layer 13 is bottom emitting (please refer to the arrow in the upward direction in fig. 21), the first light emitting layer 12 is top emitting (please refer to the arrow in the upward direction in fig. 21), and the display panel has a double-sided display function, and the structure is shown in fig. 22. Preferably, the first light-emitting layer and the second light-emitting layer do not interfere with each other when top emission or bottom emission is realized.

Or in some embodiments the cathode may replace the function of the second reflective metal layer. The cathode 14 includes a first cathode 141 and a second cathode 142; the first cathode 141 is a light-transmitting first cathode, and the first cathode 141 covers the first light-emitting layer 12; the second cathode 142 is a light-shielding and reflective second cathode 142, the second cathode 142 covers the second light-emitting layer 13, and the second cathode 142 is used for reflecting light of the second light-emitting layer 13, and the structure is as shown in fig. 20 a. The first light-emitting layer and the second light-emitting layer are manufactured separately, so that the performance optimization of the light-emitting device is facilitated. Preferably, the projection of the conductive channel of the thin film transistor covered by the second cathode is located in the projection of the second cathode, and the projection direction is perpendicular to the substrate.

The cover plate 16 is covered on the cathode and the second metal reflective layer, and the second metal reflective layer has a planar structure, as shown in fig. 21 and 24. Preferably, the second metal reflective layer 15 has the same structure as the first metal reflective layer 6, and has a sidewall inclined with respect to the surface of the substrate. At this time, the cover plate 16 is also provided with a buffer layer having a prismatic vertical structure, the second metal reflective layer covers the buffer layer having the prismatic vertical structure, and an insulating layer covering the second metal reflective layer may be further provided on a side of the second metal reflective layer away from the buffer layer, and the cover plate is covered on the cathode through the second metal reflective layer, which is as shown in fig. 25.

It should be noted that, although the above embodiments have been described herein, the scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, the changes and modifications of the embodiments described herein, or the equivalent structure or equivalent process changes made by the contents of the specification and the drawings of the present invention, directly or indirectly apply the above technical solutions to other related technical fields, all included in the scope of the present invention.

Claims

1. A display panel, comprising:

a buffer layer is arranged on the surface of the substrate;

2. The display panel according to claim 1, further comprising a second light emitting layer and a second metal layer reflective layer;

3. A display panel as claimed in claim 2, characterized in that the projection of the conducting channel of the thin film transistor is located within the projection of the second metal reflective layer, the projection direction being perpendicular to the substrate.

4. The display panel according to claim 2, wherein the second metal reflective layer has the same structure as the first metal reflective layer.

5. The display panel according to claim 2, wherein the second metal layer and the cathode are respectively located at different regions of the same layer.

6. The display panel according to claim 1, wherein the thin film transistor comprises a gate electrode, a first insulating layer, an active layer, a source electrode, and a drain electrode;

the grid electrode is arranged on the buffer layer;

the first insulating layer is arranged on the grid electrode;

the source electrode and the drain electrode are arranged on the active layer;

7. The display panel according to claim 6, comprising a capacitor that transmits light, wherein the capacitor comprises a lower plate and an upper plate;

8. The display panel according to claim 1, wherein the second insulating layer comprises a passivation layer and a planarization layer;

the planarization layer is disposed on the passivation layer;

9. The display panel of claim 1, wherein the first metal reflective layer further comprises a bottom wall parallel to the surface of the substrate, the bottom wall being disposed between the first sidewall and the second sidewall.