CN212850263U - Novel OCC voltage-reducing PFC circuit - Google Patents

Abstract

The utility model discloses a novel OCC voltage reduction PFC circuit, which comprises a main power circuit and a control circuit; an input voltage detection module and an output voltage sampling module in the control circuit are respectively connected with a corresponding voltage input end and a corresponding voltage output end in the main power circuit, and an input voltage U is obtained from the main power circuit_inOutput voltage U_oInductor current I_LThe data is sampled. The utility model disclosesThe staggered single-phase bridgeless three-level power factor correction function is realized by using a Buck topological circuit structure, an IGBT without an anti-parallel diode and improved single-period control (OCC), and the effects of low total harmonic distortion, high power factor and efficient and stable work are achieved.

Description

Novel OCC voltage-reducing PFC circuit

Technical Field

The utility model relates to a technical field that AC/DC power factor corrected especially involves a novel OCC steps down PFC circuit.

Background

With the rapid development of power electronic technology, various electric devices are popularized. However, power electronic switching power supply devices that are connected to the grid become a major source of injected current harmonics into the grid. Higher current harmonics have severely affected the quality of the power grid power, transmission efficiency, and safe operation of other equipment. Therefore, relevant organizations at home and abroad set relevant safety standards for limiting the current harmonic waves of the power system aiming at the problem. Power factor correction has become an essential part of medium and high power electronic equipment as an effective method for suppressing higher harmonic currents and improving power factor.

Power factor correction circuits are divided into Passive Power Factor Correction (PPFC) and Active Power Factor Correction (APFC). APFC is widely used because of its small size and high PF value. The conventional power factor correction circuit is represented by a Boost active power factor correction rectifier (Boost APFC), and is widely applied due to the characteristics of simple structure, safety and stability. However, under the condition of wide range of input voltage, the traditional Boost APFC rectifier has lower efficiency when the low voltage is input than when the high voltage is input, and has higher output voltage and higher requirement on the voltage stress of a power device of a later stage device. Due to the existence of the preceding stage rectifier bridge, excessive energy loss is caused, and particularly, the on-state loss of the diode is more obvious in low-voltage high-power, so that the improvement of the overall efficiency of the rectifier is greatly limited.

In order to solve the problems brought by the traditional Boost APFC rectifier, a non-bridge Buck PFC rectifier is proposed by a learner, and a switching tube is used for replacing a bridge arm diode in the scheme of the non-bridge Buck PFC rectifier, so that the loss of a switching device of a conduction path is reduced, the purpose of step-down output is realized, the voltage stress requirement of a power device of a rear-stage circuit is reduced, the cost is reduced, and the working efficiency is improved. However, when the conventional bridgeless Buck PFC rectifier is used for low-voltage input, because the output voltage is higher than the input voltage, a certain input current dead angle exists, and thus the harmonic wave and power factor value of the input current can be deteriorated.

Disclosure of Invention

An object of the utility model is to overcome prior art not enough, provide a novel OCC steps down PFC circuit, utilize Buck topological circuit structure, do not take the IGBT of anti-parallel diode and through improving monocycle control (OCC), realize the function of the single-phase no bridge three-level Power Factor Correction of alternating expression (Power Factor Correction, PFC), reach the effect of low total harmonic distortion, high Power Factor and high-efficient stable work.

In order to achieve the above object, the present invention provides a technical solution:

a novel OCC voltage reduction PFC circuit comprises a main power circuit and a control circuit;

the control circuit is connected with the main power circuit, and obtains an input voltage U from the main power circuit_inOutput voltage U_oInductor current I_LSampling data;

wherein the main power circuit is composed of a power inductor L₁、L₂Power MOSFET S₁、S₂、S₃、S₄IGBT S without anti-parallel diode₅、S₆、S₇、S₈Output filter capacitor C_o1、C_o2And a load R;

the power MOSFET S₁S pole and power MOSFET S₂Is connected to the S-pole of the power MOSFET S₁G-pole and power MOSFET S₂G pole connection of (1);

the power MOSFET S₁The D pole of the switch is connected with the voltage input end;

the power MOSFET S₂D pole, IGBT S without anti-parallel diode₅S pole, IGBT S without antiparallel diode₆D pole of the inductor is equal to the power inductor L₁Is connected to a power inductor L₁The other end of the first and second capacitors are respectively connected with an output filter capacitor C_o1、C_o2ToEnd connection;

the power MOSFET S₁、S₂Power inductor L₁A loop is formed through a neutral line;

the power MOSFET S₃S pole and power MOSFET S₄Is connected to the S-pole of the power MOSFET S₃G-pole and power MOSFET S₄G pole connection of (1);

the power MOSFET S₃The D pole of the switch is connected with the voltage input end;

the power MOSFET S₄D pole, IGBT S without anti-parallel diode₇S pole, IGBT S without antiparallel diode₈D pole of the inductor is equal to the power inductor L₂Is connected to a power inductor L₂The other end of the first and second capacitors are respectively connected with an output filter capacitor C_o1、C_o2Is connected with one end of the connecting rod;

the power MOSFET S₃、S₄Power inductor L₂A loop is formed through a neutral line;

the output filter capacitor C_o2And the other end of the IGBT S without an anti-parallel diode₅And S₇D pole connection of (1), power inductance L₁An output filter capacitor C_o2IGBT S without anti-parallel diode₅Forming a loop; power inductor L₂An output filter capacitor C_o2IGBT S without anti-parallel diode₇Forming a loop;

the output filter capacitor C_o1And the other end of the IGBT S without an anti-parallel diode₆And S₈S pole connection of (1), power inductor L₁An output filter capacitor C_o1IGBT S without anti-parallel diode₆Forming a loop; power inductor L₂An output filter capacitor C_o1IGBT S without anti-parallel diode₈Forming a loop;

the load R and the output filter capacitor C_o1、C_o2Are connected in series.

Furthermore, the control circuit is composed of an auxiliary power supply module, an input voltage detection module, an output voltage sampling module, an inductive current sampling module, a first driving module, a second driving module, a third driving module, a fourth driving module, a fifth driving module, a sixth driving module, a first RS trigger, a second RS trigger, a first comparator, a second comparator, a first integrator, a second integrator, an adder and an error amplifier;

the input voltage detection module and the output voltage sampling module are respectively connected with a corresponding voltage input end and a corresponding voltage output end in the main power circuit;

the error amplifier is connected between the output voltage sampling module and the adder and is respectively connected with the first comparator and the second comparator;

one end of the inductive current sampling module is connected with the main power circuit, and the other end of the inductive current sampling module is connected with the adder;

the adder is connected with the two lines;

in the first line, a first integrator, a first comparator, a first RS trigger and a first driving module are sequentially connected;

in a second line, a second integrator, a second comparator, a second RS trigger and a fourth driving module are sequentially connected;

the second driving module and the third driving module are respectively connected between the first RS trigger and the input voltage detection module;

the fifth driving module and the sixth driving module are respectively connected between the second RS trigger and the input voltage detection module;

and the auxiliary power supply module is connected with the input voltage detection module.

Further, the input voltage detection module comprises a conversion circuit, a bidirectional voltage stabilizing diode and an operational amplifier; the bidirectional voltage stabilizing diode is connected between the conversion circuit and the operational amplifier;

the conversion circuit comprises a first voltage dividing resistor R, a second voltage dividing resistor R, a third voltage dividing resistor R and a fourth voltage dividing resistor R_1a、R_2a、R_3a、R_4aComposition is carried out;

the first voltage dividing resistor R_1aOne end of the first resistor is connected with the current input, and the other end of the first resistor is connected with the second voltage-dividing resistorR_2aConnecting;

the fourth voltage dividing resistor R_4aOne end of the first resistor is connected with a current input, and the other end of the first resistor is connected with a third voltage dividing resistor R_3aConnecting;

the second voltage-dividing resistor R_2aAnd the other end of the third voltage dividing resistor R_3aAnd the other end of the same is grounded.

Further, the enabling clocks of the first RS trigger and the second RS trigger are 180 degrees out of phase.

Compared with the prior art, the principle and the advantages of the scheme are as follows:

1) because the staggered bridgeless Buck PFC rectifier system has no dead angle problem of input current, the power factor is greatly improved, the total harmonic distortion degree is reduced, and the working efficiency of the whole machine is further optimized.

2) Because the output voltage of the interleaved bridgeless Buck PFC rectifier system is lower than that of a Boost type PFC rectifier, the voltage stress of a power device of the subsequent equipment is reduced, and the cost is reduced; and when the input voltage is lower, the input voltage is close to the output voltage, so that the rectifier can realize higher working efficiency.

Drawings

In order to illustrate more clearly the embodiments of the present invention or the technical solutions in the prior art, the services required for the embodiments or the technical solutions in the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a block diagram of a novel OCC buck PFC circuit according to the present invention;

fig. 2 is a circuit diagram of a main power circuit in the novel OCC buck PFC circuit of the present invention;

FIG. 3 is a topological structure diagram of a single-circuit bridgeless Buck PFC rectifier;

FIG. 4 shows one of the operation modes of FIG. 3 during the positive half cycle of the AC input;

FIG. 5 shows a second mode of operation of FIG. 3 during a positive half cycle of the AC input;

FIG. 6 shows one of the operation modes of FIG. 3 during the negative half cycle of the AC input;

FIG. 7 shows a second mode of operation of FIG. 3 during negative half cycles of AC input;

FIG. 8 is a schematic structural diagram of an input voltage detection module;

FIG. 9 is a circuit diagram of an output voltage sampling module;

FIG. 10 is a circuit diagram of an inductor current sampling module;

FIG. 11 is a circuit diagram of the first, second, third, fourth, fifth, and sixth driving circuit modules;

FIG. 12 is a waveform diagram of key signals of the input voltage detecting module;

FIG. 13 is a graph of output voltage waveforms after simulation;

fig. 14 is a waveform diagram of the input voltage and the input current of the 0.08 times commercial power after simulation;

FIG. 15 is L after simulation₁And L₂Inductance staggers the current waveform.

Detailed Description

The invention will be further described with reference to the following specific embodiments:

as shown in fig. 1, the novel OCC buck PFC circuit according to this embodiment includes a main power circuit 1 and a control circuit 2;

the control circuit 2 is connected to the main power circuit 1, from which an input voltage U is derived_inOutput voltage U_oInductor current I_LSampling data;

in the first part, as shown in fig. 2, the main power circuit 1 is composed of a power inductor L₁、L₂Power MOSFET S₁、S₂、S₃、S₄IGBT S without anti-parallel diode₅、S₆、S₇、S₈Output filter capacitor C_o1、 C_o2And a load R;

power MOSFET S₁S pole and power MOSFET S₂Is connected to the S-pole of the power MOSFET S₁G-pole and power MOSFET S₂G pole connection of (1);

power MOSFET S₁The D pole of the switch is connected with the voltage input end;

power MOSFET S₂D pole, IGBT S without anti-parallel diode₅S pole, IGBT S without antiparallel diode₆D pole of the inductor is equal to the power inductor L₁Is connected to a power inductor L₁The other end of the first and second capacitors are respectively connected with an output filter capacitor C_o1、C_o2Is connected with one end of the connecting rod;

power MOSFET S₁、S₂Power inductor L₁A loop is formed through a neutral line;

power MOSFET S₃S pole and power MOSFET S₄Is connected to the S-pole of the power MOSFET S₃G-pole and power MOSFET S₄G pole connection of (1);

power MOSFET S₃The D pole of the switch is connected with the voltage input end;

power MOSFET S₄D pole, IGBT S without anti-parallel diode₇S pole, IGBT S without antiparallel diode₈D pole of the inductor is equal to the power inductor L₂Is connected to a power inductor L₂The other end of the first and second capacitors are respectively connected with an output filter capacitor C_o1、C_o2Is connected with one end of the connecting rod;

power MOSFET S₃、S₄Power inductor L₂A loop is formed through a neutral line;

output filter capacitor C_o2And the other end of the IGBT S without an anti-parallel diode₅And S₇D pole connection of (1), power inductance L₁An output filter capacitor C_o2IGBT S without anti-parallel diode₅Forming a loop; power inductor L₂An output filter capacitor C_o2IGBT S without anti-parallel diode₇Forming a loop;

output filter capacitor C_o1And the other end of the IGBT S without an anti-parallel diode₆And S₈S pole connection of (1), power inductor L₁An output filter capacitor C_o1IGBT S without anti-parallel diode₆Forming a loop; power inductor L₂An output filter capacitor C_o1IGBT S without anti-parallel diode₈Forming a loop;

load R and output filter capacitor C_o1、C_o2Are connected in series. In the second part, a control circuit 2 consists of an auxiliary power supply module 2-1, an input voltage detection module 2-2, an output voltage sampling module 2-3, an inductive current sampling module 2-4, a first drive module 2-5, a second drive module 2-6, a third drive module 2-7, a fourth drive module 2-8, a fifth drive module 2-9, a sixth drive module 2-10, a first RS trigger 2-11, a second RS trigger 2-12, a first comparator 2-13, a second comparator 2-14, a first integrator 2-15, a second integrator 2-16, an adder 2-17 and an error amplifier 2-18;

the specific connection relationship is as follows:

the input voltage detection module 2-2 and the output voltage sampling module 2-3 are respectively connected with a corresponding voltage input end and a corresponding voltage output end in the main power circuit 1;

the error amplifier 2-18 is connected between the output voltage sampling module 2-3 and the adder 2-17 and is respectively connected with the first comparator 2-13 and the second comparator 2-14;

one end of the inductive current sampling module 2-4 is connected with the main power circuit 1, and the other end is connected with the adder 2-17;

the summers 2-17 are connected with two lines;

in a first line, a first integrator 2-15, a first comparator 2-13, a first RS trigger 2-11 and a first driving module 2-5 are sequentially connected;

in the second line, a second integrator 2-16, a second comparator 2-14, a second RS trigger 2-12 and a fourth driving module 2-8 are sequentially connected;

the second driving module 2-6 and the third driving module 2-7 are respectively connected between the first RS trigger 2-11 and the input voltage detection module 2-2;

the fifth driving module 2-9 and the sixth driving module 2-10 are respectively connected between the second RS trigger 2-12 and the input voltage detection module 2-2;

the auxiliary power supply module 2-1 is connected with the input voltage detection module 2-2;

enabling clocks of the first RS trigger 2-11 and the second RS trigger 2-12 are 180 degrees out of phase;

further, as shown in fig. 8, the input voltage detection module 2-2 includes a conversion circuit, a bidirectional zener diode, and an operational amplifier; the bidirectional voltage stabilizing diode is connected between the conversion circuit and the operational amplifier;

the conversion circuit comprises a first voltage dividing resistor R, a second voltage dividing resistor R, a third voltage dividing resistor R and a fourth voltage dividing resistor R_1a、R_2a、R_3a、R_4aComposition is carried out;

the first voltage dividing resistor R_1aOne end of the first resistor is connected with a current input, and the other end of the first resistor is connected with a second voltage-dividing resistor R_2aConnecting;

the fourth voltage dividing resistor R_4aOne end of the first resistor is connected with a current input, and the other end of the first resistor is connected with a third voltage dividing resistor R_3aConnecting;

the second voltage-dividing resistor R_2aAnd the other end of the third voltage dividing resistor R_3aAnd the other end of the same is grounded.

And the output voltage sampling module 2-3 and the inductor current sampling module 2-4 are respectively shown in fig. 9 and fig. 10;

the first, second, third, fourth, fifth and sixth driving circuit modules are shown in fig. 11.

The specific working principle of this embodiment is as follows:

firstly, sampling value v of output voltage₀And a reference voltage v_refObtaining an error voltage value v through an error amplifier_mV is to be_mThe value is sent to an adder 2-17 and an inductive current sampling value i_mSumming to obtain V₃Value of, then V₃The value is sent to a first integrator 2-15 and a second integrator 2-16 to obtain V₁And V₂(ii) a One path is directly sent to the first comparator 2-13 and the second comparator 2-14 and is compared with V₁And V₂Comparing; then, the output values of the two comparators are respectively sent to a first RS trigger 2-11 and a second RS trigger 2-12; finally, the first RS trigger 2-11 obtains two complementary PWM driving signals Q1 and Q2; the second RS flip-flop 2-12 obtains two complementary PWM driving signals Q3 and Q4, and the PWM driving signalsThe Q1 and the PWM drive signal Q3 are 180 degrees out of phase.

When the first RS trigger 2-11 is enabled, the input voltage U is applied_inSending the voltage to the input voltage detection module 2-2 to judge the polarity of the input voltage, and if U is judged_in>When 0, the second driving module 2-6 outputs the driving signal P_S5At this time, the first driving module 2-5 and the third driving module 2-7 do not output driving signals; if U is judged_in<When 0, the third driving module 2-7 outputs the driving signal P_S6At this time, the first driving module 2-5 and the second driving module 2-6 do not output driving signals. When the first driving module 2-5 outputs the driving signal P_S1，S2At this time, the second driving module 2-6 and the third driving module 2-7 do not output driving signals.

When the second RS flip-flop 2-12 is enabled, the input voltage U is applied_inSending the voltage to the input voltage detection module 2-2 to judge the polarity of the input voltage, and if U is judged_in>When 0, the fifth driving module 2-9 outputs the driving signal P_S7At this time, the fourth driving module 2-8 and the sixth driving module 2-10 do not output driving signals; if U is judged_in<When 0, the sixth driving module 2-10 outputs the driving signal P_S8At this time, the fourth driving module 2-8 and the fifth driving module 2-9 do not output driving signals. When the fourth driving module 2-8 outputs the driving signal P_S3，S4At this time, the fifth driving module 2-9 and the sixth driving module 2-10 do not output driving signals.

The drive signal P generated by the control circuit 2_S1，S2、P_S3，S4Respectively controlling corresponding power MOSFET S₁、S₂、S₃、S₄(ii) a Drive signal P_S5、P_S6、P_S7、P_S8Controlling IGBT S without antiparallel diodes, respectively₅、 S₆、S₇、S₈。

The main power circuit 1 can realize the purpose of power factor correction through the accurate control of the control circuit 2.

Furthermore, since the present embodiment relates to an interleaved bridgeless Buck PFC rectifier, the two-way power inductor L₁、L₂The interleaved Buck PFC rectifier works in an interleaved mode and can be regarded as a bridgeless Buck PFC rectifier working in an interleaved mode with a driving signal phase difference of 180 degrees, and therefore the working process of the whole circuit of the interleaved bridgeless Buck PFC rectifier can be expressed by analyzing the working principle of a single-circuit bridgeless Buck PFC rectifier. The topological structure of the single-circuit bridgeless Buck PFC rectifier after the interleaved bridgeless Buck PFC rectifier is physically decoupled is shown in fig. 3, and the load resistance of the topological structure is 2R. The two bridgeless Buck PFC rectifiers have the same working principle, and the working modes of the topological structure of the single-circuit bridgeless Buck PFC rectifier are analyzed in detail as follows:

firstly, in the positive half cycle of the alternating current input, the phase can be divided into two working modes:

(1) working mode one

When the AC input is a positive half cycle, the power MOSFET S₁、S₂IGBT S with simultaneous conduction and without anti-parallel diode₅And S₆In the off state. Input current passes through power MOSFET S₁、S₂Power inductor L₁Then form a loop through the neutral wire to form a power inductor L₁And storing energy. Filter capacitor C for outputting direct current bus simultaneously_o1、C_o2The load 2R is energized during which the circuit operates as shown in fig. 4.

(2) Working mode two

When power MOSFET S₁、S₂When the AC input is turned off, the input voltage detection module 2-2 detects that the AC input is a positive half cycle and U_in>0, the second driving module 2-6 outputs a driving signal P_S5For IGBT S without antiparallel diode₅So that the IGBT S without the antiparallel diode₅Is turned on when the power MOSFET S₁、S₂And IGBT S without antiparallel diode₆In the off state. Power inductor L₁The energy is released, the inductive current linearly decreases, and the current passes through the direct current bus to output a filter capacitor C_o2IGBT S without antiparallel diode₅Form a loop to the filter capacitor C_o2And charging is carried out. Filter capacitor C for outputting direct current bus simultaneously_o1、C_o2Supply to the load 2RThe circuit operation state during this period can be as shown in fig. 5.

Secondly, in the negative half cycle of the alternating current input, the phase can be divided into two working modes:

(1) working mode one

When the AC input is negative half cycle, the power MOSFET S₁、S₂IGBT S with simultaneous conduction and without anti-parallel diode₅And S₆In the off state. Input current passes through power MOSFET S₁、S₂Power inductor L₁Then form a loop through the neutral wire to form a power inductor L₁And storing energy. Filter capacitor C for outputting direct current bus simultaneously_o1、C_o2The load 2R is energized, during which the circuit operates as shown in fig. 6;

(2) working mode two

Current power MOSFETS₁、S₂When the AC input is turned off, the input voltage detection module 2-2 detects that the AC input is a negative half cycle and U_in<0, the third driving module 2-7 outputs a driving signal P_S6For IGBT S without antiparallel diode₆So that the IGBT S without the antiparallel diode₆Is turned on when the power MOSFET S₁、S₂And IGBT S without antiparallel diode₅In the off state. Power inductor L₁The energy is released, the inductive current linearly decreases, and the current passes through the direct current bus to output a filter capacitor C_o1IGBT S without antiparallel diode₆Form a loop to the filter capacitor C_o1And charging is carried out. Filter capacitor C for outputting direct current bus simultaneously_o1、C_o2The load 2R is energized, during which the circuit operates as shown in fig. 7;

in the above, the main power circuit 1 realizes the specific principle of power factor correction through the precise control of the control circuit 2 as follows:

since the input voltage and the input current are sinusoidal and in phase, the input impedance of the rectifier can be equivalent to a pure resistor R_eqThe expression is:

in the formula, R_eqIs an input equivalent resistance; u shape_inFor the input voltage of the rectifier, i_inThe rectifier input current.

Rectifier input voltage U in continuous inductor current mode_inAnd an output voltage U_oThe relationship between them is:

where D is the duty cycle within one switching cycle. The combination of the vertical type (1.1) and the formula (1.2) can obtain:

the two sides of the above equation are simultaneously multiplied by the inductive current detection resistor R_sAnd finishing to obtain:

according to the formula (1.4), R_sAnd R_eqFor a constant value, the error voltage value v of the error amplifier_mIn the theoretical case, v_mAnd an output voltage U_oProportional relation, so v can be set_mComprises the following steps:

the following formula can be obtained by combining formula (1.4) and formula (1.5):

(R_s·i_in+v_m)·D＝v_m (1.6)

the above formula is a core control equation for improving the single-period control interleaved bridgeless Buck PFC rectifier, and as can be seen from the formula (1.6), as long as the duty ratio D satisfies the above formula relationship, the input current waveform of the rectifier can track the change of the input voltage waveform, and the phases are consistent, and the rectifier can achieve the purpose of correcting the unit power factor.

Further, the interleaved bridgeless Buck PFC rectifier circuit topology structure of the embodiment has the power MOSFET S connected in series by common source₁、S₂Common source series power MOSFET S₃、S₄IGBT S without anti-parallel diode₅、S₆、S₇、S₈. In order to realize the PFC function, it is necessary to determine the polarity of the input voltage, so as to select the corresponding IGBT without the anti-parallel diode to operate when the input voltage is determined to have different polarities.

Second, the input voltage detecting module 2-2, as shown in fig. 8, first, an alternating current U_inBy R_1aAnd R_2aAnd R_3aAnd R_4aThe two groups of voltage resistors convert input alternating voltage into small-signal alternating current, and a bidirectional voltage stabilizing diode (TVS) is added, so that the function of protecting an operational amplifier (OPAMP) is realized when the circuit is abnormal. The output signal u can be obtained by comparing two input ends of the OPAMP_inThe voltage is high level or low level, when the alternating voltage input is in a positive half cycle, the potential of the in-phase input end of the OPAMP is positive, the potential of the input end of the reverse end is negative, and the OPAMP outputs high level; conversely, when the ac voltage input is a negative half cycle, the OPAMP outputs a low level. Thereby gating the corresponding driving circuit. The waveforms of the key signals of the input voltage detection module 2-2 are shown in fig. 12.

To prove the effectiveness of this embodiment, the simulation software PSIM is used to simulate the embodiment of the present invention, and the following is the simulation result. Fig. 13 shows the output voltage waveform, fig. 14 shows the input voltage and input current waveforms of 0.08 times the commercial power, and fig. 15 shows L₁And L₂The inductors interleave the current waveforms.

The above-mentioned embodiments are only preferred embodiments of the present invention, and the scope of the present invention is not limited thereto, so that all the changes made according to the shape and principle of the present invention should be covered within the protection scope of the present invention.

Claims (4)

1. The novel OCC voltage-reducing PFC circuit is characterized by comprising a main power circuit (1) and a control circuit (2);

the control circuit (2) is connected with the main power circuit (1) and obtains an input voltage U from the main power circuit_inOutput voltage U_oInductor current I_LSampling data;

wherein the main power circuit (1) is composed of a power inductor L₁、L₂Power MOSFET S₁、S₂、S₃、S₄IGBT S without anti-parallel diode₅、S₆、S₇、S₈Output filter capacitor C_o1、C_o2And a load R;

the power MOSFET S₁S pole and power MOSFET S₂Is connected to the S-pole of the power MOSFET S₁G-pole and power MOSFET S₂G pole connection of (1);

the power MOSFET S₁The D pole of the switch is connected with the voltage input end;

the power MOSFET S₂D pole, IGBT S without anti-parallel diode₅S pole, IGBT S without antiparallel diode₆D pole of the inductor is equal to the power inductor L₁Is connected to a power inductor L₁The other end of the first and second capacitors are respectively connected with an output filter capacitor C_o1、C_o2Is connected with one end of the connecting rod;

the power MOSFET S₁、S₂Power inductor L₁A loop is formed through a neutral line;

the power MOSFET S₃S pole and power MOSFET S₄Is connected to the S-pole of the power MOSFET S₃G-pole and power MOSFET S₄G pole connection of (1);

the power MOSFET S₃The D pole of the switch is connected with the voltage input end;

the power MOSFET S₄D pole, IGBT S without anti-parallel diode₇S pole, IGBT S without antiparallel diode₈D pole of the power supply is equal to that of the power supplyFeeling L₂Is connected to a power inductor L₂The other end of the first and second capacitors are respectively connected with an output filter capacitor C_o1、C_o2Is connected with one end of the connecting rod;

the power MOSFET S₃、S₄Power inductor L₂A loop is formed through a neutral line;

the output filter capacitor C_o2And the other end of the IGBT S without an anti-parallel diode₅And S₇D pole connection of (1), power inductance L₁An output filter capacitor C_o2IGBT S without anti-parallel diode₅Forming a loop; power inductor L₂An output filter capacitor C_o2IGBT S without anti-parallel diode₇Forming a loop;

the output filter capacitor C_o1And the other end of the IGBT S without an anti-parallel diode₆And S₈S pole connection of (1), power inductor L₁An output filter capacitor C_o1IGBT S without anti-parallel diode₆Forming a loop; power inductor L₂An output filter capacitor C_o1IGBT S without anti-parallel diode₈Forming a loop;

the load R and the output filter capacitor C_o1、C_o2Are connected in series.

2. The novel OCC buck PFC circuit according to claim 1, wherein the control circuit (2) is composed of an auxiliary power supply module (2-1), an input voltage detection module (2-2), an output voltage sampling module (2-3), an inductive current sampling module (2-4), a first driving module (2-5), a second driving module (2-6), a third driving module (2-7), a fourth driving module (2-8), a fifth driving module (2-9), a sixth driving module (2-10), a first RS trigger (2-11), a second RS trigger (2-12), a first comparator (2-13), a second comparator (2-14), a first integrator (2-15), a second integrator (2-16), An adder (2-17) and an error amplifier (2-18);

the input voltage detection module (2-2) and the output voltage sampling module (2-3) are respectively connected with a corresponding voltage input end and a corresponding voltage output end in the main power circuit (1);

the error amplifier (2-18) is connected between the output voltage sampling module (2-3) and the adder (2-17) and is respectively connected with the first comparator (2-13) and the second comparator (2-14);

one end of the inductive current sampling module (2-4) is connected with the main power circuit (1), and the other end of the inductive current sampling module is connected with the adder (2-17);

the summers (2-17) are connected with two lines;

in a first line, a first integrator (2-15), a first comparator (2-13), a first RS trigger (2-11) and a first driving module (2-5) are sequentially connected;

in the second line, a second integrator (2-16), a second comparator (2-14), a second RS trigger (2-12) and a fourth driving module (2-8) are sequentially connected;

the second driving module (2-6) and the third driving module (2-7) are respectively connected between the first RS trigger (2-11) and the input voltage detection module (2-2);

the fifth driving module (2-9) and the sixth driving module (2-10) are respectively connected between the second RS trigger (2-12) and the input voltage detection module (2-2);

and the auxiliary power supply module (2-1) is connected with the input voltage detection module (2-2).

3. The OCC buck PFC circuit of claim 2, wherein the input voltage detection module (2-2) comprises a conversion circuit, a bi-directional zener diode and an operational amplifier; the bidirectional voltage stabilizing diode is connected between the conversion circuit and the operational amplifier;

the conversion circuit comprises a first voltage dividing resistor R, a second voltage dividing resistor R, a third voltage dividing resistor R and a fourth voltage dividing resistor R_1a、R_2a、R_3a、R_4aComposition is carried out;

the first voltage dividing resistor R_1aOne end of the first resistor is connected with a current input, and the other end of the first resistor is connected with a second voltage-dividing resistor R_2aConnecting;

the fourth voltage dividing resistor R_4aOne end of the first resistor is connected with a current input, and the other end of the first resistor is connected with a third voltage dividing resistor R_3aConnecting;

the second voltage-dividing resistor R_2aAnd the other end of the third voltage dividing resistor R_3aAnd the other end of the same is grounded.

4. The novel OCC buck PFC circuit of claim 2, wherein the enable clocks of the first RS flip-flop (2-11) and the second RS flip-flop (2-12) are 180 degrees out of phase.

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