CN212850263U - Novel OCC voltage-reducing PFC circuit - Google Patents

Novel OCC voltage-reducing PFC circuit Download PDF

Info

Publication number
CN212850263U
CN212850263U CN202021714075.3U CN202021714075U CN212850263U CN 212850263 U CN212850263 U CN 212850263U CN 202021714075 U CN202021714075 U CN 202021714075U CN 212850263 U CN212850263 U CN 212850263U
Authority
CN
China
Prior art keywords
power
voltage
pole
module
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN202021714075.3U
Other languages
Chinese (zh)
Inventor
李志忠
赵付立
陈嘉辉
李优新
何源烽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guangdong University of Technology
Original Assignee
Guangdong University of Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Guangdong University of Technology filed Critical Guangdong University of Technology
Priority to CN202021714075.3U priority Critical patent/CN212850263U/en
Application granted granted Critical
Publication of CN212850263U publication Critical patent/CN212850263U/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Landscapes

  • Rectifiers (AREA)

Abstract

The utility model discloses a novel OCC voltage reduction PFC circuit, which comprises a main power circuit and a control circuit; an input voltage detection module and an output voltage sampling module in the control circuit are respectively connected with a corresponding voltage input end and a corresponding voltage output end in the main power circuit, and an input voltage U is obtained from the main power circuitinOutput voltage UoInductor current ILThe data is sampled. The utility model disclosesThe staggered single-phase bridgeless three-level power factor correction function is realized by using a Buck topological circuit structure, an IGBT without an anti-parallel diode and improved single-period control (OCC), and the effects of low total harmonic distortion, high power factor and efficient and stable work are achieved.

Description

Novel OCC voltage-reducing PFC circuit
Technical Field
The utility model relates to a technical field that AC/DC power factor corrected especially involves a novel OCC steps down PFC circuit.
Background
With the rapid development of power electronic technology, various electric devices are popularized. However, power electronic switching power supply devices that are connected to the grid become a major source of injected current harmonics into the grid. Higher current harmonics have severely affected the quality of the power grid power, transmission efficiency, and safe operation of other equipment. Therefore, relevant organizations at home and abroad set relevant safety standards for limiting the current harmonic waves of the power system aiming at the problem. Power factor correction has become an essential part of medium and high power electronic equipment as an effective method for suppressing higher harmonic currents and improving power factor.
Power factor correction circuits are divided into Passive Power Factor Correction (PPFC) and Active Power Factor Correction (APFC). APFC is widely used because of its small size and high PF value. The conventional power factor correction circuit is represented by a Boost active power factor correction rectifier (Boost APFC), and is widely applied due to the characteristics of simple structure, safety and stability. However, under the condition of wide range of input voltage, the traditional Boost APFC rectifier has lower efficiency when the low voltage is input than when the high voltage is input, and has higher output voltage and higher requirement on the voltage stress of a power device of a later stage device. Due to the existence of the preceding stage rectifier bridge, excessive energy loss is caused, and particularly, the on-state loss of the diode is more obvious in low-voltage high-power, so that the improvement of the overall efficiency of the rectifier is greatly limited.
In order to solve the problems brought by the traditional Boost APFC rectifier, a non-bridge Buck PFC rectifier is proposed by a learner, and a switching tube is used for replacing a bridge arm diode in the scheme of the non-bridge Buck PFC rectifier, so that the loss of a switching device of a conduction path is reduced, the purpose of step-down output is realized, the voltage stress requirement of a power device of a rear-stage circuit is reduced, the cost is reduced, and the working efficiency is improved. However, when the conventional bridgeless Buck PFC rectifier is used for low-voltage input, because the output voltage is higher than the input voltage, a certain input current dead angle exists, and thus the harmonic wave and power factor value of the input current can be deteriorated.
Disclosure of Invention
An object of the utility model is to overcome prior art not enough, provide a novel OCC steps down PFC circuit, utilize Buck topological circuit structure, do not take the IGBT of anti-parallel diode and through improving monocycle control (OCC), realize the function of the single-phase no bridge three-level Power Factor Correction of alternating expression (Power Factor Correction, PFC), reach the effect of low total harmonic distortion, high Power Factor and high-efficient stable work.
In order to achieve the above object, the present invention provides a technical solution:
a novel OCC voltage reduction PFC circuit comprises a main power circuit and a control circuit;
the control circuit is connected with the main power circuit, and obtains an input voltage U from the main power circuitinOutput voltage UoInductor current ILSampling data;
wherein the main power circuit is composed of a power inductor L1、L2Power MOSFET S1、S2、S3、S4IGBT S without anti-parallel diode5、S6、S7、S8Output filter capacitor Co1、Co2And a load R;
the power MOSFET S1S pole and power MOSFET S2Is connected to the S-pole of the power MOSFET S1G-pole and power MOSFET S2G pole connection of (1);
the power MOSFET S1The D pole of the switch is connected with the voltage input end;
the power MOSFET S2D pole, IGBT S without anti-parallel diode5S pole, IGBT S without antiparallel diode6D pole of the inductor is equal to the power inductor L1Is connected to a power inductor L1The other end of the first and second capacitors are respectively connected with an output filter capacitor Co1、Co2ToEnd connection;
the power MOSFET S1、S2Power inductor L1A loop is formed through a neutral line;
the power MOSFET S3S pole and power MOSFET S4Is connected to the S-pole of the power MOSFET S3G-pole and power MOSFET S4G pole connection of (1);
the power MOSFET S3The D pole of the switch is connected with the voltage input end;
the power MOSFET S4D pole, IGBT S without anti-parallel diode7S pole, IGBT S without antiparallel diode8D pole of the inductor is equal to the power inductor L2Is connected to a power inductor L2The other end of the first and second capacitors are respectively connected with an output filter capacitor Co1、Co2Is connected with one end of the connecting rod;
the power MOSFET S3、S4Power inductor L2A loop is formed through a neutral line;
the output filter capacitor Co2And the other end of the IGBT S without an anti-parallel diode5And S7D pole connection of (1), power inductance L1An output filter capacitor Co2IGBT S without anti-parallel diode5Forming a loop; power inductor L2An output filter capacitor Co2IGBT S without anti-parallel diode7Forming a loop;
the output filter capacitor Co1And the other end of the IGBT S without an anti-parallel diode6And S8S pole connection of (1), power inductor L1An output filter capacitor Co1IGBT S without anti-parallel diode6Forming a loop; power inductor L2An output filter capacitor Co1IGBT S without anti-parallel diode8Forming a loop;
the load R and the output filter capacitor Co1、Co2Are connected in series.
Furthermore, the control circuit is composed of an auxiliary power supply module, an input voltage detection module, an output voltage sampling module, an inductive current sampling module, a first driving module, a second driving module, a third driving module, a fourth driving module, a fifth driving module, a sixth driving module, a first RS trigger, a second RS trigger, a first comparator, a second comparator, a first integrator, a second integrator, an adder and an error amplifier;
the input voltage detection module and the output voltage sampling module are respectively connected with a corresponding voltage input end and a corresponding voltage output end in the main power circuit;
the error amplifier is connected between the output voltage sampling module and the adder and is respectively connected with the first comparator and the second comparator;
one end of the inductive current sampling module is connected with the main power circuit, and the other end of the inductive current sampling module is connected with the adder;
the adder is connected with the two lines;
in the first line, a first integrator, a first comparator, a first RS trigger and a first driving module are sequentially connected;
in a second line, a second integrator, a second comparator, a second RS trigger and a fourth driving module are sequentially connected;
the second driving module and the third driving module are respectively connected between the first RS trigger and the input voltage detection module;
the fifth driving module and the sixth driving module are respectively connected between the second RS trigger and the input voltage detection module;
and the auxiliary power supply module is connected with the input voltage detection module.
Further, the input voltage detection module comprises a conversion circuit, a bidirectional voltage stabilizing diode and an operational amplifier; the bidirectional voltage stabilizing diode is connected between the conversion circuit and the operational amplifier;
the conversion circuit comprises a first voltage dividing resistor R, a second voltage dividing resistor R, a third voltage dividing resistor R and a fourth voltage dividing resistor R1a、R2a、R3a、R4aComposition is carried out;
the first voltage dividing resistor R1aOne end of the first resistor is connected with the current input, and the other end of the first resistor is connected with the second voltage-dividing resistorR2aConnecting;
the fourth voltage dividing resistor R4aOne end of the first resistor is connected with a current input, and the other end of the first resistor is connected with a third voltage dividing resistor R3aConnecting;
the second voltage-dividing resistor R2aAnd the other end of the third voltage dividing resistor R3aAnd the other end of the same is grounded.
Further, the enabling clocks of the first RS trigger and the second RS trigger are 180 degrees out of phase.
Compared with the prior art, the principle and the advantages of the scheme are as follows:
1) because the staggered bridgeless Buck PFC rectifier system has no dead angle problem of input current, the power factor is greatly improved, the total harmonic distortion degree is reduced, and the working efficiency of the whole machine is further optimized.
2) Because the output voltage of the interleaved bridgeless Buck PFC rectifier system is lower than that of a Boost type PFC rectifier, the voltage stress of a power device of the subsequent equipment is reduced, and the cost is reduced; and when the input voltage is lower, the input voltage is close to the output voltage, so that the rectifier can realize higher working efficiency.
Drawings
In order to illustrate more clearly the embodiments of the present invention or the technical solutions in the prior art, the services required for the embodiments or the technical solutions in the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a block diagram of a novel OCC buck PFC circuit according to the present invention;
fig. 2 is a circuit diagram of a main power circuit in the novel OCC buck PFC circuit of the present invention;
FIG. 3 is a topological structure diagram of a single-circuit bridgeless Buck PFC rectifier;
FIG. 4 shows one of the operation modes of FIG. 3 during the positive half cycle of the AC input;
FIG. 5 shows a second mode of operation of FIG. 3 during a positive half cycle of the AC input;
FIG. 6 shows one of the operation modes of FIG. 3 during the negative half cycle of the AC input;
FIG. 7 shows a second mode of operation of FIG. 3 during negative half cycles of AC input;
FIG. 8 is a schematic structural diagram of an input voltage detection module;
FIG. 9 is a circuit diagram of an output voltage sampling module;
FIG. 10 is a circuit diagram of an inductor current sampling module;
FIG. 11 is a circuit diagram of the first, second, third, fourth, fifth, and sixth driving circuit modules;
FIG. 12 is a waveform diagram of key signals of the input voltage detecting module;
FIG. 13 is a graph of output voltage waveforms after simulation;
fig. 14 is a waveform diagram of the input voltage and the input current of the 0.08 times commercial power after simulation;
FIG. 15 is L after simulation1And L2Inductance staggers the current waveform.
Detailed Description
The invention will be further described with reference to the following specific embodiments:
as shown in fig. 1, the novel OCC buck PFC circuit according to this embodiment includes a main power circuit 1 and a control circuit 2;
the control circuit 2 is connected to the main power circuit 1, from which an input voltage U is derivedinOutput voltage UoInductor current ILSampling data;
in the first part, as shown in fig. 2, the main power circuit 1 is composed of a power inductor L1、L2Power MOSFET S1、S2、S3、S4IGBT S without anti-parallel diode5、S6、S7、S8Output filter capacitor Co1、 Co2And a load R;
power MOSFET S1S pole and power MOSFET S2Is connected to the S-pole of the power MOSFET S1G-pole and power MOSFET S2G pole connection of (1);
power MOSFET S1The D pole of the switch is connected with the voltage input end;
power MOSFET S2D pole, IGBT S without anti-parallel diode5S pole, IGBT S without antiparallel diode6D pole of the inductor is equal to the power inductor L1Is connected to a power inductor L1The other end of the first and second capacitors are respectively connected with an output filter capacitor Co1、Co2Is connected with one end of the connecting rod;
power MOSFET S1、S2Power inductor L1A loop is formed through a neutral line;
power MOSFET S3S pole and power MOSFET S4Is connected to the S-pole of the power MOSFET S3G-pole and power MOSFET S4G pole connection of (1);
power MOSFET S3The D pole of the switch is connected with the voltage input end;
power MOSFET S4D pole, IGBT S without anti-parallel diode7S pole, IGBT S without antiparallel diode8D pole of the inductor is equal to the power inductor L2Is connected to a power inductor L2The other end of the first and second capacitors are respectively connected with an output filter capacitor Co1、Co2Is connected with one end of the connecting rod;
power MOSFET S3、S4Power inductor L2A loop is formed through a neutral line;
output filter capacitor Co2And the other end of the IGBT S without an anti-parallel diode5And S7D pole connection of (1), power inductance L1An output filter capacitor Co2IGBT S without anti-parallel diode5Forming a loop; power inductor L2An output filter capacitor Co2IGBT S without anti-parallel diode7Forming a loop;
output filter capacitor Co1And the other end of the IGBT S without an anti-parallel diode6And S8S pole connection of (1), power inductor L1An output filter capacitor Co1IGBT S without anti-parallel diode6Forming a loop; power inductor L2An output filter capacitor Co1IGBT S without anti-parallel diode8Forming a loop;
load R and output filter capacitor Co1、Co2Are connected in series. In the second part, a control circuit 2 consists of an auxiliary power supply module 2-1, an input voltage detection module 2-2, an output voltage sampling module 2-3, an inductive current sampling module 2-4, a first drive module 2-5, a second drive module 2-6, a third drive module 2-7, a fourth drive module 2-8, a fifth drive module 2-9, a sixth drive module 2-10, a first RS trigger 2-11, a second RS trigger 2-12, a first comparator 2-13, a second comparator 2-14, a first integrator 2-15, a second integrator 2-16, an adder 2-17 and an error amplifier 2-18;
the specific connection relationship is as follows:
the input voltage detection module 2-2 and the output voltage sampling module 2-3 are respectively connected with a corresponding voltage input end and a corresponding voltage output end in the main power circuit 1;
the error amplifier 2-18 is connected between the output voltage sampling module 2-3 and the adder 2-17 and is respectively connected with the first comparator 2-13 and the second comparator 2-14;
one end of the inductive current sampling module 2-4 is connected with the main power circuit 1, and the other end is connected with the adder 2-17;
the summers 2-17 are connected with two lines;
in a first line, a first integrator 2-15, a first comparator 2-13, a first RS trigger 2-11 and a first driving module 2-5 are sequentially connected;
in the second line, a second integrator 2-16, a second comparator 2-14, a second RS trigger 2-12 and a fourth driving module 2-8 are sequentially connected;
the second driving module 2-6 and the third driving module 2-7 are respectively connected between the first RS trigger 2-11 and the input voltage detection module 2-2;
the fifth driving module 2-9 and the sixth driving module 2-10 are respectively connected between the second RS trigger 2-12 and the input voltage detection module 2-2;
the auxiliary power supply module 2-1 is connected with the input voltage detection module 2-2;
enabling clocks of the first RS trigger 2-11 and the second RS trigger 2-12 are 180 degrees out of phase;
further, as shown in fig. 8, the input voltage detection module 2-2 includes a conversion circuit, a bidirectional zener diode, and an operational amplifier; the bidirectional voltage stabilizing diode is connected between the conversion circuit and the operational amplifier;
the conversion circuit comprises a first voltage dividing resistor R, a second voltage dividing resistor R, a third voltage dividing resistor R and a fourth voltage dividing resistor R1a、R2a、R3a、R4aComposition is carried out;
the first voltage dividing resistor R1aOne end of the first resistor is connected with a current input, and the other end of the first resistor is connected with a second voltage-dividing resistor R2aConnecting;
the fourth voltage dividing resistor R4aOne end of the first resistor is connected with a current input, and the other end of the first resistor is connected with a third voltage dividing resistor R3aConnecting;
the second voltage-dividing resistor R2aAnd the other end of the third voltage dividing resistor R3aAnd the other end of the same is grounded.
And the output voltage sampling module 2-3 and the inductor current sampling module 2-4 are respectively shown in fig. 9 and fig. 10;
the first, second, third, fourth, fifth and sixth driving circuit modules are shown in fig. 11.
The specific working principle of this embodiment is as follows:
firstly, sampling value v of output voltage0And a reference voltage vrefObtaining an error voltage value v through an error amplifiermV is to bemThe value is sent to an adder 2-17 and an inductive current sampling value imSumming to obtain V3Value of, then V3The value is sent to a first integrator 2-15 and a second integrator 2-16 to obtain V1And V2(ii) a One path is directly sent to the first comparator 2-13 and the second comparator 2-14 and is compared with V1And V2Comparing; then, the output values of the two comparators are respectively sent to a first RS trigger 2-11 and a second RS trigger 2-12; finally, the first RS trigger 2-11 obtains two complementary PWM driving signals Q1 and Q2; the second RS flip-flop 2-12 obtains two complementary PWM driving signals Q3 and Q4, and the PWM driving signalsThe Q1 and the PWM drive signal Q3 are 180 degrees out of phase.
When the first RS trigger 2-11 is enabled, the input voltage U is appliedinSending the voltage to the input voltage detection module 2-2 to judge the polarity of the input voltage, and if U is judgedin>When 0, the second driving module 2-6 outputs the driving signal PS5At this time, the first driving module 2-5 and the third driving module 2-7 do not output driving signals; if U is judgedin<When 0, the third driving module 2-7 outputs the driving signal PS6At this time, the first driving module 2-5 and the second driving module 2-6 do not output driving signals. When the first driving module 2-5 outputs the driving signal PS1，S2At this time, the second driving module 2-6 and the third driving module 2-7 do not output driving signals.
When the second RS flip-flop 2-12 is enabled, the input voltage U is appliedinSending the voltage to the input voltage detection module 2-2 to judge the polarity of the input voltage, and if U is judgedin>When 0, the fifth driving module 2-9 outputs the driving signal PS7At this time, the fourth driving module 2-8 and the sixth driving module 2-10 do not output driving signals; if U is judgedin<When 0, the sixth driving module 2-10 outputs the driving signal PS8At this time, the fourth driving module 2-8 and the fifth driving module 2-9 do not output driving signals. When the fourth driving module 2-8 outputs the driving signal PS3，S4At this time, the fifth driving module 2-9 and the sixth driving module 2-10 do not output driving signals.
The drive signal P generated by the control circuit 2S1，S2、PS3，S4Respectively controlling corresponding power MOSFET S1、S2、S3、S4(ii) a Drive signal PS5、PS6、PS7、PS8Controlling IGBT S without antiparallel diodes, respectively5、 S6、S7、S8。
The main power circuit 1 can realize the purpose of power factor correction through the accurate control of the control circuit 2.
Furthermore, since the present embodiment relates to an interleaved bridgeless Buck PFC rectifier, the two-way power inductor L1、L2The interleaved Buck PFC rectifier works in an interleaved mode and can be regarded as a bridgeless Buck PFC rectifier working in an interleaved mode with a driving signal phase difference of 180 degrees, and therefore the working process of the whole circuit of the interleaved bridgeless Buck PFC rectifier can be expressed by analyzing the working principle of a single-circuit bridgeless Buck PFC rectifier. The topological structure of the single-circuit bridgeless Buck PFC rectifier after the interleaved bridgeless Buck PFC rectifier is physically decoupled is shown in fig. 3, and the load resistance of the topological structure is 2R. The two bridgeless Buck PFC rectifiers have the same working principle, and the working modes of the topological structure of the single-circuit bridgeless Buck PFC rectifier are analyzed in detail as follows:
firstly, in the positive half cycle of the alternating current input, the phase can be divided into two working modes:
(1) working mode one
When the AC input is a positive half cycle, the power MOSFET S1、S2IGBT S with simultaneous conduction and without anti-parallel diode5And S6In the off state. Input current passes through power MOSFET S1、S2Power inductor L1Then form a loop through the neutral wire to form a power inductor L1And storing energy. Filter capacitor C for outputting direct current bus simultaneouslyo1、Co2The load 2R is energized during which the circuit operates as shown in fig. 4.
(2) Working mode two
When power MOSFET S1、S2When the AC input is turned off, the input voltage detection module 2-2 detects that the AC input is a positive half cycle and Uin>0, the second driving module 2-6 outputs a driving signal PS5For IGBT S without antiparallel diode5So that the IGBT S without the antiparallel diode5Is turned on when the power MOSFET S1、S2And IGBT S without antiparallel diode6In the off state. Power inductor L1The energy is released, the inductive current linearly decreases, and the current passes through the direct current bus to output a filter capacitor Co2IGBT S without antiparallel diode5Form a loop to the filter capacitor Co2And charging is carried out. Filter capacitor C for outputting direct current bus simultaneouslyo1、Co2Supply to the load 2RThe circuit operation state during this period can be as shown in fig. 5.
Secondly, in the negative half cycle of the alternating current input, the phase can be divided into two working modes:
(1) working mode one
When the AC input is negative half cycle, the power MOSFET S1、S2IGBT S with simultaneous conduction and without anti-parallel diode5And S6In the off state. Input current passes through power MOSFET S1、S2Power inductor L1Then form a loop through the neutral wire to form a power inductor L1And storing energy. Filter capacitor C for outputting direct current bus simultaneouslyo1、Co2The load 2R is energized, during which the circuit operates as shown in fig. 6;
(2) working mode two
Current power MOSFETS1、S2When the AC input is turned off, the input voltage detection module 2-2 detects that the AC input is a negative half cycle and Uin<0, the third driving module 2-7 outputs a driving signal PS6For IGBT S without antiparallel diode6So that the IGBT S without the antiparallel diode6Is turned on when the power MOSFET S1、S2And IGBT S without antiparallel diode5In the off state. Power inductor L1The energy is released, the inductive current linearly decreases, and the current passes through the direct current bus to output a filter capacitor Co1IGBT S without antiparallel diode6Form a loop to the filter capacitor Co1And charging is carried out. Filter capacitor C for outputting direct current bus simultaneouslyo1、Co2The load 2R is energized, during which the circuit operates as shown in fig. 7;
in the above, the main power circuit 1 realizes the specific principle of power factor correction through the precise control of the control circuit 2 as follows:
since the input voltage and the input current are sinusoidal and in phase, the input impedance of the rectifier can be equivalent to a pure resistor ReqThe expression is:
Figure BDA0002636804360000101
in the formula, ReqIs an input equivalent resistance; u shapeinFor the input voltage of the rectifier, iinThe rectifier input current.
Rectifier input voltage U in continuous inductor current modeinAnd an output voltage UoThe relationship between them is:
Figure BDA0002636804360000111
where D is the duty cycle within one switching cycle. The combination of the vertical type (1.1) and the formula (1.2) can obtain:
Figure BDA0002636804360000112
the two sides of the above equation are simultaneously multiplied by the inductive current detection resistor RsAnd finishing to obtain:
Figure BDA0002636804360000113
according to the formula (1.4), RsAnd ReqFor a constant value, the error voltage value v of the error amplifiermIn the theoretical case, vmAnd an output voltage UoProportional relation, so v can be setmComprises the following steps:
Figure BDA0002636804360000114
the following formula can be obtained by combining formula (1.4) and formula (1.5):
(Rs·iin+vm)·D＝vm (1.6)
the above formula is a core control equation for improving the single-period control interleaved bridgeless Buck PFC rectifier, and as can be seen from the formula (1.6), as long as the duty ratio D satisfies the above formula relationship, the input current waveform of the rectifier can track the change of the input voltage waveform, and the phases are consistent, and the rectifier can achieve the purpose of correcting the unit power factor.
Further, the interleaved bridgeless Buck PFC rectifier circuit topology structure of the embodiment has the power MOSFET S connected in series by common source1、S2Common source series power MOSFET S3、S4IGBT S without anti-parallel diode5、S6、S7、S8. In order to realize the PFC function, it is necessary to determine the polarity of the input voltage, so as to select the corresponding IGBT without the anti-parallel diode to operate when the input voltage is determined to have different polarities.
Second, the input voltage detecting module 2-2, as shown in fig. 8, first, an alternating current UinBy R1aAnd R2aAnd R3aAnd R4aThe two groups of voltage resistors convert input alternating voltage into small-signal alternating current, and a bidirectional voltage stabilizing diode (TVS) is added, so that the function of protecting an operational amplifier (OPAMP) is realized when the circuit is abnormal. The output signal u can be obtained by comparing two input ends of the OPAMPinThe voltage is high level or low level, when the alternating voltage input is in a positive half cycle, the potential of the in-phase input end of the OPAMP is positive, the potential of the input end of the reverse end is negative, and the OPAMP outputs high level; conversely, when the ac voltage input is a negative half cycle, the OPAMP outputs a low level. Thereby gating the corresponding driving circuit. The waveforms of the key signals of the input voltage detection module 2-2 are shown in fig. 12.
To prove the effectiveness of this embodiment, the simulation software PSIM is used to simulate the embodiment of the present invention, and the following is the simulation result. Fig. 13 shows the output voltage waveform, fig. 14 shows the input voltage and input current waveforms of 0.08 times the commercial power, and fig. 15 shows L1And L2The inductors interleave the current waveforms.
The above-mentioned embodiments are only preferred embodiments of the present invention, and the scope of the present invention is not limited thereto, so that all the changes made according to the shape and principle of the present invention should be covered within the protection scope of the present invention.

Claims (4)

1.一种新型OCC降压PFC电路，其特征在于，包括主功率电路(1)和控制电路(2)；1. a novel OCC step-down PFC circuit, is characterized in that, comprises main power circuit (1) and control circuit (2); 所述控制电路(2)与主功率电路(1)连接，从主功率电路得到输入电压Uin、输出电压Uo、电感电流IL采样数据；The control circuit (2) is connected to the main power circuit (1), and the sampling data of the input voltage U in , the output voltage U o and the inductor current IL are obtained from the main power circuit; 其中，所述主功率电路(1)由功率电感L1、L2、功率MOSFET S1、S2、S3、S4、不带反并联二极管的IGBT S5、S6、S7、S8，输出滤波电容Co1、Co2、负载R组成；Wherein, the main power circuit (1) consists of power inductors L 1 , L 2 , power MOSFETs S 1 , S 2 , S 3 , S 4 , IGBTs S 5 , S 6 , S 7 , S without anti-parallel diodes 8 , composed of output filter capacitors C o1 , C o2 and load R; 所述功率MOSFET S1的S极与功率MOSFET S2的S极连接，功率MOSFET S1的G极与功率MOSFET S2的G极连接； The S pole of the power MOSFET S1 is connected with the S pole of the power MOSFET S2, and the G pole of the power MOSFET S1 is connected with the G pole of the power MOSFET S2 ; 所述功率MOSFET S1的D极与电压输入端连接； The D pole of the power MOSFET S1 is connected to the voltage input end; 所述功率MOSFET S2的D极、不带反并联二极管的IGBT S5的S极、不带反并联二极管的IGBT S6的D极均与功率电感L1的一端连接，功率电感L1的另一端分别与输出滤波电容Co1、Co2的一端连接； The D pole of the power MOSFET S2, the S pole of the IGBT S5 without the anti - parallel diode, and the D pole of the IGBT S6 without the anti-parallel diode are all connected to one end of the power inductor L1, and the The other ends are respectively connected with one end of the output filter capacitors C o1 and C o2 ; 所述功率MOSFET S1、S2、功率电感L1，通过中性线构成回路；The power MOSFETs S 1 , S 2 and the power inductor L 1 form a loop through the neutral wire; 所述功率MOSFET S3的S极与功率MOSFET S4的S极连接，功率MOSFET S3的G极与功率MOSFET S4的G极连接； The S pole of the power MOSFET S3 is connected with the S pole of the power MOSFET S4, and the G pole of the power MOSFET S3 is connected with the G pole of the power MOSFET S4 ; 所述功率MOSFET S3的D极与电压输入端连接； The D pole of the power MOSFET S3 is connected to the voltage input end; 所述功率MOSFET S4的D极、不带反并联二极管的IGBT S7的S极、不带反并联二极管的IGBT S8的D极均与功率电感L2的一端连接，功率电感L2的另一端分别与输出滤波电容Co1、Co2的一端连接； The D pole of the power MOSFET S4, the S pole of the IGBT S7 without the anti - parallel diode, and the D pole of the IGBT S8 without the anti - parallel diode are all connected to one end of the power inductor L2, and the power inductor L2 The other ends are respectively connected with one end of the output filter capacitors C o1 and C o2 ; 所述功率MOSFET S3、S4、功率电感L2，通过中性线构成回路；The power MOSFETs S 3 , S 4 and the power inductor L 2 form a loop through the neutral wire; 所述输出滤波电容Co2的另一端与不带反并联二极管的IGBT S5和S7的D极连接，功率电感L1、输出滤波电容Co2、不带反并联二极管的IGBT S5构成回路；功率电感L2、输出滤波电容Co2、不带反并联二极管的IGBT S7构成回路；The other end of the output filter capacitor C o2 is connected to the D poles of the IGBTs S 5 and S 7 without anti-parallel diodes, and the power inductor L 1 , the output filter capacitor C o2 , and the IGBT S 5 without anti-parallel diodes form a loop ; Power inductor L 2 , output filter capacitor C o2 , and IGBT S 7 without anti-parallel diode form a loop; 所述输出滤波电容Co1的另一端与不带反并联二极管的IGBT S6和S8的S极连接，功率电感L1、输出滤波电容Co1、不带反并联二极管的IGBT S6构成回路；功率电感L2、输出滤波电容Co1、不带反并联二极管的IGBT S8构成回路；The other end of the output filter capacitor C o1 is connected to the S poles of the IGBTs S 6 and S 8 without anti-parallel diodes, and the power inductor L 1 , the output filter capacitor C o1 , and the IGBT S 6 without anti-parallel diodes form a loop ; The power inductor L 2 , the output filter capacitor C o1 , and the IGBT S 8 without the anti-parallel diode form a loop; 所述负载R和输出滤波电容Co1、Co2串联。The load R is connected in series with the output filter capacitors C o1 and C o2 . 2.根据权利要求1所述的一种新型OCC降压PFC电路，其特征在于，所述控制电路(2)由辅助供电电源模块(2-1)、输入电压检测模块(2-2)、输出电压采样模块(2-3)、电感电流采样模块(2-4)、第一驱动模块(2-5)、第二驱动模块(2-6)、第三驱动模块(2-7)、第四驱动模块(2-8)、第五驱动模块(2-9)、第六驱动模块(2-10)、第一RS触发器(2-11)、第二RS触发器(2-12)、第一比较器(2-13)、第二比较器(2-14)、第一积分器(2-15)、第二积分器(2-16)、加法器(2-17)、误差放大器(2-18)组成；2. A novel OCC step-down PFC circuit according to claim 1, wherein the control circuit (2) is composed of an auxiliary power supply module (2-1), an input voltage detection module (2-2), an output voltage sampling module (2-3), an inductor current sampling module (2-4), a first driving module (2-5), a second driving module (2-6), a third driving module (2-7), Fourth drive module (2-8), fifth drive module (2-9), sixth drive module (2-10), first RS flip-flop (2-11), second RS flip-flop (2-12 ), first comparator (2-13), second comparator (2-14), first integrator (2-15), second integrator (2-16), adder (2-17), Error amplifier (2-18) composition; 其中，所述输入电压检测模块(2-2)和输出电压采样模块(2-3)分别与主功率电路(1)中对应的电压输入端和电压输出端连接；Wherein, the input voltage detection module (2-2) and the output voltage sampling module (2-3) are respectively connected with corresponding voltage input terminals and voltage output terminals in the main power circuit (1); 所述误差放大器(2-18)连接在输出电压采样模块(2-3)和加法器(2-17)之间，并分别与第一比较器(2-13)和第二比较器(2-14)连接；The error amplifier (2-18) is connected between the output voltage sampling module (2-3) and the adder (2-17), and is connected to the first comparator (2-13) and the second comparator (2-17) respectively -14) Connect; 所述电感电流采样模块(2-4)的一端与主功率电路(1)连接，另一端与加法器(2-17)连接；One end of the inductor current sampling module (2-4) is connected to the main power circuit (1), and the other end is connected to the adder (2-17); 所述加法器(2-17)连接两条线路；The adder (2-17) connects two lines; 第一条线路中，第一积分器(2-15)、第一比较器(2-13)、第一RS触发器(2-11)、第一驱动模块(2-5)顺序连接；In the first line, the first integrator (2-15), the first comparator (2-13), the first RS flip-flop (2-11), and the first driving module (2-5) are connected in sequence; 第二条线路中，第二积分器(2-16)、第二比较器(2-14)、第二RS触发器(2-12)、第四驱动模块(2-8)顺序连接；In the second line, the second integrator (2-16), the second comparator (2-14), the second RS flip-flop (2-12), and the fourth driving module (2-8) are connected in sequence; 所述第二驱动模块(2-6)和第三驱动模块(2-7)分别连接于第一RS触发器(2-11)和输入电压检测模块(2-2)之间；The second driving module (2-6) and the third driving module (2-7) are respectively connected between the first RS flip-flop (2-11) and the input voltage detection module (2-2); 所述第五驱动模块(2-9)、第六驱动模块(2-10)分别连接于第二RS触发器(2-12)和输入电压检测模块(2-2)之间；The fifth driving module (2-9) and the sixth driving module (2-10) are respectively connected between the second RS trigger (2-12) and the input voltage detection module (2-2); 所述辅助供电电源模块(2-1)与输入电压检测模块(2-2)连接。The auxiliary power supply module (2-1) is connected to the input voltage detection module (2-2). 3.根据权利要求2所述的一种新型OCC降压PFC电路，其特征在于，所述输入电压检测模块(2-2)包括转换电路、双向稳压二极管以及运算放大器；其中，双向稳压二极管接于转换电路和运算放大器之间；3. a kind of novel OCC step-down PFC circuit according to claim 2, is characterized in that, described input voltage detection module (2-2) comprises conversion circuit, bidirectional voltage stabilizer diode and operational amplifier; Wherein, bidirectional voltage stabilizer The diode is connected between the conversion circuit and the operational amplifier; 所述转换电路由第一、二、三、四分压电阻R1a、R2a、R3a、R4a组成；The conversion circuit is composed of first, second, third and fourth voltage dividing resistors R 1a , R 2a , R 3a and R 4a ; 所述第一分压电阻R1a的一端接电流输入，另一端与第二分压电阻R2a连接；One end of the first voltage dividing resistor R1a is connected to the current input, and the other end is connected to the second voltage dividing resistor R2a ; 所述第四分压电阻R4a的一端接电流输入，另一端与第三分压电阻R3a连接；One end of the fourth voltage dividing resistor R 4a is connected to the current input, and the other end is connected to the third voltage dividing resistor R 3a ; 所述第二分压电阻R2a的另一端和第三分压电阻R3a的另一端接地。The other end of the second voltage dividing resistor R 2a and the other end of the third voltage dividing resistor R 3a are grounded. 4.根据权利要求2所述的一种新型OCC降压PFC电路，其特征在于，所述第一RS触发器(2-11)和第二RS触发器(2-12)的使能时钟相位相差180度。4. A novel OCC step-down PFC circuit according to claim 2, characterized in that the enable clock phase of the first RS flip-flop (2-11) and the second RS flip-flop (2-12) A difference of 180 degrees.
CN202021714075.3U 2020-08-17 2020-08-17 Novel OCC voltage-reducing PFC circuit Expired - Fee Related CN212850263U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202021714075.3U CN212850263U (en) 2020-08-17 2020-08-17 Novel OCC voltage-reducing PFC circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202021714075.3U CN212850263U (en) 2020-08-17 2020-08-17 Novel OCC voltage-reducing PFC circuit

Publications (1)

Publication Number Publication Date
CN212850263U true CN212850263U (en) 2021-03-30

Family

ID=75136940

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202021714075.3U Expired - Fee Related CN212850263U (en) 2020-08-17 2020-08-17 Novel OCC voltage-reducing PFC circuit

Country Status (1)

Country Link
CN (1) CN212850263U (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112087128A (en) * 2020-08-17 2020-12-15 广东工业大学 Staggered bridgeless Buck PFC rectifier system
CN113206605A (en) * 2021-04-12 2021-08-03 三峡大学 Three-level rectification charger with single-phase T-shaped staggered parallel structure
CN113271003A (en) * 2021-06-16 2021-08-17 广东工业大学 PFC conversion circuit of uninterruptible power supply and control method
CN113904461A (en) * 2021-10-11 2022-01-07 陈文芗 a converter
CN117060710A (en) * 2023-08-21 2023-11-14 哈尔滨工业大学 Single-phase bridgeless buck-boost PFC converter

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112087128A (en) * 2020-08-17 2020-12-15 广东工业大学 Staggered bridgeless Buck PFC rectifier system
CN112087128B (en) * 2020-08-17 2024-08-27 广东工业大学 Interleaved bridgeless Buck PFC rectifier system
CN113206605A (en) * 2021-04-12 2021-08-03 三峡大学 Three-level rectification charger with single-phase T-shaped staggered parallel structure
CN113206605B (en) * 2021-04-12 2023-09-19 三峡大学 Three-level rectifying charger with single-phase T-shaped staggered parallel structure
CN113271003A (en) * 2021-06-16 2021-08-17 广东工业大学 PFC conversion circuit of uninterruptible power supply and control method
CN113904461A (en) * 2021-10-11 2022-01-07 陈文芗 a converter
CN117060710A (en) * 2023-08-21 2023-11-14 哈尔滨工业大学 Single-phase bridgeless buck-boost PFC converter
CN117060710B (en) * 2023-08-21 2024-11-26 哈尔滨工业大学 Single-phase bridgeless buck-boost PFC converter

Similar Documents

Publication Publication Date Title
CN212850263U (en) Novel OCC voltage-reducing PFC circuit
CN111431394B (en) Control method of buck single-phase three-level bridgeless PFC converter system
CN107896069A (en) A kind of New single-phase mixes three-level rectifier
CN102130577B (en) Window control circuit for power factor correction circuit
CN103166489B (en) A kind of control circuit of Three-Phase SVPWM Rectifier
CN102447404A (en) Three-phase alternating-current (AC)-direct-current (DC) full-bridge high-frequency converter
CN113726199B (en) Low-output ripple boost rectifier and control method thereof
CN211018677U (en) A Numerically Controlled Short Arc DC Superimposed Pulse Power Supply
CN102832828B (en) Magnetic combined three-phase input AC (Alternating Current)/DC (Direct Current) full-bridge high frequency converter
CN211630095U (en) A single-phase three-level Buck PFC rectifier
CN113765359A (en) Multi-unit parallel connection integrated voltage reduction bridgeless PFC converter
CN101860318B (en) Alternating current governing system for twin-stage matrix converter having anti-losing capability
CN107124105B (en) Improve the control system and method for isolated form three-level PFC converter PF
CN211959064U (en) Novel non-isolated Buck PFC converter system
CN110535364A (en) A kind of dual Buck inverter improvement modulator approach based on accessory power supply
CN203151389U (en) Control circuit of three-phase high power factor rectifier
CN111342684B (en) A single-phase three-level Buck PFC rectifier and its control method
CN112087128B (en) Interleaved bridgeless Buck PFC rectifier system
CN105226932A (en) High efficiency circuit of power factor correction topological structure and control method thereof
CN203243277U (en) A three-phase 220V AC motor drive device using 110V AC
CN111431420B (en) Control method of three-phase four-wire system three-level Buck PFC rectifier system
CN211959080U (en) Buck three-phase four-wire three-level PFC rectifier system
CN219779988U (en) A New Buck Power Factor Correction Converter
CN204442168U (en) A kind of based on without bridge CUK isolated form Three Phase Power Factor Correction Converter
CN104967304B (en) One kind is based on no bridge CUK isolated form Three Phase Power Factor Correction Converters

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20210330

Termination date: 20210817