CN212846771U - SPI communication interface testing arrangement - Google Patents
SPI communication interface testing arrangement Download PDFInfo
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- CN212846771U CN212846771U CN202020943494.8U CN202020943494U CN212846771U CN 212846771 U CN212846771 U CN 212846771U CN 202020943494 U CN202020943494 U CN 202020943494U CN 212846771 U CN212846771 U CN 212846771U
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Abstract
A SPI communication interface testing arrangement, include: the power supply device comprises a microcontroller, a dual-power circuit, an overload protection circuit, a startup and shutdown control circuit and a PC (personal computer) end, wherein an SPI (serial peripheral interface) communication interface is communicated with the microcontroller, the output end of the dual-power circuit transmits a voltage signal to the overload protection circuit and is controlled by the microcontroller through the signal, the output end of the overload protection circuit is connected with a power supply voltage end of the microcontroller, the input end of the startup and shutdown circuit is connected with the output end of the overload protection circuit, the microcontroller transmits a control signal to the startup and shutdown circuit, the output end of the startup and shutdown circuit is connected with the power supply voltage end of the SPI communication interface, and the PC end is interconnected with the microcontroller; the utility model discloses will because plus two voltage switch, open outage, overload protection and external USB2.0 PHY circuit, improved the communication speed with PC and increased two voltage switch function and have overload protection open the outage test, be enough to be applied to the reliability test scheme.
Description
Technical Field
The utility model relates to a testing arrangement, concretely relates to SPI communication interface testing arrangement.
Background
In the existing SPI test platform, the existing SPI bridge is mostly used, for example, FT4222 of FTDI is a USB to SPI bridge chip, but although this chip supports Quad SPI, the speed can only reach 30MHz, and 108MHz is insufficient for the modern fast speed requirement.
In the market, for the requirement of low voltage of portable equipment, two main stream working voltages of 3.3V and 1.8V are generated, and common test platforms mostly correspond to different voltages for different platforms, so that the trouble of platform exchange can be caused during voltage exchange test, therefore, the double-voltage switching test of the same platform can simplify the test operation, reduce the possibility of manual platform exchange misoperation, and further improve the stability of the test.
SUMMERY OF THE UTILITY MODEL
Utility model purpose: in order to overcome the not enough of prior art, the utility model provides a SPI communication interface testing arrangement has solved among the prior art problem that communication speed is low, voltage replacement misoperation rate is high.
The technical scheme is as follows: a SPI communication interface testing arrangement, include: microcontroller, dual supply circuit, overload protection circuit, power-on and power-off control circuit and PC end, SPI communication interface with microcontroller intercommunication, dual supply circuit output gives voltage signal overload protection circuit, and by microcontroller carries out signal control, overload protection circuit output with microcontroller's supply voltage end links to each other, power-on and power-off input with overload protection circuit output links to each other, and microcontroller is to power-on and power-off transmission control signal, and power-on and power-off circuit's output with SPI communication interface's supply voltage end is connected, PC end and microcontroller interconnect.
Further, the method comprises the following steps:
the microcontroller is of the model STM32F7 series.
Further, the method comprises the following steps:
and the SPI communication interface is connected to a QSPI interface of the microcontroller.
Further, the method comprises the following steps:
the device also comprises a USB3315 of SMSC company, wherein the USB3315 is arranged on a USB interface of the microcontroller, and a PC end is connected with the additional USB 3315.
Further, the method comprises the following steps:
the power-on and power-off control circuit receives a control signal through the microcontroller interface GPIO0, and the dual-power circuit receives a control signal through the microcontroller interface GPIO 1.
Further, the method comprises the following steps:
the overload protection circuit comprises a triode, a first resistor, a second resistor and a third resistor, wherein the first resistor is connected to the emitter end of the triode, the second resistor is connected between the collector and the base of the triode, and the third resistor is connected between the base and the emitter of the triode.
Further, the method comprises the following steps:
the power on-off circuit comprises a first field effect transistor, a first phase inverter and a second field effect transistor, wherein a source electrode of the first field effect transistor is connected with a power supply voltage end of the microcontroller, a drain electrode of the first field effect transistor is connected with the power supply voltage end of the SPI communication interface, a grid electrode of the first field effect transistor is connected with a grid electrode of the second field effect transistor and then connected with the first phase inverter, the microcontroller transmits a control signal to the first phase inverter, a drain electrode of the second field effect transistor is connected to the power supply voltage end of the SPI communication interface, and a source electrode of the second field effect transistor is grounded.
Further, the method comprises the following steps:
the dual power supply circuit comprises a 1.8V low-power LDO, a 3.3V low-power LDO, a third field effect tube, a fourth field effect tube and a second phase inverter, wherein a source electrode of the third field effect tube is connected with the 1.8V low-power LDO and a source electrode of the fourth field effect tube is connected with the 3.3V low-power LDO, drain electrodes of the third field effect tube and the fourth field effect tube are connected with each other and input signals into the overload protection circuit, a grid electrode of the third field effect tube is connected with the second phase inverter, and a grid electrode of the fourth field effect tube is connected with a control end of the microcontroller, so that the microcontroller transmits control signals to the control end.
Has the advantages that: compared with the prior art, the utility model, it is showing the advantage and is: the utility model discloses add STM32F7 MCU into firmware and software, realize low-cost and high-speed 108MHz QSPI test platform fast. The device can test not only the 108MHz Quad mode but also the read-write test of 1bit, 2bit, 4bit and Quad modes through software and firmware, and improves the communication speed with PC and increases the double voltage test and the start-stop test with overload protection due to the addition of a double voltage switching circuit, a power-off circuit and an overload protection circuit and the plug-in USB2.0 PHY circuit, thus being enough to be applied to a reliability test scheme.
Drawings
Fig. 1 is a block diagram of a testing apparatus according to the present invention;
FIG. 2 is a circuit diagram of a testing apparatus according to an embodiment of the present invention;
fig. 3 is a test command interface diagram according to an embodiment of the present invention.
Detailed Description
As shown in fig. 1, a SPI communication interface testing arrangement, include: microcontroller, dual supply circuit, overload protection circuit, power-on and power-off control circuit and PC end, SPI communication interface and microcontroller intercommunication, dual supply circuit output gives overload protection circuit with voltage signal transmission, and carry out signal control by microcontroller, overload protection circuit output links to each other with microcontroller's supply voltage end VCC, power-on and power-off circuit input links to each other with overload protection circuit output, microcontroller is to power-on and power-off circuit transmission control signal, and power-on and power-off circuit's output is connected with SPI communication interface's supply voltage end VCC, PC end and microcontroller interconnect.
101 in FIG. 1 does high-speed 108MHz QSPI testing arrangement body, use distinctive 108MHz QSPI hardware in microcontroller STM32F7, via USB bridge SPI communication interface for connect 102 in FIG. 1, SPI determinand is like SPI NAND Flash, sees through the USB again and is connected with the PC, uses 103 software in FIG. 1 to accomplish high-speed 108MHz QSPI order verification test.
The device still include SMSC company's USB3315, USB3315 installs on microcontroller's USB interface, the PC end is connected with plus USB3315, it is for the fast-speed test of cooperation, need promote test platform and PC's communication speed, consequently, plus USB 2.0's PHY, promote STM32F7 built-in USB 1.1's speed originally to 2.0, plus device has used SMSC company's USB 3315.
The dual-power circuit provides two power switching modes, the USB 5V is converted into 3.3V and 1.8V, the GPIO1 in the MCU switches voltage through the USB, the voltage output by the MCU is controlled by the power-on and power-off control circuit through the GPIO0 in the MCU to be supplied to an element to be tested, and the power-on and power-off test is completed through the USB by software, and the overload protection circuit is used for preventing an object to be tested from being short-circuited to cause overlarge current so as to achieve the purpose of protecting the microcontroller.
The PC comprises a software interface for testing, and the software interface comprises button starting and closing buttons and a power supply selection button.
As shown in fig. 2, the power on/off control circuit 2 controls the power on/off of the SPI device under test through the USB to the MCU and the GPIO0, so that the power on/off test item can be implemented, and the overload protection circuit 1 provides overload protection to prevent the SPI device under test from short-circuiting.
The power-on and power-off control circuit 2 comprises a first field-effect tube P3, a first phase inverter and a second field-effect tube N1, wherein the source electrode of the first field-effect tube P3 is connected with a power supply voltage end VCC of the microcontroller, the drain electrode of the first field-effect tube P3 is connected with the power supply voltage end VCC of the SPI communication interface, two grid electrodes of the P3 and the N1 are connected, and then the first field-effect tube P3 is connected with the first phase inverter and is connected with GPIO0 of the microcontroller, and the microcontroller sends a control. The drain electrode of the second field effect transistor N1 is connected to the power supply voltage end of the SPI communication interface, and the source electrode is grounded.
The operation principle of the power on/off control circuit 2 is as follows: when a motor starting button of a worker is pressed, a GPIO0 port of the microcontroller is set to be 1, namely, high level, the first field effect transistor P3 is conducted, SPI communication hardware is electrified, and the second field effect transistor N1 is cut off due to the connection of the phase inverter, so that the short circuit between a power supply and the ground is avoided; when the worker clicks the closing button, the GPIO0 port of the microcontroller is set to 0, namely, the low level, the first field effect transistor P3 is cut off, the SPI communication hardware is not powered on, and the second field effect transistor N1 is switched on due to the existence of the phase inverter.
The dual-power circuit 3 comprises a 1.8V low-power LDO, a 3.3V low-power LDO, a third field-effect tube P1, a fourth field-effect tube P2 and a second inverter, wherein the source electrode of the third field-effect tube P1 is connected with the 1.8V low-power LDO, the source electrode of the fourth field-effect tube P2 is connected with the 3.3V low-power LDO, the input of the dual-power circuit is 5V, a control signal is transmitted by the microcontroller to determine whether the 5V voltage is converted into 1.8V or 3.3V, the drain electrodes of the third field-effect tube P1 and the fourth field-effect tube P2 are connected and input a signal into the overload protection circuit, the grid electrode of the third field-effect tube P1 is connected with the second inverter, the grid electrode of the fourth field-effect tube P2 is commonly connected to the control end of the microcontroller, and the microcontroller.
The working principle of the dual power supply circuit 3 is as follows: when a worker selects a 1.8V power supply button, the GPIO1 port of the microcontroller is set to be 1, the third field effect tube is conducted, the SPI communication interface is electrified by 1.8V, and the fourth field effect tube is cut off due to the existence of the phase inverter; the staff selects the 3.3V power button, and GPIO1 port of microcontroller puts 0, because there is the inverter, the third field effect transistor cuts off, and the fourth field effect transistor switches on, and at this moment, 3.3V low-power consumption LDO work, for other module transport 3.3V voltage.
Further, in this embodiment, the overload protection circuit 1 includes a triode Q1, a first resistor R, a second resistor R1 and a third resistor R2, the first resistor R is connected to an emitter of the triode, the second resistor R1 is connected between a collector and a base of the triode, the third resistor R2 is connected between the base and the emitter of the triode, an output end of the third resistor R2 is connected to the power-on/off control circuit 2 and is finally connected to a supply voltage terminal VCC of the microcontroller, short circuit of an object to be tested is prevented, and safety of the device during use is improved.
As shown in fig. 3, the working process of the present invention includes:
the operation mode is as follows:
1. connecting an object to be tested (108 MHz);
2. connecting the USB to the PC terminal;
3. starting PC end test software, setting 108MHz, selecting 3.3V/1.8V and issuing various test combination commands (including whether to carry out power on/off test) or independently carrying out read-write test.
Further, the PC software can directly issue the SPI application commands corresponding to various formats, report the execution result to obtain the test result, and combine different command sequences to test whether the SPI application commands conform to the protocol specification of the SPI device.
Further, the actions of the PC side are received and responded, the firmware in the test platform is used as an actual executor, and the 1bit, 2bit, 4bit and Quad commands are switched or automatic read-write test is carried out according to the instruction of PC software, and the execution and the result are returned.
The utility model discloses a STM32F7 MCU has realized the platform of high-speed 108MHz QSPI interface and test SPI command, only need can accomplish the verification instrument of communication protocol test with a set of USB2.0 and PC, connect via software control completion command test and automatic reading and writing test by PC, and select because of having added the dual voltage, can reduce exchange test platform's manual operation error risk and include overload protection via software control switching voltage, can prevent to cause the possibility of MCU damage when the determinand takes place the short circuit.
The method provides a 108MHz QSPI test verification method, and also solves the problems that the complexity of a test platform also reduces the cost of the test platform and can meet the requirements of SPI command verification and high-speed reading and writing.
Claims (8)
1. An SPI communication interface testing arrangement, its characterized in that includes: microcontroller, dual supply circuit, overload protection circuit, power-on and power-off control circuit and PC end, SPI communication interface with microcontroller intercommunication, dual supply circuit output gives voltage signal overload protection circuit, and by microcontroller carries out signal control, overload protection circuit output with microcontroller's supply voltage end links to each other, power-on and power-off input with overload protection circuit output links to each other, and microcontroller is to power-on and power-off transmission control signal, and power-on and power-off circuit's output with SPI communication interface's supply voltage end is connected, PC end and microcontroller interconnect.
2. The SPI communication interface testing device of claim 1, wherein the microcontroller is of the STM32F7 family.
3. The SPI communication interface test device according to claim 2, wherein the SPI communication interface is connected to a QSPI interface of the microcontroller.
4. The SPI communication interface test device according to claim 2, further comprising a USB3315 of SMSC company, wherein the USB3315 is mounted on a USB interface of the microcontroller, and a PC terminal is connected to the additional USB 3315.
5. The SPI communication interface testing device according to claim 2, wherein the power on/off control circuit receives the control signal through a microcontroller interface GPIO0, and the dual power supply circuit receives the control signal through a microcontroller interface GPIO 1.
6. The SPI communication interface test device according to claim 1 or 2, wherein the overload protection circuit comprises a transistor, a first resistor, a second resistor and a third resistor, the first resistor being connected to an emitter terminal of the transistor, the second resistor being connected between a collector and a base of the transistor, and the third resistor being connected between the base and the emitter of the transistor.
7. The SPI communication interface testing device according to claim 1 or 2, wherein the power-on/off circuit comprises a first fet, a first inverter, and a second fet, wherein a source of the first fet is connected to a supply voltage terminal of the microcontroller, a drain of the first fet is connected to a supply voltage terminal of the SPI communication interface, a gate of the first fet is connected to the first inverter after being interconnected to a gate of the second fet, the microcontroller transmits the control signal thereto, a drain of the second fet is connected to the supply voltage terminal of the SPI communication interface, and a source of the second fet is grounded.
8. The SPI communication interface testing device of claim 1 or 2, wherein the dual power supply circuit comprises a 1.8V low-power LDO, a 3.3V low-power LDO, a third field-effect tube, a fourth field-effect tube and a second inverter, wherein a source electrode of the third field-effect tube is connected with the 1.8V low-power LDO, a source electrode of the fourth field-effect tube is connected with the 3.3V low-power LDO, drain electrodes of the third field-effect tube and the fourth field-effect tube are connected with each other and input a signal into the overload protection circuit, a gate electrode of the third field-effect tube is connected with the second inverter, a gate electrode of the fourth field-effect tube is connected with a control terminal of the microcontroller, and the microcontroller transmits a control signal to the second inverter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020943494.8U CN212846771U (en) | 2020-05-29 | 2020-05-29 | SPI communication interface testing arrangement |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020943494.8U CN212846771U (en) | 2020-05-29 | 2020-05-29 | SPI communication interface testing arrangement |
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| Publication Number | Publication Date |
|---|---|
| CN212846771U true CN212846771U (en) | 2021-03-30 |
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| CN202020943494.8U Active CN212846771U (en) | 2020-05-29 | 2020-05-29 | SPI communication interface testing arrangement |
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| CN (1) | CN212846771U (en) |
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