CN212749147U - Chip test adapter plate and chip adapter test system - Google Patents
Chip test adapter plate and chip adapter test system Download PDFInfo
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- CN212749147U CN212749147U CN202021008475.2U CN202021008475U CN212749147U CN 212749147 U CN212749147 U CN 212749147U CN 202021008475 U CN202021008475 U CN 202021008475U CN 212749147 U CN212749147 U CN 212749147U
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Abstract
The utility model is suitable for chip test technical field, especially, relate to a chip test keysets and chip switching test system, wherein, the chip test keysets includes first winding displacement interface, second winding displacement interface and interface channel, interface channel communicates the signal interface of two winding displacement interfaces the same type, during the chip test, first winding displacement interface passes through the winding displacement and connects first chip test machine, the second winding displacement interface passes through the test card that the winding displacement is connected the second chip, thereby realize the test card switching compatible use of first chip test machine and second chip test machine, need not to make the card again, improve the utilization ratio of different chip test machines and test card, the wasting of resources test machine has been reduced.
Description
Technical Field
The utility model belongs to the technical field of the chip test, especially, relate to a chip test keysets and chip switching test system.
Background
Chips have become an irreplaceable part in people's lives, and with the development of science and technology, chips are also more and more important, and the demand of the chips is also increasing. For the chip testing industry, developers can perform platform-to-platform upgrading of testing programs under the condition of limited resources, and production enterprises can more flexibly allocate existing testing resources under the condition of limited resources, which is undoubtedly very important.
During the development of the chip test program, probe cards used by the testers of different platforms are different. If the project needs to be tested on different platforms, cards need to be manufactured again, time is consumed, and in the production process, due to the limitation of resource conditions of a test factory, the problem that a test machine and a probe card are idle but cannot be matched due to the fact that the test machine and the probe card are not of the same model exists, and resources are wasted is often caused.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a chip test keysets aims at solving because of the problem that the test card can not generally lead to the wasting of resources between the different test machines.
The embodiment of the utility model provides a first aspect provides a chip test keysets, and chip test keysets includes first winding displacement interface, second winding displacement interface and interface channel;
the first bus interface comprises a plurality of signal interfaces which are in adaptive connection with the first chip testing machine, the second bus interface comprises a plurality of signal interfaces which are in adaptive connection with the testing card of the second chip testing machine, and the same type of signal interfaces in the first bus interface and the second bus interface are correspondingly connected through the connecting channel.
In one embodiment, the first bus bar interface includes a plurality of first bus bars, each of the first bus bars is connected with the first chip tester in an adaptive manner through a flat cable, and the second bus bar interface includes a plurality of second bus bars, each of the second bus bars is connected with the test card of the second chip tester in an adaptive manner through a flat cable.
In one embodiment, the plurality of first and second sockets each comprise a DPS resource interface socket, a URC resource interface socket, and a plurality of channel interface sockets.
In one embodiment, the number of the channel interface female sockets is 8.
In one embodiment, the first chip tester is a Chroma tester and the second chip tester is a TR6836 tester;
each channel interface mother socket of the first mother socket comprises 64 channel signal interfaces, the DPS resource interface mother socket of the first mother socket comprises 64 DPS resource signal interfaces, and the URC resource interface mother socket of the first mother socket comprises 64 URC resource signal interfaces;
each channel interface female of the second female sockets comprises 40 channel signal interfaces, the DPS resource interface female of the second female sockets comprises 68 DPS resource signal interfaces, and the URC resource interface female of the second female sockets comprises 68 URC resource signal interfaces.
In one embodiment, the first chip tester is a TR6836 tester, and the second chip tester is a Chroma tester;
each channel interface mother bay of the first mother bay comprises 40 channel signal interfaces, the DPS resource interface mother bay of the first mother bay comprises 68 DPS resource signal interfaces, and the URC resource interface mother bay of the first mother bay comprises 68 URC resource signal interfaces;
each channel interface mother socket of the second mother socket comprises 64 channel signal interfaces, the DPS resource interface mother socket of the second mother socket comprises 64 DPS resource signal interfaces, and the URC resource interface mother socket of the second mother socket comprises 64 URC resource signal interfaces.
In one embodiment, the connection channels include a plurality of channel signal connection channels, a plurality of DPS resource connection channels, a plurality of URC resource connection channels, a ground connection channel, and a power connection channel.
In one embodiment, the number of channels of the plurality of channel signal connection channels is 256, the number of channels of the plurality of DPS resource connection channels is 32, and the number of channels of the plurality of URC resource connection channels is 7.
The utility model discloses the second aspect of embodiment provides a chip switching test system, chip switching test system include the test card of first chip test machine, second chip test machine and as above the chip test keysets, first chip test machine the chip test keysets with the test card of second chip test machine electric connection in proper order.
In one embodiment, the first chip tester and the second chip tester are a Chroma tester and a TR6836 tester, respectively.
The utility model discloses a first winding displacement interface, chip test keysets is constituteed to second winding displacement interface and interface channel, interface channel communicates the signal interface of two winding displacement interfaces the same type, during the chip test, first chip test machine is connected through the winding displacement to first winding displacement interface, the second winding displacement interface passes through the test card that the winding displacement is connected the second chip test machine, thereby realize the compatible use of test card switching of first chip test machine and second chip test machine, need not to make the card again, improve the utilization ratio of different chip test machines and test card, the wasting of resources has been reduced.
Drawings
Fig. 1 is a first schematic structural diagram of a chip test interposer according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a second structure of a chip test interposer according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a third chip test adapter board according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a fourth structure of a chip test interposer according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a fifth structure of a chip test interposer according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a sixth structure of the chip testing interposer according to an embodiment of the present invention.
Detailed Description
In order to make the technical problem, technical solution and advantageous effects to be solved by the present invention more clearly understood, the following description is given in conjunction with the accompanying drawings and embodiments to illustrate the present invention in further detail. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.
A first aspect of the embodiments of the present invention provides a chip test interposer 100.
As shown in fig. 1, fig. 1 is a first schematic structural diagram of a chip testing interposer 100 according to an embodiment of the present invention, in this embodiment, the chip testing interposer 100 includes a first bus interface 10, a second bus interface 20, and a connection channel 30;
the first bus interface 10 includes a plurality of signal interfaces adapted to the first chip tester 200, the second bus interface 20 includes a plurality of signal interfaces adapted to the test card 300 of the second chip tester, and the same type of signal interfaces of the first bus interface 10 and the second bus interface 20 are correspondingly connected through the connection channel 30.
In this embodiment, the chip test adapter plate 100 is suitable for signal switching between a Chroma tester and a TR6836 tester, and because the types of signal interfaces of the Chroma tester and the TR6836 tester are different, a test card of one chip tester and a test card of another chip tester cannot be directly connected, in this embodiment, a test adapter plate is arranged between the Chroma tester and the TR6836 tester, that is, the chip test adapter plate 100 can be connected between the Chroma tester and the test card of the TR6836 tester, or between the test card of the Chroma tester and the TR6836 tester, and is respectively provided with a first bus interface 10 of the same type as the chip tester and a second bus interface 20 of the same type as the test card of the other chip tester, it can be understood that different chip testers are provided with a plurality of signal interfaces including a test signal interface and a redundant signal interface, in order to realize the same chip testing function, the number and types of the test signal interfaces are the same, so that the connection channel 30 connects the test signal interfaces with the same type and function between the first flat cable interface 10 and the second flat cable interface 20, so as to realize the transmission of the test signals, further realize the switching and compatible use of the test card 300 of the first chip tester 200 and the second chip tester, and no card re-manufacturing is needed, thereby improving the utilization rate of different chip testers and test cards, and reducing the resource waste.
In this embodiment, the type and structure of the first bus interface 10 are set correspondingly according to the signal interface of the first chip tester 200, and in one embodiment, the type of the first bus interface 10 is the same as the structure and type of the bus interface of the original test card of the first chip tester 200, so that during connection test, the bus between the original first chip tester 200 and the test card can be used without redesigning the bus, thereby reducing the cost.
Similarly, the type and structure of the second flat cable interface 20 are correspondingly configured according to the signal interface of the test card 300 of the second chip tester, and in an embodiment, the type of the second flat cable interface 20 is the same as the structure and type of the flat cable interface of the test card 300 of the second chip tester, so that when in connection test, the flat cable between the original second chip tester and the test card can be adopted, and the flat cable does not need to be redesigned, thereby reducing the cost.
The utility model discloses a first winding displacement interface 10, chip test keysets 100 is constituteed to second winding displacement interface 20 and interface channel 30, interface channel 30 communicates the signal interface of two winding displacement interfaces the same type, during the chip test, first chip test machine 200 is connected through the winding displacement to first winding displacement interface 10, second chip test machine's test card 300 is connected through the winding displacement to second winding displacement interface 20, thereby realize the compatible use of test card 300 switching of first chip test machine 200 and second chip test machine, need not to make the card again, improve the utilization ratio of different chip test machines and test card, the wasting of resources has been reduced.
As shown in fig. 2, in one embodiment, the first bus bar interface 10 includes a plurality of first female sockets, such as female sockets 11, 12, and 13, each of which is adapted to be connected to the first chip testing machine 200 via a bus bar, and the second bus bar interface 20 includes a plurality of second female sockets, such as female sockets 21, 22, and 23, each of which is adapted to be connected to the test card 300 of the second chip testing machine via a bus bar.
In this embodiment, since the test cards 300 of the first chip tester 200 and the second chip tester have a plurality of types of signal interfaces and transmit a plurality of different types of test signals, as shown in tables 1 and 2, table 1 is a resource of internal channels of the Chroma tester, table 2 is a resource of internal channels of the TR6836 tester, the resource of internal channels of the Chroma tester includes a plurality of channel resources, URC resources and DPS resources, transmits different signals and uses different numbers of PIN cables, and similarly, the resource of internal channels of the TR6836 tester includes a plurality of channel resources, URC resources and DPS resources and uses different numbers of PIN cables from the Chroma tester, in order to adapt to the Chroma tester and the TR6836 tester themselves or their test cards and to facilitate connection, the first bus interface 10 and the second bus interface 20 each include a plurality of female sockets and are connected to the chip tester and the test card through one bus respectively, in one embodiment, each of the first and second bus bar seats is provided with 10 bus bar seats.
TABLE 1
TABLE 2
As shown in tables 1 and 2, in order to adapt to the Chroma tester and the TR6836 tester or their test cards, in an embodiment, each of the first female sockets and the second female sockets includes a DPS resource interface female socket, a URC resource interface female socket, and a plurality of channel interface female sockets, the plurality of channel interface female sockets are respectively connected to corresponding channel interfaces of the tester or the test card in an adaptive manner by a flat cable, the URC resource interface female socket is connected to the URC resource interface of the tester or the test card in an adaptive manner by a flat cable, the DPS resource interface female socket is connected to the DPS resource interface of the tester or the test card in an adaptive manner by a flat cable, in an embodiment, the number of the channel interface female sockets is 8, and in order to reduce the number of the female sockets and simplify the structure, in an embodiment, the DPS resource interface female sockets and the URC resource interface female sockets are combined into one resource interface female socket.
As shown in fig. 3 and 4, fig. 3 shows a first channel interface female socket of the second flat cable interface 20 of the chip test interposer 100, fig. 4 shows a first channel interface female socket of the first flat cable interface 10 of the chip test interposer 100, the first channel interface female socket of the second flat cable interface 20 is connected to a first channel interface of a test card of the TR6836 test machine through a 40PIN flat cable, the first channel interface female socket of the first flat cable interface 10 is connected to a first channel interface of the Chroma test machine through a 64PIN flat cable, meanwhile, T0-T31 signal interfaces in the first channel interface female socket of the first flat cable interface 10 are correspondingly connected to T0-T31 signal interfaces in the first channel interface female socket of the second flat cable interface 20 one by one, and meanwhile, a plurality of redundant signal interfaces are all left or grounded.
And as shown in fig. 5 and fig. 6, fig. 5 shows the interface female seats of DPS resource and URC resource of the second traverse interface 20 of the chip test patch board 100, which illustrates the interface female seats of DPS resource and URC resource of the first traverse interface 10 of the chip test patch board 100, the interface female seats of DPS resource and URC resource of the second traverse interface 20 are adaptively connected with the channel interfaces of test card DPS resource and URC resource of TR6836 tester through four 68PIN cables, the interface female seats of DPS resource and URC resource of the first traverse interface 10 are adaptively connected with the channel interfaces of test card DPS resource and URC resource of TR6836 tester through two 64PIN cables, and the DPS 0-7 and the DPS 0-UR 31 of the interface female seats of the DPS resource and URC resource of the first traverse interface 10 and the URC resource are adaptively connected with the DPS 0-DPS 3932 and the RUs 387 2-RU 39387 387 2 of the interface female seats of the DPS resource and URC resource of the first traverse interface female interfaces of TR resource of the first traverse interface 20 through two 64 connecting channels 30, the +5V and + -15V signal interfaces are respectively connected in an adaptive manner, so that the transmission of the DPS resource and the URC resource is realized, and the redundant signal interfaces are grounded or vacant.
According to different connection positions and use scenes, the chip test adapter board 100 has two connection modes, in one embodiment, the first chip tester 200 is a Chroma tester, the second chip tester is a TR6836 tester, and the chip test board is connected between test cards of the Chroma tester and the TR6836 tester;
each channel interface mother socket of the first mother socket comprises 64 channel signal interfaces, the DPS resource interface mother socket of the first mother socket comprises 64 DPS resource signal interfaces, and the URC resource interface mother socket of the first mother socket comprises 64 URC resource signal interfaces;
each channel interface mother bay of the second mother bay comprises 40 channel signal interfaces, the DPS resource interface mother bay of the second mother bay comprises 68 DPS resource signal interfaces, and the URC resource interface mother bay of the second mother bay comprises 68 URC resource signal interfaces.
As shown in Table 1, according to the channel resource type of the Chroma tester, a plurality of first mother sockets are adapted and connected, namely, when the channel resource channels SLOT 0-SLOT 7 of the Chroma testing machine all adopt 64PIN flat cables, each channel interface female socket of the first female socket is provided with 64 channel signal interfaces in a matching way, similarly, the DPS resource interface female socket of the first female socket is provided with 64 DPS resource signal interfaces, the URC resource interface female socket of the first female socket is provided with 64 URC resource signal interfaces, as shown in table 2, a plurality of second female seats are arranged in a matching connection way according to the channel resource type of the TR6836 testing machine, namely, when the channel interfaces 1-7 of the test card of the TR6836 tester all adopt 40PIN flat cables, each channel interface female seat of the second female seat is provided with 40 channel signal interfaces in a matching way, similarly, the DPS resource interface female seat of the second female seat is provided with 68 DPS resource signal interfaces, and the URC resource interface female seat of the second female seat is provided with 68 URC resource signal interfaces.
In one embodiment, when the first chip tester 200 is a TR6836 tester and the second chip tester is a Chroma tester, i.e., the chip test board is connected between the test card of the Chroma tester and the TR6836 tester, as shown in tables 1 and 2, each channel interface socket of the first socket includes 40 channel signal interfaces, the DPS resource interface socket of the first socket includes 68 DPS resource signal interfaces, and the URC resource interface socket of the first socket includes 68 URC resource signal interfaces;
each channel interface mother bay of the second mother bay comprises 64 channel signal interfaces, the DPS resource interface mother bay of the second mother bay comprises 64 DPS resource signal interfaces, and the URC resource interface mother bay of the second mother bay comprises 64 URC resource signal interfaces.
In one embodiment, the connection channels 30 include a plurality of channel signal connection channels 30, a plurality of DPS resource connection channels 30, a plurality of URC resource connection channels 30, a ground connection channel 30, and a power connection channel 30.
In this embodiment, the connection channels 30 are correspondingly arranged according to the types and numbers of signals transmitted between the tester and the test card, as shown in table 1 and table 2, the signals transmitted between the tester and the test card include channel signals, DPS resources, URC resources, and corresponding power signals, and therefore, in order to adapt to the first bus interface 10 and the second bus interface 20, the connection channels 30 are provided with a plurality of channel signal connection channels 30, a plurality of DPS resource connection channels 30, a plurality of URC resource connection channels 30, a ground connection channel 30, and a power connection channel 30, and in one embodiment, the number of the plurality of channel signal connection channels 30 is 256, the number of the plurality of DPS resource connection channels 30 is 32, and the number of the plurality of URC resource connection channels 30 is 7.
As shown in fig. 1, the second aspect of the embodiment of the present invention provides a chip transfer testing system, which comprises a first chip testing machine 200, a testing card 300 of a second chip testing machine, and a chip testing adapter plate 100, wherein the specific structure of the chip testing adapter plate 100 refers to the above embodiments, and since the chip transfer testing system adopts all the technical solutions of all the above embodiments, all the beneficial effects brought by the technical solutions of the above embodiments are at least achieved, which is not repeated herein. Wherein, the first chip tester 200, the chip test adapter plate 100 and the test card 300 of the second chip tester are electrically connected in sequence, wherein, the chip test adapter plate 100 is suitable for signal switching between a Chroma tester and a TR6836 tester, namely, in one embodiment, the first chip tester 200 and the second chip tester are respectively a Chroma tester and a TR6836 tester, the chip test adapter plate 100 can be connected between the Chroma tester and the test card of the TR6836 tester, or between the test card of the Chroma tester and the TR6836 tester, and is respectively provided with a first wire arranging interface 10 with the same type as the chip tester and a second wire arranging interface 20 with the same type as the test card of the other type of chip tester, thereby realizing the switching compatibility use of the first chip tester 200 and the test card 300 of the second chip tester without card reproduction and improving the utilization rate of different chip testers and test cards, the resource waste is reduced.
The above-mentioned embodiments are only used for illustrating the technical solution of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (10)
1. A chip test adapter plate is characterized by comprising a first bus interface, a second bus interface and a connecting channel;
the first bus interface comprises a plurality of signal interfaces which are in adaptive connection with the first chip testing machine, the second bus interface comprises a plurality of signal interfaces which are in adaptive connection with the testing card of the second chip testing machine, and the same type of signal interfaces in the first bus interface and the second bus interface are correspondingly connected through the connecting channel.
2. The chip test interposer as recited in claim 1, wherein the first bus interface comprises a plurality of first female sockets, each of the first female sockets is adapted to connect to a first chip tester via a flat cable, and the second bus interface comprises a plurality of second female sockets, each of the second female sockets is adapted to connect to a test card of a second chip tester via a flat cable.
3. The chip test patch panel of claim 2, wherein the plurality of first female sockets and the plurality of second female sockets each comprise a DPS resource interface female socket, a URC resource interface female socket, and a plurality of channel interface female sockets.
4. The chip test interposer as recited in claim 3, wherein the number of said channel interface female sockets is 8.
5. The chip test interposer as recited in claim 4, wherein said first chip tester is a Chroma tester and said second chip tester is a TR6836 tester;
each channel interface mother socket of the first mother socket comprises 64 channel signal interfaces, the DPS resource interface mother socket of the first mother socket comprises 64 DPS resource signal interfaces, and the URC resource interface mother socket of the first mother socket comprises 64 URC resource signal interfaces;
each channel interface female of the second female sockets comprises 40 channel signal interfaces, the DPS resource interface female of the second female sockets comprises 68 DPS resource signal interfaces, and the URC resource interface female of the second female sockets comprises 68 URC resource signal interfaces.
6. The chip test interposer as recited in claim 4, wherein said first chip tester is a TR6836 tester, and said second chip tester is a Chroma tester;
each channel interface mother bay of the first mother bay comprises 40 channel signal interfaces, the DPS resource interface mother bay of the first mother bay comprises 68 DPS resource signal interfaces, and the URC resource interface mother bay of the first mother bay comprises 68 URC resource signal interfaces;
each channel interface mother socket of the second mother socket comprises 64 channel signal interfaces, the DPS resource interface mother socket of the second mother socket comprises 64 DPS resource signal interfaces, and the URC resource interface mother socket of the second mother socket comprises 64 URC resource signal interfaces.
7. The chip test patch panel of claim 5 or 6, wherein the connection channels comprise a plurality of channel signal connection channels, a plurality of DPS resource connection channels, a plurality of URC resource connection channels, a ground connection channel, and a power connection channel.
8. The chip test patch panel of claim 7, wherein the plurality of channel signal connection channels has a channel number of 256, the plurality of DPS resource connection channels has a channel number of 32, and the plurality of URC resource connection channels has a channel number of 7.
9. A chip switching test system is characterized by comprising a first chip tester, a test card of a second chip tester and the chip test switching plate according to any one of claims 1 to 8, wherein the first chip tester, the chip test switching plate and the test card of the second chip tester are electrically connected in sequence.
10. The chip transfer test system of claim 9, wherein the first chip tester and the second chip tester are a Chroma tester and a TR6836 tester, respectively.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021008475.2U CN212749147U (en) | 2020-06-04 | 2020-06-04 | Chip test adapter plate and chip adapter test system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021008475.2U CN212749147U (en) | 2020-06-04 | 2020-06-04 | Chip test adapter plate and chip adapter test system |
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| CN212749147U true CN212749147U (en) | 2021-03-19 |
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| CN202021008475.2U Active CN212749147U (en) | 2020-06-04 | 2020-06-04 | Chip test adapter plate and chip adapter test system |
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Address after: 518000 1st, 5th and 6th floors of No. 1 workshop, No. 28 Qingfeng Avenue, Baolong Street, Longgang District, Shenzhen City, Guangdong Province Patentee after: Shenzhen mifitech Technology Co.,Ltd. Address before: 518000 1st, 5th and 6th floors of No. 1 workshop, No. 28 Qingfeng Avenue, Baolong Street, Longgang District, Shenzhen City, Guangdong Province Patentee before: Shenzhen Mifeitake Technology Co.,Ltd. |