CN212725313U - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN212725313U CN212725313U CN202021976505.9U CN202021976505U CN212725313U CN 212725313 U CN212725313 U CN 212725313U CN 202021976505 U CN202021976505 U CN 202021976505U CN 212725313 U CN212725313 U CN 212725313U
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Abstract
The application discloses a display panel and a display device. The display panel comprises a substrate, an array substrate positioned on the substrate, a pixel definition layer positioned on the array substrate, a light-emitting device layer positioned on the pixel definition layer, and a cathode layer positioned on the light-emitting device layer; the pixel definition layer comprises a plurality of first openings, and the first openings penetrate through the pixel definition layer; the display panel also comprises a resistance reduction device positioned between the substrate and the light-emitting device layer, wherein the resistance reduction device comprises a plurality of first resistance reduction devices, and the first resistance reduction devices are electrically connected with the cathode layer through the first openings. This application is through falling resistance device and cathode layer parallel connection, has reduced the resistance impedance of opening part, has reduced the pressure drop of cathode layer, has improved the demonstration homogeneity.
Description
Technical Field
The application relates to the field of display, especially to the technical field of display, and specifically relates to a display panel and a display device.
Background
With the improvement of the living standard, the application of the OLED (Organic Light-Emitting Diode) to a large-sized display screen is more widespread.
In the prior art, when a large-size display screen works, due to the existence of cathode resistance, the voltage drop of a cathode is gradually increased along with the increase of a cathode line, so that the display brightness is uneven, and the visual effect of a user is poor.
Therefore, a display panel and a display device are needed to solve the above technical problems.
Disclosure of Invention
The application provides a display panel and display device to solve prior art, jumbo size display screen is at the during operation, because the existence of cathode resistance, along with the increase of negative pole line, the voltage drop of negative pole aggravates gradually, leads to showing luminance inequality, makes the relatively poor technical problem of user's visual effect.
In order to solve the above problems, the technical solution provided by the present application is as follows:
a display panel includes a substrate, an array substrate on the substrate, a pixel defining layer on the array substrate, a light emitting device layer on the pixel defining layer, and a cathode layer on the light emitting device layer;
the pixel definition layer comprises a plurality of first openings, and the first openings penetrate through the pixel definition layer;
the display panel further comprises a resistance reduction device positioned between the substrate and the light-emitting device layer, wherein the resistance reduction device comprises a plurality of first resistance reduction devices, and the first resistance reduction devices are electrically connected with the cathode layer through the first openings.
In the display panel of the present application, the first resistance reduction device is located in the first opening.
In the display panel of the present application, the resistance reduction device and the gate layer of the array substrate are disposed in the same layer.
In the display panel of the present application, the resistance reduction device and the source drain layer of the array substrate are disposed on the same layer.
In the display panel of the present application, the first resistance reducing device includes a first sub-resistance reducing device and a second sub-resistance reducing device, and the first sub-resistance reducing device and the second sub-resistance reducing device are connected in parallel;
the first sub resistance reducing device and the grid layer of the array substrate are arranged in the same layer;
the second sub-resistance reducing device and the source drain layer of the array substrate are arranged on the same layer.
In the display panel of the present application, the display panel further includes an anode layer between the pixel defining layer and the array substrate;
the pixel defining layer further comprises a plurality of second openings, the second openings penetrate through the pixel defining layer, and the light emitting device layer and the cathode layer are filled in the second openings;
the anode layer comprises a first anode electrically connected to the cathode layer through the second opening;
the resistance reducing device further comprises a plurality of second resistance reducing devices, and the second resistance reducing devices are electrically connected with the cathode layer through the second openings.
In the display panel of the present application, the anode layer further includes a second anode, and the second anode is disposed on the same layer as the first anode;
the second anode is electrically connected to the cathode layer through the first opening.
In the display panel of the present application, the second resistance reduction device is located in the second opening.
In the display panel, the distribution density of the resistance reducing devices close to the center of the display panel is greater than the distribution density of the resistance reducing devices far away from the center of the display panel.
A display device comprises any one of the display panel, the polarizer layer and the cover plate layer.
Has the advantages that: this application is through falling resistance device and cathode layer parallel connection, has reduced the resistance impedance of opening part, has reduced the pressure drop of cathode layer, has improved the demonstration homogeneity.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
FIG. 1 is a schematic structural diagram of a first structure of a display panel according to the present application;
FIG. 2 is a schematic structural diagram of a second structure of a display panel according to the present application;
FIG. 3 is a schematic structural diagram of a third structure of a display panel according to the present application;
FIG. 4 is a schematic structural diagram of a fourth structure of a display panel according to the present application;
fig. 5 is a schematic structural diagram of a display device according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
In the prior art, when a large-size display screen works, due to the existence of cathode resistance, the voltage drop of a cathode is gradually increased along with the increase of a cathode line, so that the display brightness is uneven, and the visual effect of a user is poor. Based on this, the present application provides a display panel and a display device.
Referring to fig. 1 to 4, the present application provides a display panel 100, where the display panel 100 includes a substrate 200, an array substrate 300 on the substrate 200, a pixel definition layer 500 on the array substrate 300, a light emitting device layer 600 on the pixel definition layer 500, and a cathode layer 700 on the light emitting device layer 600;
the pixel defining layer 500 includes a plurality of first openings 510, the first openings 510 penetrating the pixel defining layer 500;
the display panel 100 further includes a resistance reduction device 800 between the substrate 200 and the light emitting device layer 600, the resistance reduction device 800 includes a plurality of first resistance reduction devices 810, and the first resistance reduction devices 810 are electrically connected to the cathode layer 700 through the first openings 510.
This application is through falling resistance device and cathode layer parallel connection, has reduced the resistance impedance of opening part, has reduced the pressure drop of cathode layer, has improved the demonstration homogeneity.
The technical solution of the present application will now be described with reference to specific embodiments.
Referring to fig. 1 to 4, the display panel 100 includes a substrate 200, an array substrate 300 on the substrate 200, a pixel definition layer 500 on the array substrate 300, a light emitting device layer 600 on the pixel definition layer 500, and a cathode layer 700 on the light emitting device layer 600. The pixel defining layer 500 includes a plurality of first openings 510, and the first openings 510 penetrate the pixel defining layer 500. The display panel 100 further includes a resistance reduction device 800 between the substrate 200 and the light emitting device layer 600, the resistance reduction device 800 includes a plurality of first resistance reduction devices 810, and the first resistance reduction devices 810 are electrically connected to the cathode layer 700 through the first openings 510.
In this embodiment, the array substrate 300 includes a light-shielding layer, a gate layer 310 located on the light-shielding layer, a gate insulating layer 320 located on the gate layer 310, and a source drain layer 330 located on the gate insulating layer 320, specifically refer to fig. 3 and fig. 4.
The light emitting device layer 600 includes a hole injection layer 610, a hole transport layer 620, a light emitting material layer 630, an electron transport layer 640, and an electron injection layer, the electron injection layer is not shown in the drawings, and the hole injection layer 610 is close to the anode layer, as shown in fig. 1 to 4.
In this embodiment, the array substrate 300 further includes a semiconductor layer, the semiconductor layer is an active layer, the semiconductor layer may be located on the source/drain layer 330, or the semiconductor layer may be located on the gate insulating layer 320, or the gate layer 310 is located on the semiconductor layer, the semiconductor layer is located on the substrate 200, and a specific position of the semiconductor layer is not limited herein.
In this embodiment, the first resistance reducing device 810 is located in the first opening 510, please refer to fig. 2 specifically. The first resistance reducing device 810 can simplify the film process in the first opening 510, and is beneficial to the planarization of the films of the display panel 100, so that the films have better adhesion and the alignment difficulty is reduced.
In the embodiment, the resistance reduction device is connected with the cathode layer in parallel, so that the resistance impedance at the opening is reduced, the voltage drop of the cathode layer is reduced, and the display uniformity is improved.
In this embodiment, the first opening 510 is filled with the electron transport layer 640 of the light emitting device layer 600 and the cathode layer 700, as shown in fig. 1 to 4. The distance between the first resistance reducing device 810 and the cathode layer 700 is reduced, so that the resistance between the first resistance reducing device 810 and the cathode layer 700 is reduced to the maximum, the influence of the voltage drop of the display panel 100 is reduced, and the display uniformity of the panel is improved.
In this embodiment, the resistance reducing device 800 and the source drain layer 330 of the array substrate 300 are disposed in the same layer. The first opening 510 penetrates through any one of the film layers on the source/drain layer 330, the first resistance reducing device 810 is exposed by the first opening 510, and the first resistance reducing device 810 is electrically connected to the cathode layer 700 through the first opening 510, as shown in fig. 3. The method is beneficial to the planarization of the film layers of the display panel 100 while not occupying the space of other film layers, so that the film layers have better adhesion and the alignment difficulty is reduced. The resistance reducing device 800 effectively reduces the resistance at the first opening 510, thereby reducing the influence of the panel voltage drop and improving the display uniformity of the panel.
In this embodiment, the resistance reducing device 800 and the gate layer 310 of the array substrate 300 are disposed in the same layer. The first opening 510 penetrates through the source/drain layer 330 and the gate insulating layer 320, the first resistance reducing device 810 is exposed by the first opening 510, and the first resistance reducing device 810 is electrically connected with the cathode layer 700 through the first opening 510. The resistance reducing device 800 and the source drain layer 330 of the array substrate 300 are arranged in a same layer, and refer to fig. 3 specifically. The method is beneficial to the planarization of the film layers of the display panel 100 while not occupying the space of other film layers, so that the film layers have better adhesion and the alignment difficulty is reduced. The resistance reducing device 800 effectively reduces the resistance at the first opening 510, thereby reducing the influence of the panel voltage drop and improving the display uniformity of the panel.
In this embodiment, the resistance reducing device 800 and the semiconductor layer of the array substrate 300 are disposed in the same layer. The first opening 510 penetrates through any film layer on the semiconductor layer, the first resistance reducing device 810 is exposed by the first opening 510, and the first resistance reducing device 810 is electrically connected with the cathode layer 700 through the first opening 510. The resistance reducing device 800 and the source drain layer 330 of the array substrate 300 are arranged in a same layer, and refer to fig. 3 specifically. The space of other films is not occupied, meanwhile, the planarization of the films of the display panel 100 is facilitated, the adhesion among the films is better, the alignment difficulty degree is reduced, and the resistance reducing device 800 can be arranged in more space due to the fact that the structure of the films of the semiconductor layer is simpler, the requirement on the etching precision etching process is not high, the cost is saved, and the processing difficulty is reduced. The resistance reducing device 800 effectively reduces the resistance at the first opening 510, thereby reducing the influence of the panel voltage drop and improving the display uniformity of the panel.
In this embodiment, the resistance reducing device 800 and the light shielding layer of the array substrate 300 are disposed in the same layer. The first opening 510 penetrates through any film layer on the source drain layer 330, the first resistance reducing device 810 is exposed by the first opening 510, and the first resistance reducing device 810 is electrically connected with the cathode layer 700 through the first opening 510. The resistance reducing device 800 and the source drain layer 330 of the array substrate 300 are arranged in a same layer, and refer to fig. 3 specifically. The space of other films is not occupied, meanwhile, the planarization of the films of the display panel 100 is facilitated, the adhesion among the films is better, the alignment difficulty degree is reduced, and as the structure of the films of the light shielding layer is simpler, more spaces can be provided for the resistance reducing device 800, the requirement on the etching precision etching process is not high, the cost is saved, and the processing difficulty is reduced. The resistance reducing device 800 effectively reduces the resistance at the first opening 510, thereby reducing the influence of the panel voltage drop and improving the display uniformity of the panel.
In this embodiment, the first resistance reducing device 810 includes a first resistance reducing sub-device 811 and a second resistance reducing sub-device 812, and the first resistance reducing sub-device 811 is connected in parallel with the second resistance reducing sub-device 812. The first sub-resistance-reducing device 811 and the gate layer 310 of the array substrate 300 are disposed at the same layer. The second sub-resistance-reducing device 812 and the source drain layer 330 of the array substrate 300 are disposed in the same layer. The second sub resistance-reducing device 812 is electrically connected to the cathode layer 700 through the first opening 510. The first sub-resistance-reducing device 811 and the second sub-resistance-reducing device 812 are connected in parallel by a first connection line 813 and a second connection line 814, please refer to fig. 4. The first resistance reducing device 810 reduces the resistance of the resistance reducing device 800 by connecting the first sub resistance reducing device 811 and the second sub resistance reducing device 812 in parallel, and reduces the resistance impedance at the first opening 510 to the greatest extent, thereby reducing the influence of the voltage drop of the panel and improving the display uniformity of the panel. Meanwhile, the possible fault of the first sub resistance reducing device 811 is avoided to cause resistance reducing failure, and the fault probability is reduced.
In this embodiment, the first sub-resistance-reducing device 811 may be disposed in the same layer as any one of the gate layer 310, the semiconductor layer, the light-shielding layer, and the source/drain layer 330, the second sub-resistance-reducing device 812 may be disposed in a different layer from the first sub-resistance-reducing device 811, and the first sub-resistance-reducing device 811 may be connected in parallel to the second sub-resistance-reducing device 812. The second sub resistance-reducing device 812 is electrically connected to the cathode layer 700 through the first opening 510. The first sub-resistance-reducing device 811 and the second sub-resistance-reducing device 812 are connected in parallel by a first connection line 813 and a second connection line 814. The first sub-resistance-reducing device 811 and the gate layer 310 of the array substrate 300 may be disposed in the same layer, and the second sub-resistance-reducing device 812 and the source drain layer 330 of the array substrate 300 may be disposed in the same layer, as shown in fig. 4. The first resistance reducing device 810 reduces the resistance of the resistance reducing device 800 by connecting the first sub resistance reducing device 811 and the second sub resistance reducing device 812 in parallel, and reduces the resistance impedance at the first opening 510 to the greatest extent, thereby reducing the influence of the voltage drop of the panel and improving the display uniformity of the panel. Meanwhile, the possible fault of the first sub resistance reducing device 811 is avoided to cause resistance reducing failure, and the fault probability is reduced.
In this embodiment, the display panel 100 further includes an anode layer between the pixel defining layer 500 and the array substrate 300. The pixel defining layer 500 further includes a plurality of second openings 520, the second openings 520 penetrate the pixel defining layer 500, and the light emitting device layer 600 and the cathode layer 700 are filled in the second openings 520. The anode layer comprises a first anode 410, and the first anode 410 is electrically connected to the cathode layer 700 through the second opening 520. The resistance reducing device 800 further includes a plurality of second resistance reducing devices 820, and the second resistance reducing devices 820 are electrically connected to the cathode layer 700 through the second openings 520, as shown in fig. 1 to 4. The second opening 520 corresponds to a light emitting opening area of the display panel 100, a large resistance also exists between the anode layer and the cathode layer 700, and the second resistance reducing device 820 can reduce the resistance between the first anode 410 and the cathode layer 700, thereby effectively reducing the resistance impedance at the second opening 520, reducing the influence of the panel voltage drop, and improving the display uniformity of the panel.
In this embodiment, the anode layer further includes a second anode 420, and the second anode 420 is disposed on the same layer as the first anode 410. The second anode 420 is located between the first resistance reducing device 810 and the array substrate 300. The second anode 420 is electrically connected to the cathode layer 700 through the first opening 510, specifically referring to fig. 1 to 4. The second anode 420 is located at the first opening 510, and the second anode 420 may serve as an auxiliary anode of the first anode 410, increasing the conductivity between the anode layer and the cathode layer 700, and decreasing the resistance between the cathode layer 700 and the anode layer.
In this embodiment, the second resistance reduction device 820 is located in the second opening 520, please refer to fig. 2. The second resistance reduction device 820 can simplify the film process in the second opening 520, and is also beneficial to the planarization of the films of the display panel 100, so that the films have better adhesion and the alignment difficulty is reduced.
In this embodiment, the distribution density of the resistance reducing devices 800 near the center of the display panel 100 is greater than the distribution density of the resistance reducing devices 800 far from the center of the display panel 100. The first resistance reducing devices 810 correspond to the first openings 510, and the distribution density of the first openings 510 near the center of the display panel 100 is greater than the distribution density of the first openings 510 far from the center of the display panel 100. The more serious the voltage drop near the center of the display panel 100 is, the poorer the display effect is, so the closer the center of the display panel 100 is, the higher the distribution density of the resistance reducing devices 800 is, the higher the resistance conductivity of the central display area is, and the voltage drop can be reduced better, thereby improving the display effect.
In this embodiment, the resistance reducing device 800 is made of metal oxide. The metal oxide gold is one or a combination of indium gallium zinc oxide, indium tin oxide, indium zinc oxide and indium gallium zinc tin oxide.
In this embodiment, the anode layer is made of a material selected from one or more of copper, aluminum, and titanium.
In this embodiment, the material of the cathode layer 700 is one or a combination of magnesium and silver.
This application is through falling resistance device and cathode layer parallel connection, has reduced the resistance impedance of opening part, has reduced the pressure drop of cathode layer, has improved the demonstration homogeneity.
Referring to fig. 1 to 5, the present application further provides a display device 10, where the display device 100 includes any one of the display panel 100, the polarizer layer 20, and the cover plate layer 30.
This application is through falling resistance device and cathode layer parallel connection, has reduced the resistance impedance of opening part, has reduced the pressure drop of cathode layer, has improved the demonstration homogeneity.
For a specific embodiment, please refer to the above-mentioned embodiment of the display panel 100, which is not described herein again.
The application discloses a display panel and a display device. The display panel comprises a substrate, an array substrate positioned on the substrate, a pixel definition layer positioned on the array substrate, a light-emitting device layer positioned on the pixel definition layer, and a cathode layer positioned on the light-emitting device layer; the pixel definition layer comprises a plurality of first openings, and the first openings penetrate through the pixel definition layer; the display panel also comprises a resistance reduction device positioned between the substrate and the light-emitting device layer, wherein the resistance reduction device comprises a plurality of first resistance reduction devices, and the first resistance reduction devices are electrically connected with the cathode layer through the first openings. This application is through falling resistance device and cathode layer parallel connection, has reduced the resistance impedance of opening part, has reduced the pressure drop of cathode layer, has improved the demonstration homogeneity.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The above embodiments of the present application are described in detail, and specific examples are applied in the present application to explain the principles and implementations of the present application, and the description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A display panel, comprising a substrate, an array substrate on the substrate, a pixel definition layer on the array substrate, a light emitting device layer on the pixel definition layer, and a cathode layer on the light emitting device layer;
the pixel definition layer comprises a plurality of first openings, and the first openings penetrate through the pixel definition layer;
the display panel further comprises a resistance reduction device positioned between the substrate and the light-emitting device layer, wherein the resistance reduction device comprises a plurality of first resistance reduction devices, and the first resistance reduction devices are electrically connected with the cathode layer through the first openings.
2. The display panel of claim 1, wherein the first resistance reducing device is located within the first opening.
3. The display panel of claim 1, wherein the resistance reduction device is disposed in the same layer as a gate layer of the array substrate.
4. The display panel according to claim 1, wherein the resistance reduction device and the source drain layer of the array substrate are disposed in the same layer.
5. The display panel according to claim 1, wherein the first resistance reduction device comprises a first resistance reduction sub-device and a second resistance reduction sub-device, and the first resistance reduction sub-device and the second resistance reduction sub-device are connected in parallel;
the first sub resistance reducing device and the grid layer of the array substrate are arranged in the same layer;
the second sub-resistance reducing device and the source drain layer of the array substrate are arranged on the same layer.
6. The display panel according to claim 1, further comprising an anode layer between the pixel defining layer and the array substrate;
the pixel defining layer further comprises a plurality of second openings, the second openings penetrate through the pixel defining layer, and the light emitting device layer and the cathode layer are filled in the second openings;
the anode layer comprises a first anode electrically connected to the cathode layer through the second opening;
the resistance reducing device further comprises a plurality of second resistance reducing devices, and the second resistance reducing devices are electrically connected with the cathode layer through the second openings.
7. The display panel of claim 6, wherein the anode layer further comprises a second anode disposed in a same layer as the first anode;
the second anode is electrically connected to the cathode layer through the first opening.
8. The display panel of claim 6, wherein the second resistance reducing device is located within the second opening.
9. The display panel according to claim 1, wherein the distribution density of the resistance reduction devices near the center of the display panel is greater than the distribution density of the resistance reduction devices far from the center of the display panel.
10. A display device comprising the display panel according to any one of claims 1 to 9, a polarizer layer, and a cover plate layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021976505.9U CN212725313U (en) | 2020-09-10 | 2020-09-10 | Display panel and display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021976505.9U CN212725313U (en) | 2020-09-10 | 2020-09-10 | Display panel and display device |
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| CN212725313U true CN212725313U (en) | 2021-03-16 |
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| CN202021976505.9U Active CN212725313U (en) | 2020-09-10 | 2020-09-10 | Display panel and display device |
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