CN212693954U - UIS test circuit - Google Patents

Abstract

The application provides a UIS test circuit, includes: the circuit comprises an inductor, a controllable constant voltage current clamping circuit, a driving circuit and a time sequence control circuit. And the first end of the inductor is used for being electrically connected with the first end of the controllable switching tube to be tested. And the first end of the controllable constant-voltage current clamping circuit is electrically connected with the second end of the inductor. And the first end of the driving circuit is used for being electrically connected with the control end of the controllable switching tube to be tested. And the second end of the driving circuit and the second end of the controllable constant-voltage current clamping circuit are connected with the second end of the controllable switching tube to be tested in a common mode. And the time sequence control circuit is respectively and electrically connected with the third end of the driving circuit and the third end of the controllable constant-voltage current clamping circuit. And the time sequence control circuit is used for controlling the conduction and the disconnection of the controllable switching tube to be tested through the driving circuit.

Description

UIS test circuit

Technical Field

The present application relates to the field of integrated circuit testing techniques, and more particularly, to UIS test circuits.

Background

In an integrated circuit test, for a power device such as a MOSFET or an IGBT, it is generally necessary to perform a UIS (Single-Pulse clamped Inductive Switching) parameter test. The circuit topology for UIS parametric testing comprises an inductor L, a current measuring circuit, a current comparison circuit, a Vgs driving circuit, a high-speed cut-off switch, a Vdd power supply and a timing control circuit besides a Device Under Test (DUT). In order to monitor the avalanche establishment process in the UIS parameter test, a voltage measuring circuit and a time measuring circuit are additionally arranged for respectively testing the breakdown voltage and the avalanche time of the device and judging whether the UIS test of the device is abnormal or not.

When the traditional circuit topology is adopted to carry out UIS parameter test, from the time when Id (current flowing through a tested device DUT) reaches a set current threshold value PeakI is detected to the time when the DUT is rapidly turned off, the Id is measured by a current measuring circuit, the Id is compared with the PeakI by a current comparison circuit, a time sequence control circuit carries out Vgs drive control, the DUT is rapidly turned off, and the hardware response processes of the current measuring circuit, the current comparison circuit and the PeakI have certain control delay, so that the actual turn-off current and the PeakI have certain difference, and the condition of false trigger protection and the like exists.

SUMMERY OF THE UTILITY MODEL

Therefore, when the UIS parameter test is needed to be carried out on the traditional circuit topology, a certain control delay exists, the actual turn-off current and the set current threshold value have a certain difference, and the problem of false trigger protection exists.

A UIS test circuit comprising:

the first end of the inductor is used for being electrically connected with the first end of the controllable switching tube to be tested;

the first end of the controllable constant-voltage current clamping circuit is electrically connected with the second end of the inductor;

a first end of the driving circuit is used for being electrically connected with a control end of the controllable switching tube to be tested, and a second end of the driving circuit and a second end of the controllable constant-voltage current clamping circuit are both used for being commonly connected with a second end of the controllable switching tube to be tested; and

and the time sequence control circuit is respectively electrically connected with the third end of the driving circuit and the third end of the controllable constant-voltage current clamping circuit and is used for controlling the conduction and the disconnection of the controllable switching tube to be tested through the driving circuit.

In one embodiment, the controllable constant voltage current clamping circuit comprises:

the first end of the power amplifier circuit is electrically connected with the second end of the controllable switch tube to be tested;

the first end of the current measuring circuit is electrically connected with the second end of the power amplifier circuit and is used for measuring the output current of the power amplifier circuit to obtain a first current;

the first end of the clamping circuit is electrically connected with the second end of the current measuring circuit, and the second end of the clamping circuit is electrically connected with the sequential control circuit;

the first end of the voltage measuring circuit and the third end of the current measuring circuit are connected with the second end of the inductor in a shared mode, the second end of the voltage measuring circuit is electrically connected with the first end of the power amplifier circuit, the third end of the voltage measuring circuit is electrically connected with the sequential control circuit, the fourth end of the voltage measuring circuit is electrically connected with the third end of the clamping circuit and used for measuring the output voltage of the power amplifier circuit to obtain a first voltage, and the first voltage is compared with a set voltage to obtain a comparison result; and

and the first end of the integrating circuit is electrically connected with the fourth end of the clamping circuit, the second end of the integrating circuit is electrically connected with the third end of the power amplifying circuit, and the third end of the integrating circuit is electrically connected with the fifth end of the voltage measuring circuit.

In one embodiment, the clamp circuit includes: the circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a first operational amplifier, a first diode and a second diode;

the first end of the first resistor is electrically connected with the time sequence control circuit, the second end of the first resistor, the first end of the second resistor, the first end of the third resistor, the first end of the fourth resistor, the anode of the first diode and the first end of the first operational amplifier are connected in common, the second end of the second resistor is electrically connected with the second end of the current measuring circuit, the second end of the third resistor is electrically connected with the fourth end of the current measuring circuit, the second end of the first operational amplifier is grounded, the output end of the first operational amplifier, the cathode of the first diode and the anode of the second diode are connected in common, and the cathode of the second diode and the second end of the fourth resistor are electrically connected with the first end of the integrating circuit.

In one embodiment, the integration circuit includes: a fifth resistor, a sixth resistor, a second operational amplifier and a capacitor;

the first end of the fifth resistor is electrically connected with the fourth end of the clamping circuit, the first end of the sixth resistor is electrically connected with the fifth end of the voltage measuring circuit, the second end of the fifth resistor, the second end of the sixth resistor, the first end of the second operational amplifier and the first end of the capacitor are connected in common, the second end of the second operational amplifier is grounded, and the output end of the second operational amplifier and the second end of the capacitor are electrically connected with the third end of the power amplifying circuit.

In one embodiment, the current measuring circuit comprises: the current measuring resistor, the third operational amplifier, the fourth operational amplifier, the first differential operational amplifier, the seventh resistor, the eighth resistor, the ninth resistor and the tenth resistor;

the first end of the current measuring resistor is connected with the second end of the power amplification circuit and the first end of the fourth operational amplifier in common, the second end of the current measuring resistor, the second end of the inductor and the first end of the third operational amplifier are connected in common, the second end of the third operational amplifier, the output end of the third operational amplifier and the first end of the seventh resistor are connected in common, a second end of the seventh resistor is electrically connected to a first end of the first differential operational amplifier and a first end of the eighth resistor, the second end of the eighth resistor and the output end of the first differential operational amplifier are connected with the first end of the clamping circuit in common, the second end of the fourth operational amplifier and the output end of the fourth operational amplifier are both electrically connected with the first end of the ninth resistor, the second end of the first differential operational amplifier and the second end of the ninth resistor are both grounded through the tenth resistor.

In one embodiment, the voltage measuring circuit includes: a fifth operational amplifier, a sixth operational amplifier, a second differential operational amplifier, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor and an operational amplifier;

a first end of the fifth operational amplifier is electrically connected to a second end of the inductor, a second end of the fifth operational amplifier and an output end of the fifth operational amplifier are commonly connected to a first end of the eleventh resistor, a second end of the eleventh resistor is electrically connected to a first end of the second differential operational amplifier and a first end of the twelfth resistor, a second end of the twelfth resistor and an output end of the second differential operational amplifier are commonly connected to a first end of the fifteenth resistor, a first end of the sixth operational amplifier is electrically connected to a second end of the power amplifier circuit, a second end of the sixth operational amplifier and an output end of the sixth operational amplifier are both electrically connected to a first end of the thirteenth resistor, and a second end of the second differential operational amplifier and a second end of the thirteenth resistor are both grounded through the fourteenth resistor, the sequential control circuit is connected with the second end of the fifteenth resistor, the first end of the seventeenth resistor and the first end of the operational amplifier through the sixteenth resistor, the second end of the seventeenth resistor is connected with the output end of the operational amplifier and the third end of the clamping circuit, and the second end of the operational amplifier is grounded.

In one embodiment, the driving circuit includes: the optical coupler device comprises an optical coupler device, a first controllable switch tube and a second controllable switch tube;

the first end of opto-coupler device with the sequential control circuit electricity is connected, the second end of opto-coupler device with the first end of first controllable switch pipe, the control end of first controllable switch pipe and the control end of second controllable switch pipe connect altogether, the second end of first controllable switch pipe with the first end of second controllable switch pipe all be used for with the control end of the controllable switch pipe that awaits measuring connects altogether, the third end of opto-coupler device with the second end electricity of second controllable switch pipe is connected.

In one embodiment, the UIS test circuit further comprises:

and the first end of the voltage measuring circuit is used for being electrically connected with the first end of the controllable switching tube to be measured, the second end of the voltage measuring circuit is used for being electrically connected with the second end of the controllable switching tube to be measured, and the output end of the voltage measuring circuit is electrically connected with the sequential control circuit and is used for measuring avalanche voltage between the first end and the second end of the controllable switching tube to be measured.

In one embodiment, the voltage measurement circuit includes: a seventh operational amplifier, an eighth operational amplifier, a third differential operational amplifier, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, and a twenty-first resistor;

the first end of the seventh operational amplifier is used for being electrically connected with the first end of the controllable switch tube to be tested, the second end of the seventh operational amplifier, the output end of the seventh operational amplifier and the first end of the eighteenth resistor are connected in common, a second end of the eighteenth resistor is electrically connected to a first end of the third differential operational amplifier and a first end of the nineteenth resistor, the second end of the nineteenth resistor and the output end of the third differential operational amplifier are connected with the time sequence control circuit in common, the first end of the eighth operational amplifier is used for being electrically connected with the second end of the controllable switch tube to be tested, the second end of the eighth operational amplifier and the output end of the eighth operational amplifier are both electrically connected with the first end of the twentieth resistor, a second terminal of the third differential operational amplifier and a second terminal of the twentieth resistor are both grounded through the twenty-first resistor.

In one embodiment, the UIS test circuit further comprises:

and the first end of the time measuring circuit is electrically connected with the first end of the controllable switching tube to be measured, and the second end of the time measuring circuit is electrically connected with the sequential control circuit and is used for measuring the avalanche time of the controllable switching tube to be measured.

Compared with the prior art, in the UIS test circuit, the timing control circuit controls the conduction and the disconnection of the controllable switch tube to be tested through the driving circuit, and is matched with the inductor and the controllable constant-voltage current clamping circuit, when the controllable switch tube to be tested is conducted, the controllable constant-voltage current clamping circuit determines whether constant-voltage current clamping is output or not based on a set constant-voltage clamping value, so that the phenomenon that the current flowing through the controllable switch tube to be tested is continuously increased to generate false triggering protection can be avoided, and the delay response speed of the turn-off control of the controllable switch tube to be tested is further reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic block circuit diagram of a UIS test circuit provided in an embodiment of the present application;

fig. 2 is a circuit diagram of a driving circuit according to an embodiment of the present disclosure;

FIG. 3 is a logic diagram of a UIS test circuit provided in an embodiment of the present application;

FIG. 4 is a logic diagram of a UIS test circuit according to another embodiment of the present application;

fig. 5 is a schematic block diagram of a controllable constant-voltage current clamping circuit according to an embodiment of the present disclosure;

FIG. 6 is a schematic circuit diagram of a current measuring circuit according to an embodiment of the present application;

fig. 7 is a circuit diagram of a clamp circuit according to an embodiment of the present disclosure;

FIG. 8 is a circuit diagram of a clamp circuit according to another embodiment of the present disclosure;

fig. 9 is a schematic circuit diagram of a voltage measuring circuit according to an embodiment of the present disclosure;

fig. 10 is a circuit diagram of an integration circuit according to an embodiment of the present application;

FIG. 11 is a block circuit diagram of a UIS test circuit provided in another embodiment of the present application;

FIG. 12 is a circuit diagram of a voltage measurement circuit according to an embodiment of the present application;

FIG. 13 is a circuit diagram of a time measurement circuit according to an embodiment of the present application;

fig. 14 is a timing diagram of a test of a time measurement circuit according to an embodiment of the present application.

Description of reference numerals:

10 UIS test circuit

100 inductance

110 controllable switch tube to be tested

200 controllable constant voltage current clamping circuit

210 power amplifier circuit

220 current measuring circuit

221 current sensing resistor 222, third operational amplifier 223, fourth operational amplifier

224 first differential operational amplifier 225 seventh resistor 226 eighth resistor

227 ninth resistor 228 tenth resistor

230 clamp circuit

231 first resistance 232 second resistance 233 third resistance

234 fourth resistor 235 first operational amplifier 236 first diode

237 second diode

240 voltage measuring circuit

241 fifth operational amplifier 242 sixth operational amplifier

243 second differential operational amplifier 244 eleventh resistor 245 twelfth resistor

246 thirteenth resistor 247 the fourteenth resistor 248 the fifteenth resistor

249 sixteenth resistor 2410 seventeenth resistor 2411 operational amplifier

250 integral circuit

251 fifth resistor 252 and sixth resistor 253 second operational amplifier

254 capacitance

300 driving circuit

311 optical coupler 312, a first controllable switch tube 313 and a second controllable switch tube

400 sequential control circuit

500 voltage measuring circuit

511 seventh operational amplifier 512 eighth operational amplifier 513 third differential operational amplifier

514 eighteenth resistor 515 nineteenth resistor 516 twentieth resistor

517 twenty-first resistor

600 time measuring circuit

Detailed Description

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. This application is capable of embodiments in many different forms than those described herein and those skilled in the art will be able to make similar modifications without departing from the spirit of the application and it is therefore not intended to be limited to the embodiments disclosed below.

It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Referring to fig. 1, an embodiment of the present application provides a UIS test circuit 10, including: inductor 100, controllable constant voltage current clamping circuit 200, driving circuit 300 and timing control circuit 400. The first end of the inductor 100 is used to electrically connect to the first end of the controllable switch tube 110 to be tested. A first terminal of the controllable constant voltage current clamping circuit 200 is electrically connected to a second terminal of the inductor 100. The first end of the driving circuit 300 is used for electrically connecting with the control end of the controllable switch tube 110 to be tested. The second end of the driving circuit 300 and the second end of the controllable constant voltage current clamping circuit 200 are both used for being connected to the second end of the controllable switch tube 110 to be tested.

The timing control circuit 400 is electrically connected to the third terminal of the driving circuit 300 and the third terminal of the controllable constant voltage current clamping circuit 200, respectively. The timing control circuit 400 is used for controlling the on/off of the controllable switch tube 110 to be tested through the driving circuit 300. When the controllable switch tube 110 to be tested is turned on, the controllable constant voltage current clamping circuit 200 determines whether to output constant voltage current clamping based on a set constant voltage clamping value.

In one embodiment, the controllable switch tube 110 to be tested may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The controllable switch tube 110 to be measured may also be an IGBT (Insulated Gate Bipolar Transistor). The controllable switch tube 110 to be tested may also be a triode or the like.

It is understood that the specific circuit topology of the controllable constant-voltage current clamping circuit 200 is not limited, and only has the function of determining whether to output the constant-voltage current clamping based on the set constant-voltage clamping value. In one embodiment, the controllable constant voltage current clamping circuit 200 may be composed of a current sensor, a power amplifier, a clamping device, a voltage sensor, a comparing device, an integrating and summing circuit, and the like. In one embodiment, the controllable constant-voltage current-clamping circuit 200 may also be a controllable integrated chip having the functions of constant-voltage output and constant-voltage current-clamping output.

It can be understood that the specific circuit topology of the driving circuit 300 is not limited as long as the driving circuit has the function of driving the controllable switching tube 110 to be tested to be turned on and off. In one embodiment, the driving circuit 300 may be a switching tube driver. In one embodiment, the driving circuit 300 may also employ a circuit topology as shown in fig. 2. Specifically, the driving circuit 300 may include a light coupling device 311, a first controllable switch tube 312, and a second controllable switch tube 313. Specifically, a first end of the optical coupler 311 is electrically connected to the timing control circuit 400. The second end of the optical coupler 311 is connected to the first end of the first controllable switch tube 312, the control end of the first controllable switch tube 312, and the control end of the second controllable switch tube 313. The second end of the first controllable switch tube 312 and the first end of the second controllable switch tube 313 are both used for being connected to the control end of the controllable switch tube 110 to be tested. A third end of the optocoupler 311 is electrically connected with a second end of the second controllable switch tube 313.

The first controllable switch tube 312 may be a triode; similarly, the second controllable switch tube 313 may also be a triode. The timing control circuit 400 may output a control signal (Vgs _ trig) to control the on/off of the optocoupler 311, so as to drive the first controllable switch tube 312 or the second controllable switch tube 313 to be in an on state, and finally, control the on/off of the controllable switch tube 110 device to be tested.

It is understood that the specific circuit topology of the timing control circuit 400 is not limited as long as the driving circuit 300 has a function of controlling the on/off of the controllable switch tube 110 to be tested. In one embodiment, the timing control circuit 400 may be an fpga (field Programmable Gate array) chip. The timing control circuit 400 may also be a single chip.

In one embodiment, the controllable constant voltage current clamping circuit 200 determines whether the constant voltage current clamping output is based on the set constant voltage current clamping value by: the controllable constant voltage current clamping circuit 200 may compare the set constant voltage clamping value with an output current of the controllable constant voltage current clamping circuit 200. If the output current of the controllable constant-voltage current clamping circuit 200 exceeds the range of the set constant-voltage clamping value, the controllable constant-voltage current clamping circuit 200 clamps the current and outputs the current. If the output voltage of the controllable constant-voltage current-clamping circuit 200 does not exceed the range of the set constant-voltage current-clamping value, the controllable constant-voltage current-clamping circuit 200 outputs a constant voltage at the moment.

Specifically, as shown in fig. 3, when the timing control circuit 400 controls the controllable switch tube 110 to be tested (i.e. DUT) to be turned on through the driving circuit 300, that is, the driving circuit 300 outputs a Vgs driving signal to drive the DUT to be turned on, a closed loop is formed among the inductor 100, the controllable constant voltage clamping circuit 200, and the controllable switch tube 110 to be tested, that is, a charging loop of the inductor 100 is formed. The current Id flowing through the DUT at this time rises from zero, i.e., the output current of the controllable constant voltage clamp circuit 200 rises from zero. When the output current of the controllable constant-voltage current-clamping circuit 200 reaches the set constant-voltage clamping value (i.e., PeakI), the controllable constant-voltage current-clamping circuit 200 clamps the current output. That is, at point B4, the output current of the controllable constant-voltage current-clamping circuit 200 is clamp-controlled at the set constant-voltage clamp value. After a C4 point GateV arrives, the timing control circuit controls Vgs output by the driving circuit 300 to drive the DUT to be rapidly turned off; that is, the timing control circuit 400 controls the DUT to be turned off through the driving circuit 300 within a preset delay time, and the charging loop of the inductor 100 is turned off. The preset delay time is the time from B4 to C4.

After the DUT is turned off, an avalanche process builds and the inductor 100 discharges to form a breakdown voltage Vds that breaks down the DUT. At this point Id drops to zero by time T42 and the avalanche ends. At the same time, the breakdown voltage Vds drops back to the Vdd voltage (i.e., Vds is equal to Vdd). At point E4, the controllable constant voltage current clamping circuit 200 recovers and the Vds voltage gradually recovers to zero. In the process from the point B4 to the point C4 in fig. 3, Id does not rise continuously due to the current clamping control of the controllable constant voltage current clamping circuit 200, so as to avoid the phenomenon of false trigger protection, and further reduce the delay response speed of the DUT turn-off control.

As shown in fig. 4, after the avalanche process DUT is broken down to cause short circuit, at point D5, Id rises again, and reaches the set constant voltage clamp value PeakI again, the output current of the controllable constant voltage clamp current circuit 200 is still clamped at the set constant voltage clamp value. After the constant voltage current clamping is recovered to the point E5, the energy of the inductor 100 is released through the controllable constant voltage current clamping circuit 200, so that Id is quickly returned to the zero point. Thus, the reliability of UIS testing can be improved by adopting the logic.

In this embodiment, the timing control circuit 400 controls the conduction and the disconnection of the controllable switching tube 110 to be tested through the driving circuit 300, and cooperates with the inductor 100 and the controllable constant voltage current clamping circuit 200, when the controllable switching tube 110 to be tested is conducted, the controllable constant voltage current clamping circuit 200 determines whether to output constant voltage current clamping based on a set constant voltage clamping value, so as to avoid the phenomenon that the current flowing through the controllable switching tube 110 to be tested continues to rise, which causes false triggering protection, and further reduce the delay response speed of the turn-off control of the controllable switching tube 110 to be tested.

Referring to fig. 5, in one embodiment, the controllable constant voltage current clamping circuit 200 includes: the power amplifier circuit 210, the current measuring circuit 220, the clamping circuit 230, the voltage measuring circuit 240 and the integrating circuit 250. The first end of the power amplifier circuit 210 is electrically connected to the second end of the controllable switch tube 110 to be tested. The first end of the current measuring circuit 220 is electrically connected to the second end of the power amplifier circuit 210. The current measuring circuit 220 is configured to measure an output current of the power amplifier circuit 210 and obtain a first current. A first terminal of the clamping circuit 230 is electrically connected to a second terminal of the current sensing circuit 220. A second terminal of the clamping circuit 230 is electrically connected to the timing control circuit 400. The first terminal of the voltage measuring circuit 240 and the third terminal of the current measuring circuit 220 are connected to the second terminal of the inductor 100. The second end of the voltage measuring circuit 240 is electrically connected to the first end of the power amplifier circuit 210. The third terminal of the voltage measuring circuit 240 is electrically connected to the timing control circuit 400. The fourth terminal of the voltage measuring circuit 240 is electrically connected to the third terminal of the clamping circuit 230.

The voltage measuring circuit 240 is configured to measure an output voltage of the power amplifier circuit 210 to obtain a first voltage, and compare the first voltage with a set voltage to obtain a comparison result. A first terminal of the integrating circuit 250 is electrically connected to a fourth terminal of the clamping circuit 230. The second terminal of the integrating circuit 250 is electrically connected to the third terminal of the power amplifier circuit 210. The third terminal of the integrating circuit 250 is electrically connected to the fifth terminal of the voltage measuring circuit 240. The clamping circuit 230 is configured to determine whether to output a clamping instruction according to the first current, the set constant voltage clamping value, and the comparison result, and if the clamping circuit outputs the clamping instruction, the integrating circuit 250 is configured to control the power amplifier circuit 210 to perform constant voltage current clamping output based on the clamping instruction and the comparison result.

In an embodiment, the specific circuit topology of the power amplifier circuit 210 is not limited, and may be a power amplifier. It is understood that the specific circuit topology of the current measuring circuit 220 is not limited as long as the function of measuring the output current of the power amplifier circuit 210 and obtaining the first current is provided. In an embodiment, a circuit topology of the current measuring circuit 220 is shown in fig. 6, and specifically includes: a current sensing resistor 221, a third operational amplifier 222, a fourth operational amplifier 223, a first differential operational amplifier 224, a seventh resistor 225, an eighth resistor 226, a ninth resistor 227, and a tenth resistor 228.

The first end of the current measuring resistor 221 is connected to the second end of the power amplifier circuit 210 and the first end of the fourth operational amplifier 223. The second terminal of the current-measuring resistor 221 is connected to the second terminal of the inductor 100 and the first terminal of the third operational amplifier 222. The second terminal of the third operational amplifier 222, the output terminal of the third operational amplifier 222 and the first terminal of the seventh resistor 225 are commonly connected. A second end of the seventh resistor 225 is electrically connected to a first end of the first differential operational amplifier 224 and a first end of the eighth resistor 226. The second terminal of the eighth resistor 226 and the output terminal of the first differential operational amplifier 224 are commonly connected to the first terminal of the clamping circuit 230. The second end of the fourth operational amplifier 223 and the output end of the fourth operational amplifier 223 are both electrically connected to the first end of the ninth resistor 227. The second terminal of the first differential operational amplifier 224 and the second terminal of the ninth resistor 227 are both connected to ground through the tenth resistor 228.

The output current of the power amplifier circuit 210 flows in from FL and flows out from FH, so that a voltage drop is generated across the current-measuring resistor 221. Then, the voltage is followed by the third operational amplifier 222 and the fourth operational amplifier 223, and then the current signal Imeas (i.e. the first current) is obtained after the operation is performed by the first differential operational amplifier 224. And outputs the current signal Imeas to the clamping circuit 230, so that the clamping circuit 230 determines whether to control the power amplifier circuit 210 to clamp the current.

In an embodiment, the current measuring circuit 220 may also be disposed between the power amplifier circuit 210 and the controllable switch tube 110 to be tested, as long as the current measuring circuit 220 is ensured to be capable of measuring the output current of the power amplifier circuit 210 and obtaining the first current.

It is to be understood that the specific circuit topology of the clamping circuit 230 is not limited as long as it has a function of determining whether to output a clamping instruction according to the first current, the set constant voltage clamp value, and the comparison result. In one embodiment, the clamping circuit 230 may be composed of a plurality of resistors, diodes, and operational amplification circuits. In an embodiment, the clamping circuit 230 may also adopt the circuit topology shown in fig. 7, which specifically includes: a first resistor 231, a second resistor 232, a third resistor 233, a fourth resistor 234, a first operational amplifier 235, a first diode 236, and a second diode 237.

Specifically, a first end of the first resistor 231 is electrically connected to the timing control circuit 400. The second terminal of the first resistor 231, the first terminal of the second resistor 232, the first terminal of the third resistor 233, the first terminal of the fourth resistor 234, the anode of the first diode 236 and the first terminal of the first operational amplifier 235 are connected in common. A second terminal of the second resistor 232 is electrically connected to a second terminal of the current measuring circuit 220. A second end of the third resistor 233 is electrically connected to a fourth end of the voltage measuring circuit 240, and a second end of the first operational amplifier 235 is grounded. The output terminal of the first operational amplifier 235, the cathode of the first diode 236, and the anode of the second diode 237 are connected in common. A cathode of the second diode 237 and a second terminal of the fourth resistor 234 are electrically connected to a first terminal of the integration circuit 250.

The first operational amplifier 235 may sum up the voltage value (Vs +) corresponding to the set constant voltage clamp value output by the timing control circuit 400, the voltage value (Vo) corresponding to the current signal Imeas, and the comparison result Vctrl to obtain a second voltage. Determining whether a clamping condition is satisfied based on the second voltage. Specifically, the second voltage may be compared with a preset reference voltage, if the second voltage exceeds a range of the preset reference voltage, it indicates that the output current of the power amplifier circuit 210 exceeds a range of the set constant voltage clamp value, and at this time, the clamping condition is satisfied, and the second diode 237 is turned on in the forward direction and outputs a clamping command Iclamp + to the integrating circuit 250. So that the integration circuit 250 can control the constant voltage clamp output of the power amplifier circuit 210 based on the clamp instruction Iclamp + and the comparison result.

If the second voltage does not exceed the range of the preset reference voltage, it indicates that the output current of the power amplifier circuit 210 does not exceed the range of the set constant voltage clamp value, and the clamping condition is not satisfied at this time, then the second diode 237 is turned off in the reverse direction. At this time, the clamping command Iclamp + is not output to the integrating circuit 250, and the integrating circuit 250 may control the power amplifier circuit 210 to output a constant voltage based on the comparison result.

In one embodiment, the clamping circuit 230 employing the circuit topology described above may clamp a forward voltage. If a negative voltage is to be clamped, the anodes and cathodes of the first diode 236 and the second diode 237 in the circuit topology described above may be interchanged (as shown in fig. 8 in particular).

It can be understood that the specific circuit topology of the voltage measuring circuit 240 is not limited as long as the function of measuring the output voltage of the power amplifier circuit 210 to obtain the first voltage and comparing the first voltage with the set voltage to obtain the comparison result is provided. In one embodiment, the voltage measuring circuit 240 may be composed of a voltage sensor and a comparator. In an embodiment, a circuit topology of the voltage measuring circuit 240 may also be as shown in fig. 9, and specifically includes: a fifth operational amplifier 241, a sixth operational amplifier 242, a second differential operational amplifier 243, an eleventh resistor 244, a twelfth resistor 245, a thirteenth resistor 246, a fourteenth resistor 247, a fifteenth resistor 248, a sixteenth resistor 249, a seventeenth resistor 2410, and an operational amplifier 2411.

Wherein a first terminal of the fifth operational amplifier 241 is electrically connected to a second terminal of the inductor 100. The second terminal of the fifth operational amplifier 241, the output terminal of the fifth operational amplifier 241 and the first terminal of the eleventh resistor 244 are commonly connected. A second end of the eleventh resistor 244 is electrically connected to a first end of the second differential operational amplifier 243 and a first end of the twelfth resistor 245. The second terminal of the twelfth resistor 245 and the output terminal of the second differential operational amplifier 243 are commonly connected to the first terminal of the fifteenth resistor 248. A first end of the sixth operational amplifier 242 is electrically connected to a second end of the power amplifier circuit 210. The second end of the sixth operational amplifier 242 and the output end of the sixth operational amplifier 242 are both electrically connected to the first end of the thirteenth resistor 246. A second terminal of the second differential operational amplifier 243 and a second terminal of the thirteenth resistor 246 are both connected to ground through the fourteenth resistor 247. The timing control circuit 400 is connected to the second terminal of the fifteenth resistor 248, the first terminal of the seventeenth resistor 2410 and the first terminal of the operational amplifier 2411 through the sixteenth resistor 249. A second terminal of the seventeenth resistor 2410, an output terminal of the operational amplifier 2411 and a third terminal of the clamp circuit 230 are commonly connected. The second terminal of the operational amplifier 2411 is grounded.

The voltage of the second terminal of the inductor 100 is followed by the voltage signal SH through the fifth operational amplifier 241 and the following voltage signal is outputted to the second differential operational amplifier 243. The voltage signal SL at the first end of the power amplifier circuit 210 is followed by the sixth operational amplifier 242, and the subsequent voltage signal is output to the second differential operational amplifier 243. The second differential operational amplifier 243 performs a differential operation on the two subsequent voltage signals to obtain Vmeas (i.e., the first voltage). In one embodiment, the operational amplifier 2411 may compare Vmeas with a set voltage and obtain a comparison result Vctrl. In one embodiment, the operational amplifier 2411 may also sum Vmeas with a preset voltage Vse, compare the sum with a set voltage to obtain a comparison result Vctrl, and output Vctrl to the clamping circuit 230 and the integrating circuit 250, respectively, for subsequent calculation. In one embodiment, the comparison result Vctrl is a voltage signal.

In one embodiment, the comparing the first voltage with the set voltage by the voltage measuring circuit 240 means: the voltage measuring circuit 240 may compare the first voltage with the set voltage, and if the first voltage is not equal to the set voltage, the integrating circuit 250 may adjust the output voltage of the power amplifier circuit 210 based on the comparison result to achieve constant voltage output. If the first voltage is equal to the set voltage, the integrator circuit 250 does not adjust the output voltage of the power amplifier circuit 210.

It is understood that the specific circuit topology of the integration circuit 250 is not limited as long as it has a function of controlling the constant-voltage clamp current output of the power amplifier circuit based on the clamp instruction and the comparison result. In one embodiment, the integration circuit 250 may be composed of an operational amplifier and a capacitor. In an embodiment, a circuit topology of the integrating circuit 250 can also be as shown in fig. 10, and specifically includes: a fifth resistor 251, a sixth resistor 252, a second operational amplifier 253, and a capacitor 254. A first terminal of the fifth resistor 251 is electrically connected to a fourth terminal of the clamping circuit 230. A first end of the sixth resistor 252 is electrically connected to a fifth end of the voltage measuring circuit 240. The second terminal of the fifth resistor 251, the second terminal of the sixth resistor 252, the first terminal of the second operational amplifier 253, and the first terminal of the capacitor 254 are commonly connected. A second terminal of the second operational amplifier 253 is grounded. The output end of the second operational amplifier 253 and the second end of the capacitor 254 are electrically connected to the third end of the power amplifier circuit 210.

The second operational amplifier 253 cooperates with the fifth resistor 251 and the sixth resistor 252 to sum the clamping instruction output by the clamping circuit 230 and the comparison result, and cooperates with the capacitor 254 to perform an integration operation, thereby controlling the constant voltage clamp output of the power amplifier circuit 210 based on the operation result. When the clamping circuit 230 is capable of clamping both positive and negative voltages, the integrating circuit 250 may further include a seventh resistor R42. That is, the negative clamping command Iclamp-output from the clamping circuit 230 is input to the second operational amplifier 253 via the seventh resistor R42.

Referring to FIG. 11, in one embodiment, the UIS test circuit 10 further comprises: a voltage measurement circuit 500. The first end of the voltage measurement circuit 500 is electrically connected to the first end of the controllable switch tube 110 to be tested. The second end of the voltage measuring circuit 500 is electrically connected to the second end of the controllable switch tube 110 to be tested. The output terminal of the voltage measuring circuit 500 is electrically connected to the timing control circuit 400. The voltage measurement circuit 500 is used for measuring an avalanche voltage between the first end and the second end of the controllable switch tube 110 to be measured.

It is understood that the specific circuit structure of the voltage measuring circuit 500 is not limited, and only has the function of measuring the avalanche voltage between the first terminal and the second terminal of the controllable switch tube 110 to be tested. In one embodiment, the voltage measurement circuit 500 may be a conventional circuit with voltage measurement function, such as an RC circuit. In an embodiment, a circuit topology of the voltage measurement circuit 500 may also be as shown in fig. 12, and specifically includes: a seventh operational amplifier 511, an eighth operational amplifier 512, a third differential operational amplifier 513, an eighteenth resistor 514, a nineteenth resistor 515, a twentieth resistor 516, and a twenty-first resistor 517.

The first end of the seventh operational amplifier 511 is used for electrically connecting with the first end of the controllable switch tube 110 to be tested. The second end of the seventh operational amplifier 511, the output end of the seventh operational amplifier 511 and the first end of the eighteenth resistor 514 are commonly connected. A second end of the eighteenth resistor 514 is electrically connected to a first end of the third differential operational amplifier 513 and a first end of the nineteenth resistor 515. A second terminal of the nineteenth resistor 515 and an output terminal of the third differential operational amplifier 513 are connected to the timing control circuit 400 in common. The first end of the eighth operational amplifier 512 is used to be electrically connected to the second end of the controllable switch tube 110 to be tested, and the second end of the eighth operational amplifier 512 and the output end of the eighth operational amplifier 512 are both electrically connected to the first end of the twentieth resistor 516. A second terminal of the third differential operational amplifier 513 and a second terminal of the twentieth resistor 516 are both grounded through the twenty-first resistor 517.

The seventh operational amplifier 511 and the eighth operational amplifier 512 perform differential operation with the third differential operational amplifier 513 following the measured Vdrain (i.e. the first end voltage of the controllable switch tube 110 to be tested) and Vsource (i.e. the second end voltage of the controllable switch tube 110 to be tested), and output Vds signals to the timing control circuit 400.

In one embodiment, the UIS test circuit 10 further comprises: time measurement circuit 600. A first end of the time measuring circuit 600 is electrically connected to a first end of the controllable switch tube 110 to be tested. The second end of the time measurement circuit 600 is electrically connected to the second end of the controllable switch tube 110 to be tested and the timing control circuit 400. The time measuring circuit 600 is used for measuring the avalanche time of the controllable switch tube 110 under test.

In an embodiment, a specific circuit topology of the time measurement circuit 600 is shown in fig. 13, and specifically includes: two comparators OP61 and OP 62. The tested signal Vdrain is compared with the V _ trig + and V _ trig-by the comparators OP61 and OP62, and the obtained level signal is sent to the timing control circuit 400 for timing, so that the pulse width (i.e. avalanche time) of Vds can be measured.

In one embodiment, if the controllable switch tube 110 to be tested is an NMOS, the timing control circuit 400 is cooperated with the time measurement circuit 600 to obtain the test timing chart shown in fig. 14. And setting the V _ trig + value to be greater than Vd and less than Vds, so as to obtain the T _ trig + waveform.

In summary, in the present application, the timing control circuit 400 controls the conduction and the disconnection of the controllable switch tube 110 to be tested through the driving circuit 300, and cooperates with the inductor 100 and the controllable constant voltage current clamping circuit 200, when the controllable switch tube 110 to be tested is conducted, the controllable constant voltage current clamping circuit 200 determines whether to output the constant voltage current clamping based on the set constant voltage clamping value, so as to avoid the phenomenon that the current flowing through the controllable switch tube 110 to be tested continues to rise, which causes false triggering protection, and further reduce the delay response speed of the turn-off control of the controllable switch tube 110 to be tested.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the utility model. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A UIS test circuit, comprising:

the first end of the inductor (100) is used for being electrically connected with the first end of the controllable switching tube (110) to be tested;

the controllable constant-voltage current clamping circuit (200), wherein a first end of the controllable constant-voltage current clamping circuit (200) is electrically connected with a second end of the inductor (100);

a first end of the driving circuit (300) is used for being electrically connected with a control end of the controllable switching tube (110) to be tested, and a second end of the driving circuit (300) and a second end of the controllable constant-voltage current clamping circuit (200) are both used for being commonly connected with a second end of the controllable switching tube (110) to be tested; and

and the time sequence control circuit (400) is respectively and electrically connected with the third end of the driving circuit (300) and the third end of the controllable constant voltage current clamping circuit (200) and is used for controlling the conduction and the disconnection of the controllable switching tube (110) to be tested through the driving circuit (300).

2. A UIS test circuit according to claim 1, wherein said controllable constant voltage clamping current circuit (200) comprises:

the first end of the power amplifier circuit (210) is used for being electrically connected with the second end of the controllable switch tube (110) to be tested;

the current measuring circuit (220), a first end of the current measuring circuit (220) is electrically connected with a second end of the power amplifier circuit (210), and is used for measuring the output current of the power amplifier circuit (210) to obtain a first current;

a clamp circuit (230), a first end of the clamp circuit (230) being electrically connected to a second end of the current sensing circuit (220), a second end of the clamp circuit (230) being electrically connected to the timing control circuit (400);

the first end of the voltage measuring circuit (240) and the third end of the current measuring circuit (220) are connected with the second end of the inductor (100) in a common mode, the second end of the voltage measuring circuit (240) is electrically connected with the first end of the power amplifier circuit (210), the third end of the voltage measuring circuit (240) is electrically connected with the time sequence control circuit (400), the fourth end of the voltage measuring circuit (240) is electrically connected with the third end of the clamping circuit (230) and used for measuring the output voltage of the power amplifier circuit (210) to obtain a first voltage, and the first voltage is compared with a set voltage to obtain a comparison result; and

and a first end of the integrating circuit (250) is electrically connected with a fourth end of the clamping circuit (230), a second end of the integrating circuit (250) is electrically connected with a third end of the power amplifier circuit (210), and a third end of the integrating circuit (250) is electrically connected with a fifth end of the voltage measuring circuit (240).

3. The UIS test circuit of claim 2, wherein said clamping circuit (230) comprises: a first resistor (231), a second resistor (232), a third resistor (233), a fourth resistor (234), a first operational amplifier (235), a first diode (236), and a second diode (237);

a first end of the first resistor (231) is electrically connected to the timing control circuit (400), a second end of the first resistor (231), a first end of the second resistor (232), a first end of the third resistor (233), a first end of the fourth resistor (234), an anode of the first diode (236) and a first end of the first operational amplifier (235) are commonly connected, a second end of the second resistor (232) is electrically connected to a second end of the current measurement circuit (220), a second end of the third resistor (233) is electrically connected to a fourth end of the voltage measurement circuit (240), a second end of the first operational amplifier (235) is grounded, an output end of the first operational amplifier (235), a cathode of the first diode (236) and an anode of the second diode (237) are commonly connected, a cathode of the second diode (237) and a second end of the fourth resistor (234) are electrically connected to a first end of the integration circuit (250) And (6) connecting.

4. A UIS test circuit according to claim 2, wherein said integration circuit (250) comprises: a fifth resistor (251), a sixth resistor (252), a second operational amplifier (253), and a capacitor (254);

a first end of the fifth resistor (251) is electrically connected with a fourth end of the clamping circuit (230), a first end of the sixth resistor (252) is electrically connected with a fifth end of the voltage measuring circuit (240), a second end of the fifth resistor (251), a second end of the sixth resistor (252), a first end of the second operational amplifier (253) and a first end of the capacitor (254) are connected in common, a second end of the second operational amplifier (253) is grounded, and an output end of the second operational amplifier (253) and a second end of the capacitor (254) are electrically connected with a third end of the power amplifier circuit (210).

5. A UIS test circuit according to claim 2, wherein said current sensing circuit (220) comprises: a current measuring resistor (221), a third operational amplifier (222), a fourth operational amplifier (223), a first differential operational amplifier (224), a seventh resistor (225), an eighth resistor (226), a ninth resistor (227) and a tenth resistor (228);

a first end of the current measuring resistor (221) is commonly connected with a second end of the power amplifier circuit (210) and a first end of the fourth operational amplifier (223), a second end of the current measuring resistor (221) is commonly connected with a second end of the inductor (100) and a first end of the third operational amplifier (222), a second end of the third operational amplifier (222) and an output end of the third operational amplifier (222) are commonly connected with a first end of the seventh resistor (225), a second end of the seventh resistor (225) is electrically connected with a first end of the first differential operational amplifier (224) and a first end of the eighth resistor (226), a second end of the eighth resistor (226) and an output end of the first differential operational amplifier (224) are commonly connected with a first end of the clamping circuit (230), a second end of the fourth operational amplifier (223) and an output end of the fourth operational amplifier (223) are both commonly connected with a first end of the ninth resistor (227) And the second end of the first differential operational amplifier (224) and the second end of the ninth resistor (227) are both connected to the ground through the tenth resistor (228).

6. A UIS test circuit according to claim 2, wherein said voltage measurement circuit (240) comprises: a fifth operational amplifier (241), a sixth operational amplifier (242), a second differential operational amplifier (243), an eleventh resistor (244), a twelfth resistor (245), a thirteenth resistor (246), a fourteenth resistor (247), a fifteenth resistor (248), a sixteenth resistor (249), a seventeenth resistor (2410), and an operational amplifier (2411);

a first end of the fifth operational amplifier (241) is electrically connected to a second end of the inductor (100), a second end of the fifth operational amplifier (241), an output end of the fifth operational amplifier (241) and a first end of the eleventh resistor (244) are connected in common, a second end of the eleventh resistor (244) is electrically connected to a first end of the second differential operational amplifier (243) and a first end of the twelfth resistor (245), a second end of the twelfth resistor (245) and an output end of the second differential operational amplifier (243) are connected in common to a first end of the fifteenth resistor (248), a first end of the sixth operational amplifier (242) is electrically connected to a second end of the power amplifier circuit (210), a second end of the sixth operational amplifier (242) and an output end of the sixth operational amplifier (242) are both electrically connected to a first end of the thirteenth resistor (246), the second terminal of the second differential operational amplifier (243) and the second terminal of the thirteenth resistor (246) are both grounded through the fourteenth resistor (247), the timing control circuit (400) is connected to the second terminal of the fifteenth resistor (248), the first terminal of the seventeenth resistor (2410) and the first terminal of the operational amplifier (2411) through the sixteenth resistor (249), the second terminal of the seventeenth resistor (2410) is connected to the output terminal of the operational amplifier (2411) and the third terminal of the clamping circuit (230), and the second terminal of the operational amplifier (2411) is grounded.

7. A UIS test circuit according to claim 1, wherein said driver circuit (300) comprises: the circuit comprises an optocoupler device (311), a first controllable switch tube (312) and a second controllable switch tube (313);

the first end of opto-coupler device (311) with sequential control circuit (400) electricity is connected, the second end of opto-coupler device (311) with the first end of first controllable switch pipe (312), the control end of first controllable switch pipe (312) with the control end of second controllable switch pipe (313) connects altogether, the second end of first controllable switch pipe (312) with the first end of second controllable switch pipe (313) all be used for with the control end of the controllable switch pipe (110) that awaits measuring connects altogether, the third end of opto-coupler device (311) with the second end electricity of second controllable switch pipe (313) is connected.

8. The UIS test circuit of any of claims 1-7, further comprising:

a voltage measurement circuit (500), a first end of the voltage measurement circuit (500) is used for being electrically connected with a first end of the controllable switch tube (110) to be measured, a second end of the voltage measurement circuit (500) is used for being electrically connected with a second end of the controllable switch tube (110) to be measured, and an output end of the voltage measurement circuit (500) is electrically connected with the timing control circuit (400) and is used for measuring an avalanche voltage between the first end and the second end of the controllable switch tube (110) to be measured.

9. A UIS test circuit according to claim 8, wherein said voltage measurement circuit (500) comprises: a seventh operational amplifier (511), an eighth operational amplifier (512), a third differential operational amplifier (513), an eighteenth resistor (514), a nineteenth resistor (515), a twentieth resistor (516), and a twenty-first resistor (517);

the first end of the seventh operational amplifier (511) is used for being electrically connected with the first end of the controllable switch tube (110) to be tested, the second end of the seventh operational amplifier (511) and the output end of the seventh operational amplifier (511) are commonly connected with the first end of the eighteenth resistor (514), the second end of the eighteenth resistor (514) is electrically connected with the first end of the third differential operational amplifier (513) and the first end of the nineteenth resistor (515), the second end of the nineteenth resistor (515) and the output end of the third differential operational amplifier (513) are commonly connected with the timing control circuit (400), the first end of the eighth operational amplifier (512) is used for being electrically connected with the second end of the controllable switch tube (110) to be tested, the second end of the eighth operational amplifier (512) and the output end of the eighth operational amplifier (512) are both electrically connected with the first end of the twentieth resistor (516), a second terminal of the third differential operational amplifier (513) and a second terminal of the twentieth resistor (516) are both connected to ground through the twenty-first resistor (517).

10. The UIS test circuit of any of claims 1-7, further comprising:

a time measuring circuit (600), wherein a first end of the time measuring circuit (600) is electrically connected with a first end of the controllable switch tube (110) to be tested, and a second end of the time measuring circuit (600) is electrically connected with the timing control circuit (400) and is used for measuring the avalanche time of the controllable switch tube (110) to be tested.

Images