CN212675891U - Drive circuit, display device and electronic device - Google Patents

Abstract

The application relates to a driving circuit, a display device and an electronic device. The driving circuit comprises a plurality of array substrate row driving GOA circuit units, and the GOA circuit units are cascaded; each GOA circuit unit comprises a reset unit, the reset unit is electrically connected with a frame starting pulse STV signal line of the driving circuit, the reset unit is used for resetting at least one of a scanning signal output end and a pull-up signal control end of the GOA circuit unit by utilizing a time sequence signal provided by the STV signal line, effective resetting of the scanning signal output end and the pull-up signal control end of the GOA circuit can be realized by multiplexing the time sequence signal of the STV signal line of the GOA circuit, noise influencing a panel display area in a previous frame image is eliminated, and the working stability of the GOA circuit is improved.

Description

Drive circuit, display device and electronic device

Technical Field

The present application relates to the field of electronic technologies, and in particular, to a driving circuit, a display device, and an electronic device.

Background

Array substrate line Driver on Array (GOA) circuits are a mature technology, however, with the increasing challenge of harsh external conditions to display technologies and the increasing requirements of people on display technologies, GOA circuits as the core driving technology of display panels are also designed to be optimized continuously to cope with the harsh external conditions of high temperature, low temperature, high humidity, etc. to meet the increasing requirements of people on picture quality. The conventional GOA circuit has various processing modes for resetting the scan signal output terminal GN, and usually a single STV signal line is added to serve as a reset signal of the GN, and the waveform timing of the added single STV signal line is different from that of the conventional STV signal line for the GOA, which is not only disadvantageous for implementing the narrow-frame technology, but also increases the signal input source, and is disadvantageous for the working stability of the GOA circuit.

SUMMERY OF THE UTILITY MODEL

In view of the foregoing deficiencies of the prior art, the present application aims to provide a driving circuit, a display device and an electronic device, which aims to solve the technical problem of how to easily and effectively reset the scan signal output terminal g (n) of the GOA circuit to improve the operating stability of the GOA circuit.

A driving circuit comprises a plurality of array substrate row driving GOA circuit units, and the GOA circuit units are cascaded.

Each GOA circuit unit comprises a reset unit, and the reset unit is electrically connected with a frame starting pulse STV signal line of the driving circuit.

And the reset unit is used for resetting at least one of the scanning signal output end and the pull-up signal control end of the GOA circuit unit by using the time sequence signal provided by the STV signal line.

The GOA circuit can effectively reset the scanning signal output end GN and the pull-up signal control end Q point of the GOA circuit by multiplexing the time sequence signal of the STV signal line so as to eliminate the noise influencing the display area of the panel in the previous frame of image and improve the working stability of the GOA circuit.

Optionally, the plurality of GOA circuit units include a first-stage GOA circuit unit, and a reset unit of the first-stage GOA circuit unit is electrically connected to the frame start pulse STV signal line of the driving circuit, and is configured to reset the scan signal output end of the first-stage GOA circuit unit by using a timing signal provided by the STV signal line. Considering that the STV signal can act as a pre-charge for the first-stage GOA circuit, for the action mode that GN-1 is turned on and then GN +2 is turned off, only the scan signal output terminal GN of the first-stage GOA circuit needs to be reset, and the pull-up signal control terminal Q point does not need to be reset.

Optionally, the reset unit of the first-stage GOA circuit unit includes a first transistor, and the first transistor is electrically connected to the STV signal line and the scan signal output end of the first-stage GOA circuit unit; and the first transistor is used for resetting a scanning signal output end of the first-stage GOA circuit unit by using a timing signal provided by the STV signal line. It can be seen that the reset unit of the first-stage GOA circuit unit can multiplex the timing signal of the STV signal line by setting a transistor to realize effective reset of the scanning signal output terminal GN, so as to eliminate the noise affecting the panel display area in the previous frame of image.

Optionally, the first transistor comprises a thin film field effect transistor. The adoption of the thin film field effect transistor is beneficial to the miniaturization design of products.

Optionally, the timing signal provided by the STV signal line is further used to precharge a pull-up signal control terminal of the first stage GOA circuit unit.

Optionally, the plurality of GOA circuit units include an i-th GOA circuit unit, a reset unit of the i-th GOA circuit unit is electrically connected to the frame start pulse STV signal line of the driving circuit, and is configured to reset the scan signal output terminal and the pull-up signal control terminal of the i-th GOA circuit unit by using a timing signal provided by the STV signal line, where i is an integer greater than or equal to 2. Therefore, for the action mode that G (N-1) is turned on and G (N +2) is turned off later, effective resetting of the scanning signal output end GN and the pull-up signal control end Q point can be simultaneously realized by multiplexing the time sequence signal of the STV signal line of each GOA circuit unit cascaded behind the first-stage GOA circuit unit, so that noise influencing a panel display area in the previous frame image is eliminated, and the working stability of the GOA circuit is improved.

Optionally, the reset unit of the ith-stage GOA circuit unit includes a second transistor electrically connected to the STV signal line and the scan signal output terminal of the ith-stage GOA circuit unit, and a third transistor electrically connected to the STV signal line and the pull-up signal control terminal of the ith-stage GOA circuit unit; the second transistor is used for resetting a scanning signal output end of the ith-level GOA circuit unit by using a timing signal provided by the STV signal line; and the third transistor is used for resetting the pull-up signal control end of the ith-level GOA circuit unit by using a timing signal provided by the STV signal line. As can be seen, for each stage of GOA circuit unit cascaded after the first stage of GOA circuit unit, the reset unit is provided with two transistors to multiplex the timing signal of the STV signal line and simultaneously realize effective reset of the scanning signal output terminal GN and the pull-up signal control terminal Q point.

Optionally, the second transistor comprises a thin film field effect transistor and the third transistor comprises a thin film field effect transistor. The adoption of the thin film field effect transistor is beneficial to the miniaturization design of products.

Optionally, each GOA circuit unit further includes a discharge unit; the discharging signal control end of the discharging unit of the jth grade GOA circuit unit in the GOA circuit units is electrically connected with the scanning signal output end of the jth +2 grade GOA circuit unit in the GOA circuit units, and j is an integer greater than or equal to 1. It can be seen that, for the action mode that GN-1 is turned on and then GN +2 is turned off, the discharge signal control terminal of the jth GOA circuit unit is electrically connected to the scan signal output terminal GN of the jth +2 GOA circuit unit.

Based on the same application concept, the application also provides a display device, which comprises a controller, a display panel and the driving circuit, wherein the controller is electrically connected with the driving circuit, and the driving circuit is electrically connected with the display panel.

Based on the same application concept, the application also provides electronic equipment comprising the display equipment.

In the embodiment of the application, the driving circuit comprises a plurality of array substrate row driving GOA circuit units, and the GOA circuit units are cascaded; each GOA circuit unit comprises a reset unit, the reset unit is electrically connected with a frame starting pulse STV signal line of the driving circuit, the reset unit is used for resetting at least one of a scanning signal output end and a pull-up signal control end of the GOA circuit unit by using a time sequence signal provided by the STV signal line, effective resetting of a scanning signal output end GN and a pull-up signal control end Q point of the GOA circuit can be realized by multiplexing the time sequence signal of the STV signal line of the GOA circuit, so that noise influencing a panel display area in an image of a previous frame is eliminated, namely only one STV signal line is adopted, the potential output by the GN of the previous frame can be effectively released, the output potential of the Q point of the previous frame can be released, a new signal input source is avoided being introduced, and the working stability of the GOA circuit is improved.

Drawings

Fig. 1 is a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a GOA circuit unit according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of another GOA circuit unit according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of another GOA circuit unit according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of another GOA circuit unit according to an embodiment of the present disclosure;

fig. 6 is a timing diagram of signals of a GOA circuit according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of another GOA circuit unit according to an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of another GOA circuit unit according to an embodiment of the present disclosure;

fig. 9 is a timing diagram of signals of another GOA circuit according to the embodiment of the present disclosure;

fig. 10 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

Referring to fig. 1, a schematic diagram of a driving circuit according to an embodiment of the present disclosure is shown, where the driving circuit 10 includes: a plurality of GOA circuit units 20, the plurality of GOA circuit units 20 being cascaded with one another.

Each GOA circuit unit 20 includes a reset unit 210, and the reset unit 210 is electrically connected to an STV signal line of the driving circuit 10, and the STV signal line is used for providing an STV signal required by the driving circuit 10.

The reset unit 210 is configured to reset at least one of the scan signal output terminal and the pull-up signal control terminal of the GOA circuit unit by using the timing signal provided by the STV signal line.

Specifically, by providing the reset unit 210 for each GOA circuit unit 20, the scan signal output terminal GN can be reset before the next frame arrives, or the scan signal output terminal GN and the pull-up signal control terminal Q point can be reset at the same time, and the timing signal of the STV signal line of the GOA circuit can be multiplexed to effectively reset the scan signal output terminal GN and the pull-up signal control terminal Q point, so as to eliminate the noise affecting the panel display area in the previous frame image.

In some possible embodiments, as shown in fig. 2 or fig. 3, each GOA circuit unit 20 further includes a pull-up unit 220, a discharge unit 230, and a pull-down unit 240 in addition to the reset unit 210, and the reset unit 210, the pull-up unit 220, the discharge unit 230, and the pull-down unit 240 constitute basic units required for normal operation of each GOA circuit unit 20.

In some possible embodiments, the plurality of GOA circuit units include a first stage GOA circuit unit, and since the STV signal may play a role of precharging the first stage GOA circuit unit, the reset unit of the first stage GOA circuit unit only needs to reset the scan signal output terminal GN (specifically G1), and the pull-up signal control terminal Q point does not reset, that is, the reset unit of the first stage GOA circuit unit is electrically connected to the STV signal line of the frame start pulse of the driving circuit, and is configured to reset the scan signal output terminal GN by using the timing signal provided by the STV signal line. As shown in fig. 2, the reset unit 210 of the first stage GOA circuit unit 20 is electrically connected to a scan signal output terminal GN for resetting the GN, which is located between the pull-up unit 220 and the discharge unit 230.

In some possible embodiments, the reset unit of the first stage GOA circuit unit may specifically include a transistor (denoted as a first transistor), and the first transistor is used to reset the GN. Specifically, as shown in fig. 4, the first transistor T12 electrically connects the STV signal line and the scan signal output terminal G1 of the first stage GOA circuit unit. A first transistor T12 for resetting G1 with a timing signal supplied from the STV signal line. In addition, the timing signal provided by the STV signal line is also used for pre-charging the Q point of the pull-up signal control end of the first-stage GOA circuit unit.

In some possible embodiments, the plurality of GOA circuit units includes an i-th stage GOA circuit unit. For each grade of GOA circuit units cascaded after the first grade of GOA circuit unit, it can be recorded as the ith grade of GOA circuit unit, i is an integer greater than or equal to 2, and the reset unit of the ith grade of GOA circuit unit simultaneously resets the scanning signal output terminal GN and the pull-up signal control terminal Q point. Specifically, the reset unit of the ith-level GOA circuit unit is electrically connected to the STV signal line of the frame start pulse of the driving circuit, and is configured to reset the scanning signal output terminal GN and the Q point of the pull-up signal control terminal using the timing signal provided by the STV signal line. As shown in fig. 3, the reset unit 210 of the ith-stage GOA circuit unit 20 electrically connects the scan signal output terminal GN and the pull-up signal control terminal Q point for resetting GN and Q points, GN being located between the pull-up unit 220 and the discharge unit 230, and Q point being located between the pull-down unit 240 and the pull-up unit 220.

In some possible embodiments, the reset unit of the ith-stage GOA circuit unit may specifically include two transistors (denoted as a second transistor and a third transistor), where one transistor implements resetting of GN and the other transistor implements resetting of Q point. Specifically, as shown in fig. 5, the second transistor T11 electrically connects the STV signal line and the scan signal output terminal GN of the i-th stage GOA circuit unit, and the second transistor T11 resets GN by using the timing signal supplied from the STV signal line. The third transistor T12 is electrically connected to the STV signal line and the Q point of the pull-up signal control terminal of the ith-stage GOA circuit unit, and the third transistor T12 is used for resetting the Q point by using the timing signal provided by the STV signal line.

The first transistor, the second transistor, and the third transistor may specifically include a thin film field effect transistor.

In some possible embodiments, the discharge signal control terminal of the discharge unit of the jth GOA circuit unit in the plurality of GOA circuit units is electrically connected to the scan signal output terminal of the jth +2 GOA circuit unit in the plurality of GOA circuit units, and j is an integer greater than or equal to 1. As shown in fig. 4, the discharge signal control terminal of the discharge unit (composed of T3 and T4) of the first stage GOA circuit unit is electrically connected to the scan signal output terminal G3 of the third stage GOA circuit unit. As shown in fig. 5 again, for the GOA circuit units of the respective stages cascaded after the first stage GOA circuit unit, the discharge signal control terminal of the discharge unit (composed of T3 and T4) of the nth stage GOA circuit unit is electrically connected to the scan signal output terminal G (N +2) of the (N +2) th stage GOA circuit unit.

In some possible embodiments, the timing diagram of the signals of the GOA circuit corresponding to fig. 4 and 5 can be as shown in fig. 6. It can be seen that when the STV signal is at a high level, each transistor in the reset unit of each GOA circuit unit is turned on, so that before each frame starts to scan, the GN and Q points from the first GOA circuit unit to the last GOA circuit unit can be reset once by the STV signal, and possible noises at the GN and Q points can be eliminated.

In some possible embodiments, if the transistor is an n-mos fet, the voltage of the VSS1 signal is higher than the voltage of the VSS2 signal, and VSS1 and VSS2 are both negative voltages; if the transistor is a p-mos field effect transistor, the voltage of the VSS1 signal is lower than that of the VSS2 signal, and VSS1 and VSS2 are both positive voltages, so as to ensure that resetting of GN and Q points can be quickly and effectively completed. VDD is a direct current signal, and if the transistor adopts a p-mos field effect transistor, the voltage is positive; if the transistor adopts an n-mos field effect transistor, the negative voltage is adopted. Where 1H is the charging time, (1/Freq-t)/N, Freq is the frequency, N is the number of stages of the GOA circuit unit, and t is the blanking time. The reason why 1H is selected as the charging time is that when 4 CLK (i.e., CK1, CK2, CK3, CK4) are adopted, G (N-1) is used for turning on, and then G (N +2) is turned off, the Q point is provided with left and right shoulders (such as the Q point waveform in fig. 6), and the right shoulder appears, so that when the capacitor C is discharged, the capacitor C is simultaneously discharged through T2 and T3, the falling edge of the GN output waveform is reduced, the GN waveform is closer to the square wave, and a good reset effect is ensured.

The CK signal connection of each grade of the GOA circuit units may be: the CK input end of the first-stage GOA circuit unit is connected with CK1, the CK input end of the second-stage GOA circuit unit is connected with CK2, the CK input end of the third-stage GOA circuit unit is connected with CK3, and the CK input end of the fourth-stage GOA circuit unit is connected with CK 4; the CK input end of the GOA circuit unit of the fifth level is connected with CK1, the CK input end of the GOA circuit unit of the sixth level is connected with CK2 and … …, and the cycle is repeated.

The above description is related to the case where the operation mode is such that G (N-1) is on and then G (N +2) is off. As can be seen from fig. 5, the phrase "G (N-1) is turned on, and then G (N +2) is turned off" in the present application means that the scanning signal output terminal G (N-1) of the previous-stage GOA circuit unit is used as an input, and the discharging signal control terminal of the discharging unit uses the scanning signal output terminal G (N +2) of the N +2 th-stage GOA circuit unit as an input.

In some possible embodiments, another possible mode of operation is described below, namely, a mode of operation in which G (N-2) is turned on and then G (N +4) is turned off. For the action mode that G (N-2) is turned on and G (N +4) is turned off later, since the STV signal can play a role of precharging the previous two stages of GOA circuit units (including the first stage GOA circuit unit and the second stage GOA circuit unit), the previous two stages of GOA circuit units only need to reset the respective scanning signal output terminals GN, and the pull-up signal control terminals Q point does not reset, the reset units of the previous two stages of GOA circuit units may specifically include a transistor, and the transistor realizes the reset of GN, as specifically shown in fig. 7.

For each grade of GOA circuit unit cascaded after the second grade of GOA circuit unit, it can be recorded as the kth grade of GOA circuit unit, k is an integer greater than or equal to 3, and the reset unit of the kth grade of GOA circuit unit simultaneously resets the scanning signal output terminal GN and the pull-up signal control terminal Q point. Specifically, the reset unit of the kth-stage GOA circuit unit may specifically include two transistors, where one transistor implements resetting of GN and the other transistor implements resetting of Q point, as specifically shown in fig. 8.

The signal timing diagrams of the GOA circuits corresponding to fig. 7 and 8 can be shown in fig. 9. It can be seen that when the STV signal is at a high level, each transistor in the reset unit of each GOA circuit unit is turned on, so that before each frame starts to scan, the GN and Q points from the first GOA circuit unit to the last GOA circuit unit can be reset once by the STV signal, and possible noises at the GN and Q points can be eliminated.

At this time, 2H is selected as the charging time because the pre-charging time is increased, 8 CLK (i.e., CK1, CK2, CK3, CK4, CK5, CK6, CK7, and CK8) are adopted, G (N-2) is used for turning on, and then G (N +4) is turned off, so that the Q point can carry the left and right shoulders (such as the Q point waveform in fig. 9), and the right shoulder appears, so that the capacitor C can be discharged simultaneously through T2 and T3 when being discharged, the falling edge of the GN output waveform is reduced, the GN waveform is made to be closer to the square wave, and a good reset effect is ensured.

The CK signal connection of each grade of the GOA circuit units may be: the CK input end of the first-level GOA circuit unit is connected with CK1, the CK input end of the second-level GOA circuit unit is connected with CK2, the CK input end of the third-level GOA circuit unit is connected with CK3, the CK input end of the fourth-level GOA circuit unit is connected with CK4, the CK input end of the fifth-level GOA circuit unit is connected with CK5, the CK input end of the sixth-level GOA circuit unit is connected with CK6, the CK input end of the seventh-level GOA circuit unit is connected with CK7, and the CK input end of the eighth-level GOA circuit unit is connected with CK 8; the CK input end of the GOA circuit unit of the ninth level is connected with CK1, the CK input end of the GOA circuit unit of the tenth level is connected with CK2 and … …, and the operation is repeated in sequence.

As can be seen from fig. 8, the phrase "G (N-2) is turned on and then G (N +4) is turned off" in the present application means that the scanning signal output terminal G (N-2) of the GOA circuit units of the first two stages is used as an input, and the discharging signal control terminal of the discharging unit uses the scanning signal output terminal G (N +4) of the GOA circuit unit of the (N +4) th stage as an input.

It should be noted that other possible operation modes may also be adopted according to the manner provided by the present application, and the embodiment of the present application does not limit the specific operation mode.

In the embodiment of the present application, the driving circuit 10 includes a plurality of GOA circuit units 20, the plurality of GOA circuit units 20 are cascaded, each GOA circuit unit 20 includes a reset unit 210, the reset unit 210 is electrically connected to the STV signal line of the driving circuit 10, the reset unit 210 is configured to reset at least one of the scanning signal output terminal GN and the pull-up signal control terminal Q point of the GOA circuit unit 20 by using the timing signal provided by the STV signal line, the scanning signal output terminal GN and the pull-up signal control terminal Q point of the GOA circuit can be effectively reset by multiplexing the timing signal of the STV signal line of the GOA circuit, so as to eliminate the noise affecting the panel display area in the image of the previous frame, that is, only one STV signal line is needed, not only the output potential of the previous frame GN but also the output potential of the Q point of the previous frame can be effectively released, thereby avoiding introducing a new signal input source, the working stability of the GOA circuit is improved.

Fig. 10 is a schematic structural diagram of a display device according to an embodiment of the present application. The display device comprises a controller 30, the driving circuit 10 described in the previous embodiment, and a display panel 40, wherein the controller 30 is electrically connected with the driving circuit 10, and the driving circuit 10 is electrically connected with the display panel 40. Data may be exchanged between the controller 30, the driving circuit 10, and the display panel 40.

The display panel 40 is driven by the driving circuit 10 to display a screen such as a character or an image.

An embodiment of the present application also provides an electronic device, which includes the display device shown in fig. 10.

It should be understood that the application of the present application is not limited to the above examples, and that modifications or changes may be made by those skilled in the art based on the above description, and all such modifications and changes are intended to fall within the scope of the appended claims.

Claims (10)

1. The driving circuit is characterized by comprising a plurality of array substrate row driving GOA circuit units, wherein the GOA circuit units are cascaded;

each GOA circuit unit comprises a reset unit, and the reset unit is electrically connected with a frame starting pulse STV signal line of the driving circuit;

and the reset unit is used for resetting at least one of the scanning signal output end and the pull-up signal control end of the GOA circuit unit by using the time sequence signal provided by the STV signal line.

2. The driving circuit according to claim 1, wherein the plurality of GOA circuit units include a first-stage GOA circuit unit, and the reset unit of the first-stage GOA circuit unit is electrically connected to an STV signal line of a frame start pulse of the driving circuit, and is configured to reset a scan signal output terminal of the first-stage GOA circuit unit by using a timing signal provided by the STV signal line.

3. The driving circuit according to claim 2, wherein the reset unit of the first stage GOA circuit unit includes a first transistor electrically connected to the STV signal line and the scan signal output terminal of the first stage GOA circuit unit;

and the first transistor is used for resetting a scanning signal output end of the first-stage GOA circuit unit by using a timing signal provided by the STV signal line.

4. The driving circuit of claim 2, wherein the timing signal provided by the STV signal line is further used to precharge a pull-up signal control terminal of the first stage GOA circuit unit.

5. The driving circuit according to any one of claims 2 to 4, wherein the plurality of GOA circuit units comprise an i-th GOA circuit unit, the reset unit of the i-th GOA circuit unit is electrically connected to the STV signal line of the frame start pulse of the driving circuit, and is configured to reset the scan signal output terminal and the pull-up signal control terminal of the i-th GOA circuit unit by using a timing signal provided by the STV signal line, and i is an integer greater than or equal to 2.

6. The driving circuit as claimed in claim 5, wherein the reset unit of the ith-stage GOA circuit unit includes a second transistor electrically connected to the STV signal line and a scan signal output terminal of the ith-stage GOA circuit unit, and a third transistor electrically connected to the STV signal line and a pull-up signal control terminal of the ith-stage GOA circuit unit;

the second transistor is used for resetting a scanning signal output end of the ith-level GOA circuit unit by using a timing signal provided by the STV signal line;

and the third transistor is used for resetting the pull-up signal control end of the ith-level GOA circuit unit by using a timing signal provided by the STV signal line.

7. The driving circuit according to claim 5, wherein each GOA circuit unit further comprises a discharge unit;

the discharging signal control end of the discharging unit of the jth grade GOA circuit unit in the GOA circuit units is electrically connected with the scanning signal output end of the jth +2 grade GOA circuit unit in the GOA circuit units, and j is an integer greater than or equal to 1.

8. The driver circuit according to claim 3, wherein the first transistor comprises a thin film field effect transistor.

9. A display device comprising a controller, a display panel, and the driver circuit according to any one of claims 1 to 8, wherein the controller is electrically connected to the driver circuit, and wherein the driver circuit is electrically connected to the display panel.

10. An electronic device characterized by comprising the display device according to claim 9.

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