CN212658792U

CN212658792U - Testing device and testing system

Info

Publication number: CN212658792U
Application number: CN202021791169.0U
Authority: CN
Inventors: 王树锋; 陈阳
Original assignee: Qianhai Jingyun Shenzhen Storage Technology Co ltd
Current assignee: Qianhai Jingyun Shenzhen Storage Technology Co ltd
Priority date: 2020-08-24
Filing date: 2020-08-24
Publication date: 2021-03-05
Anticipated expiration: 2030-08-24

Abstract

The application discloses testing arrangement and test system, this testing arrangement includes: the device comprises a test circuit, a power supply circuit, a detection circuit and a processing circuit, wherein the test circuit is connected with a chip to be tested and the detection circuit, the processing circuit is connected with the detection circuit, and the power supply circuit is respectively connected with the test circuit, the detection circuit and the processing circuit; the processing circuit controls the power supply circuit to output a first voltage to the chip to be tested through the test circuit, and the test circuit performs system test on the chip to be tested under the first voltage; the processing circuit controls the power supply circuit to output a second voltage to the chip to be tested through the detection circuit to replace the first voltage, the test circuit performs system test on the chip to be tested under the second voltage, the chip to be tested performs voltage bias limit test under the second voltage, and the detection circuit detects the electrical signal state of the chip to be tested. This application realizes the hot replacement of voltage under operating condition through using the first voltage of second voltage replacement to be convenient for carry out the limit test of pulling partially when carrying out the system test to the chip that awaits measuring.

Description

Testing device and testing system

Technical Field

The present application relates to the field of chip testing, and in particular, to a testing apparatus and a testing system.

Background

The testing device is used for testing the chip to be tested in the prior art, different testing voltages need to be switched when various tests are carried out, the testing chip is generally required to be powered off and then powered on, and the testing efficiency is low. Meanwhile, a single power supply circuit is generally used for supplying power to the whole testing device, and a detection circuit is not arranged for monitoring the working state of the testing device. When the power supply problem occurs due to the short circuit of the test chip, the failed element cannot be monitored in time, and the test device is damaged.

SUMMERY OF THE UTILITY MODEL

The application provides at least a testing device and a testing system.

This application first aspect provides a testing arrangement for bear the weight of the chip that awaits measuring and test the chip that awaits measuring, this testing arrangement includes:

the test circuit is used for connecting the chip to be tested and carrying out system test on the chip to be tested;

the detection circuit is connected with the test circuit and used for detecting the electric signal state of the chip to be detected;

the processing circuit is connected with the detection circuit;

the power supply circuit is respectively connected with the test circuit, the detection circuit and the processing circuit and is connected with a power supply for supplying power;

the processing circuit is used for controlling the power supply circuit to output a first voltage to the chip to be tested through the test circuit, so that the test circuit performs system test on the chip to be tested under the first voltage; the processing circuit is also used for controlling the power supply circuit to output a second voltage to the chip to be tested through the detection circuit to replace the first voltage, so that the test circuit performs system test on the chip to be tested under the second voltage, the chip to be tested performs voltage bias limit test under the second voltage, and the detection circuit detects the state of an electrical signal of the chip to be tested during the voltage bias limit test.

Optionally, the electrical signal comprises a detection current signal and a detection voltage signal, and the detection circuit comprises:

the power supply chip is respectively connected with the power supply circuit and the processing circuit and is used for converting the power supply voltage of the power supply circuit into output voltage and outputting the output voltage to the chip to be tested;

the sampling resistor is connected between the power supply chip and the test circuit;

the electrical detection module is respectively connected with two ends of the sampling resistor and used for detecting the voltage of the sampling resistor to obtain a detection voltage;

the AD conversion chip is connected with one end of the sampling resistor and used for detecting the current of the sampling resistor to obtain a detection current and AD converting the detection current into a detection current signal;

the AD conversion chip is further connected with one end of the electrical detection module and is used for AD converting the detection voltage into a detection voltage signal;

the AD conversion chip is further connected with the processing circuit and used for transmitting the detection voltage signal and the detection current signal to the processing circuit.

Optionally, the power supply chip is provided with a potentiometer for regulating the output voltage of the power supply chip under the control of the processing circuit.

Optionally, the processing circuit is preset with a current threshold range, and the processing circuit is configured to compare the detected current signal with the current threshold range; the processing circuit responds to the fact that the detected current signal exceeds the current threshold range, and then the power supply circuit is controlled to stop outputting the power supply voltage to the power supply chip.

Optionally, the processing circuit is preset with a voltage threshold range, the detection current is within the current threshold range, and the processing circuit responds to the detection current signal within the current threshold range, so as to adjust the potentiometer of the power supply chip to control the output voltage of the power supply chip;

if the output voltage of the control power supply chip is within the voltage threshold range and is output as a plurality of different voltages, the processing circuit is used for detecting the detection current under the plurality of different voltages in real time through the AD conversion chip; or,

if the voltage output by the power supply chip is controlled to be the second voltage, the chip to be tested is subjected to voltage bias limit test, the processing circuit is used for detecting the detection current under the second voltage in real time through the AD conversion chip, and the second voltage is larger than or equal to the maximum voltage within the voltage threshold range or is smaller than or equal to the minimum voltage within the voltage threshold range.

Optionally, the power supply chip is preset with a threshold current and a cut-off voltage, and the processing circuit is preset with a test time;

when the detection current is larger than the threshold current, the output voltage of the power supply chip is cut-off voltage, and the processing circuit receives a detection voltage signal corresponding to the cut-off voltage in the test time, the power supply chip is turned off.

Optionally, the power supply circuit further comprises a switch, and the switch is respectively connected with the test circuit and the processing circuit;

the processing circuit is used for receiving a detection voltage signal corresponding to the cut-off voltage when the detection voltage signal is received within the test time, the switch is closed, and the power supply circuit stops outputting the power supply voltage to the test circuit.

Optionally, the power supply circuit includes a first voltage stabilizer and a second voltage stabilizer, the first voltage stabilizer is connected to the power supply and is configured to convert the high-voltage direct current into a first threshold voltage, and the second voltage stabilizer is respectively connected to the first voltage stabilizer, the power chip and the processing circuit and is configured to convert the first threshold voltage into a second threshold voltage so as to supply power to the power chip and the processing circuit.

The second aspect of the application provides a test system, including as above-mentioned testing arrangement and host computer, the host computer passes through serial ports with processing circuit and connects, and the host computer passes through processing circuit and sends test instruction to the chip that awaits measuring, and the chip that awaits measuring tests according to test instruction.

The beneficial effect of this application is: be different from prior art, this application realizes the hot replacement of voltage under operating condition through the mode that uses the second voltage to replace first voltage, is convenient for carry out the system test to the chip that awaits measuring and carries out the limit test of pulling off the bias to the chip that awaits measuring simultaneously to can acquire the biggest borne voltage and the minimum operating voltage of the chip that awaits measuring.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic structural diagram of an embodiment of a test apparatus of the present application;

FIG. 2 is a schematic structural diagram of another embodiment of the test apparatus of the present application;

FIG. 3 is a schematic structural diagram of a testing apparatus according to yet another embodiment of the present application;

FIG. 4 is a schematic block diagram of an embodiment of a test system of the present application;

FIG. 5 is a schematic flow chart diagram of an embodiment of a testing method of the present application.

Detailed Description

In order to make those skilled in the art better understand the technical solution of the present application, the following describes the testing device and the testing system provided in the present application in further detail with reference to the accompanying drawings and the detailed description. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first", "second", etc. in this application are used to distinguish between different objects and not to describe a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of a testing apparatus of the present application. As shown in fig. 1, the testing apparatus 1 includes a testing circuit 10, a power supply circuit 20, a detection circuit 31, and a processing circuit 40, where the testing circuit 10 is connected to the chip 11 to be tested, and is used for performing a system test on the chip 11 to be tested.

The test apparatus 1 of the present embodiment may be provided in a plate shape, and is, for example, a test board for mounting on a tester. The test board may be detachably mounted on the automatic testing machine. The test board may be used to carry the chip 11 to be tested and perform a system test on the chip 11 to be tested. In other words, the test board can simulate the operation process of the chip 11 to be tested on the actual terminal, so as to detect whether the chip 11 to be tested has a defect, and further record the defect information. The chip 11 to be tested takes a DRAM chip as an example, and when the test board is installed on an automatic test machine to perform a system test on the chip 11 to be tested, it is possible to detect whether the chip 11 to be tested has a problem of a damaged or error-reported memory address, and further record the memory address having the problem, and upload the memory address to a server or record the memory address on the chip 11 to be tested. When the chip 11 to be tested is used in the actual terminal, the actual terminal can acquire the memory address with the problem, and then the memory address with the problem can not be called, so that the chip 11 to be tested can well run on the actual terminal.

In addition, the test circuit 10 of the test apparatus 1 may have thereon a CPU adapted to the chip 11 under test. That is, the test circuit 10 may be adjusted or replaced according to the corresponding test manufacturer and application terminal, so as to simulate the operation environment of the final actual terminal. Of course, the test circuit 10 may further include a memory, such as a ROM, to cooperate with the CPU to test the chip 11 to be tested. Taking Hua as an example, when testing a DRAM chip of Hua mobile phone with Kaolin CPU, the COU on the test circuit 10 of the test device 1 can be replaced by the corresponding Kaolin CPU, so that the test result is more accurate and the compatibility is better. The processing circuit 40 may receive an instruction, a signal, or data of the CPU on the test circuit 10, and may be used for the test circuit 10 to record and forward a test result of the chip 11 to be tested, or issue a test instruction to the CPU of the test circuit 10. The DRAM chip tested at this time may be a RAM (volatile memory) to be tested in cooperation with the CPU, specifically one of SDRAM and DDRAM.

On the other hand, the chip 11 under test may be integrated with a CPU, and may be tested in cooperation with a memory on the test circuit 10, such as a RAM or a ROM. The processing circuit 40 may receive an instruction, a signal, or data of the CPU on the chip 11 to be tested, and may be used for the test circuit 10 to record and forward a test result of the chip 11 to be tested, or issue a test instruction to the CPU of the chip 11 to be tested, or the like.

The testing device 1 carries out system testing on the chip 11 to be tested, can test whether the chip 11 to be tested has logic problems or not, can test the compatibility of the chip 11 to be tested and the adaptive testing circuit 10, can further test the compatibility of the chip 11 to be tested and an actual terminal compared with the traditional physical logic testing, has lower cost and strong expansibility and adjustability, can be rapidly adapted to different products and different manufacturers, and meets the requirements of different customers.

The power supply circuit 20 is connected to the test circuit 10, the detection circuit 31, and the processing circuit 40, and outputs a power supply voltage to the test circuit 10, the detection circuit 31, and the processing circuit 40 to supply power to the test circuit 10, the detection circuit 31, and the processing circuit 40.

The detection circuit 31 is connected to the test circuit 10 and the processing circuit 40, and is configured to detect an electrical signal state of the chip 11 to be tested, and output the electrical signal state of the chip 11 to be tested to the processing circuit 40.

In order to realize the function of the testing device 1 for testing the system of the chip 11 to be tested, a voltage source is arranged inside the testing circuit 10 of the testing device 1 and used as a testing voltage source for the chip 11 to be tested. The test circuit 10 outputs a first voltage to the chip 11 to be tested as a test voltage of the chip 11 to be tested, so that the test circuit 10 performs a system test on the chip 11 to be tested under the first voltage.

Before the system test, the chips 11 to be tested need to be screened to ensure that the chips 11 to be tested which are used for the system test are all normally working test chips, so that the test device 1 is prevented from being damaged due to short circuit of the chips 11 to be tested which are damaged. Specifically, the processing circuit 40 controls the detection circuit 31 to operate, so that the power supply circuit 20 outputs a short-circuit detection voltage to the chip 11 to be detected through the detection circuit 31; if the chip 11 to be tested works normally, the processing circuit 40 controls the power supply circuit 20 to output a power supply voltage to the test circuit 10, so that the test circuit 10 outputs a first voltage to the chip 11 to be tested, and controls the detection circuit 31 to be turned off; if the chip 11 to be tested is abnormally operated, i.e. short-circuited, the processing circuit 40 directly controls the detection circuit 31 to be turned off.

In order to perform the voltage bias limit test on the chip 11 to be tested, the processing circuit 40 further controls the power supply circuit 20 to output the second voltage to the chip 11 to be tested, and gradually increases the second voltage. When the second voltage is increased to be greater than the first voltage, the second voltage replaces the first voltage to become a power supply of the test circuit 10, so that the test circuit 10 performs a system test on the chip 11 to be tested under the second voltage, the chip 11 to be tested performs a voltage bias limit test under the second voltage, and the detection circuit 31 detects an electrical signal state of the chip 11 to be tested during the voltage bias limit test.

With reference to fig. 1 and with further reference to fig. 2, fig. 2 is a schematic structural diagram of another embodiment of the testing apparatus of the present application. As shown in fig. 2, the power supply circuit 20 includes a switch 21, a first regulator 22, and a second regulator 23. The first voltage stabilizer 22 is connected to the switch 21 and the second voltage stabilizer 23, and the power supply circuit 20 is connected to the test circuit 10, the processing circuit 40 and the detection circuit 31 through the switch 21 and the second voltage stabilizer 23.

The detection circuit 31 includes a power supply chip 311, a sampling resistor 312, an electrical detection module 313, an AD conversion chip 314, an operational amplifier 315, and a low-pass filter 316. The power supply chip 311 is provided with a potentiometer 3111 for adjusting an output voltage of the power supply chip 311. Optionally, the potentiometer 3111 may be an adjustable resistor. Alternatively, the low pass filter 316 may be an RC low frequency filter. Alternatively, the amplification factor of the operational amplifier 315 may be 50 times.

The power supply chip 311 is connected to the power supply circuit 20 via the second regulator 23, and is connected to the processing circuit 40. The power supply chip 311 is configured to convert the power supply voltage of the power supply circuit 20 into an output voltage, and output the output voltage to the chip 11 to be tested. The power supply chip 311 is used for voltage conversion, and may be a voltage conversion chip, such as an LT3045 chip.

The detection circuit 31 detects electrical signals of the chip 11 to be tested during the pull-out limit test, including a detection current signal and a detection voltage signal.

The sampling resistor 312 is connected between the power supply chip 311 and the test circuit 10. The electrical detection module 313 is respectively connected to two ends of the sampling resistor 312, and detects a voltage drop across the sampling resistor 312 to obtain a detection voltage. Alternatively, the electrical detection module 313 may obtain the detection current according to the resistance value of the sampling resistor 312 and the detection voltage.

The AD conversion chip 314 is connected to one end of the sampling resistor 312 through the operational amplifier 315 and the low-pass filter 316, detects the current of the sampling resistor 312 to obtain a detection current, and AD converts the detection current into a detection current signal; the AD conversion chip 314 is connected to one end of the electrical detection module 313 through the low pass filter 316, and AD-converts the detection voltage into a detection voltage signal; the AD conversion chip 314 is further connected to the processing circuit 40, and transmits the detection voltage signal and the detection current signal to the processing circuit 40.

The first regulator 22 is configured to convert the high voltage dc power to a first threshold voltage. Optionally, the high voltage direct current is 12V, and the first threshold voltage is 4.4V. The second voltage regulator 23 is used for further converting the first threshold voltage into a second threshold voltage, so that the output voltage can meet the operating voltage requirements of the power chip 311 and the processing circuit 40. Optionally, the second threshold voltage is 3.3V. The power supply chip 311 further converts the second threshold voltage of the second voltage regulator 23 into an output voltage meeting the operating voltage requirement of the chip 11 to be tested.

The processing circuit 40 is preset with a current threshold range, and the processing circuit 40 compares the detected current signal with the current threshold range.

In order to better screen the chips 11 to be tested, it is necessary to detect whether the chips 11 to be tested are short-circuited. The processing circuit 40 controls the power supply circuit 20 to output a short-circuit detection voltage to the chip 11 to be detected through the detection circuit 31, and at this time, the processing circuit 40 detects a detection current signal of the chip 11 to be detected through the detection circuit 31 and compares the detection current signal with a current threshold range; if the detected current signal is within the current threshold range, it indicates that the chip 11 to be tested normally works, the processing circuit 40 controls the power supply chip 311 to be turned off, and controls the switch 21 to be turned on at the same time, so that the power supply circuit 20 outputs a power supply voltage to the test circuit 10, and the test circuit 10 outputs a test voltage to the chip 11 to be tested through the voltage source, so that the test circuit 10 performs a system test on the chip 11 to be tested at a first voltage; if the detected current signal exceeds the current threshold range, it indicates that the chip 11 to be detected is in an abnormal operation, that is, the chip 11 to be detected is in a short circuit, the processing circuit 40 controls the power supply chip 311 to be turned off, so that the power supply circuit 20 stops outputting the short circuit detection voltage to the chip 11 to be detected.

The processing circuit 40 is preset with a voltage threshold range, the detection current is within the current threshold range, the processing circuit 40 controls the power chip 311 to be turned on, the second voltage replaces the first voltage, so that the test circuit 10 performs a system test on the chip 11 to be tested under the second voltage, and the processing circuit 40 compares the detection voltage signal with the voltage threshold range. The processing circuit 40 responds to the detected current signal being within the current threshold range, and then adjusts the potentiometer 3111 of the power chip 311 to control the output voltage of the power chip 311.

When the second voltage replaces the first voltage and the chip 11 to be tested performs the pull-out limit test, the processing circuit 40 adjusts the potentiometer 3111 to continuously change the output voltage of the power chip 311 within the voltage threshold range, so that the power chip 311 outputs a plurality of different voltages, and the processing circuit 40 detects the detection currents at the plurality of different voltages in real time through the AD conversion chip 314 to detect the working states and the working currents of the chip 11 to be tested at the different voltages in real time. Wherein the second voltage is greater than or equal to a maximum voltage within a voltage threshold range, or the second voltage is less than or equal to a minimum voltage within the voltage threshold range.

In response to the detected current signal exceeding the current threshold range, the processing circuit 40 controls the switch 21 to be turned off, and further controls the power supply circuit 20 to stop outputting the power supply voltage to the test circuit 10, and controls the power supply chip 311 to be turned off.

Further, the processing circuit 40 adjusts the potentiometer 3111 of the power chip 311 to make the output voltage of the power chip 311 exceed the working voltage range of the chip 11 to be tested, so as to obtain the maximum withstand voltage and the minimum working voltage of the chip 11 to be tested.

The preset current threshold range and voltage threshold range of the processing circuit 40 are equal to the standard working current range and standard working voltage range of the chip 11 to be tested.

The power supply chip 311 is preset with a threshold current and a cutoff voltage, and the processing circuit 40 is preset with a test time. Alternatively, the threshold current may be 100 mA. The threshold current is related to the working current of the chip 11 to be tested and is greater than the maximum working current of the chip 11 to be tested. Alternatively, the cutoff voltage may be 0.2V. Alternatively, the test time may be 150 ms.

When the chip 11 to be tested is short-circuited and the detection current is greater than the threshold current, the power supply chip 311 reduces the output voltage to the cut-off voltage according to the pin function of itself, that is, the output voltage is the cut-off voltage, and the current flowing through the sampling resistor 312 is zero at this time. The cut-off voltage is converted into a detection voltage signal by the AD conversion chip 314, and the processing circuit 40 receives the detection voltage signal corresponding to the cut-off voltage within the test time, that is, detects that the detection voltage and the detection current are abnormal, controls the enable pin of the power chip 311, and turns off the power chip 311. At the same time, the processing circuit 40 closes the switch 21, so that the power supply circuit 20 stops outputting the power supply voltage to the test circuit 10.

With reference to fig. 1-2 and with further reference to fig. 3, fig. 3 is a schematic structural diagram of another embodiment of the testing apparatus of the present application. Different from the above embodiments, the testing device 1 of the present embodiment further includes a first PMOS transistor 37, a second PMOS transistor 50, a first detecting circuit 32, and a second detecting circuit 33.

The first PMOS transistor 37 is disposed between the sampling resistor 312 and the test circuit 10, and is used for power isolation and preventing current from flowing backwards, so as to prevent the chip 11 to be tested from being short-circuited to cause the problem of burning out of the detection circuit 31.

The second PMOS transistor 50 is disposed between the power supply circuit 20 and the test circuit 10, and is used for power isolation and preventing current from flowing backwards, so as to prevent the problem that the power supply circuit 20 is burned out due to a short circuit of the chip 11 to be tested.

In this embodiment, a DRAM chip is taken as an example, and the DRAM chip includes three test voltages, namely VDD1, VDD2 and VDDQ, to implement the test of three functions of the DRAM chip. Therefore, three detection circuits are required to be correspondingly arranged to detect the current of the DRAM chip in the standby state and the operating state of the DRAM chip at three test voltages, and the detection circuit 31, the first detection circuit 32, and the second detection circuit 33 of the present embodiment form a total detection circuit 30. Three sub-voltage sources VDD1, VDD2 and VDDQ among the voltage sources of the test circuit 10 are respectively tested on the DRAM chip before voltage hot replacement is not performed; after the voltage hot replacement, the power supply circuit 20 supplies power to the chip 11 to be tested through the detection circuit 31, the first detection circuit 32 and the second detection circuit 33 respectively, and replaces the sub-voltage sources VDD1, VDD2 and VDDQ respectively; meanwhile, the processing circuit 40 detects the operating state of the chip 11 through the detection circuit 31, the first detection circuit 32 and the second detection circuit 33.

The first detection circuit 32 and the second detection circuit 33 have the same structure as the detection circuit 31, specifically, the first detection circuit 32 includes a first power chip 321, a first sampling resistor 322, a first electrical detection module 323, a first AD conversion chip 324, a first operational amplifier 325, a first low-pass filter 326 and a third PMOS transistor 327, and the first power chip 321 is provided with a first potentiometer 3211; the second detection circuit 33 includes a second power supply chip 331, a second sampling resistor 332, a second electrical detection module 333, a second AD conversion chip 334, a second operational amplifier 335, a second low-pass filter 336, and a fourth PMOS transistor 337, and the second power supply chip 331 is provided with a second potentiometer 3311.

In this embodiment, the detection circuit 31, the first detection circuit 32 and the second detection circuit 33 are used to detect three functions of the chip 11, and the processing circuit 40 respectively adjusts the potentiometer 3111 of the detection circuit 31, the potentiometer 3211 of the first detection circuit 32 and the potentiometer 3311 of the second detection circuit 33, so that the output voltages of the detection circuit 31, the first detection circuit 32 and the second detection circuit 33 are respectively within the first voltage range, the second voltage range and the third voltage range of the chip 11.

The range of VDD1 of the DRAM chip is 1.70V-1.95V, the range of VDD2 is 1.06V-1.17V, the range of VDDQ is 1.06V-1.17V, namely the voltage regulation ranges of the detection circuit 31, the first detection circuit 32 and the second detection circuit 33 are 1.70V-1.95V, 1.06V-1.17V and 1.06V-1.17V respectively, and the limit voltage of the chip 11 to be tested is 1.06V and 1.95V.

The range of IDD1 of DRAM chip is 2mA-3mA, the range of IDD2 is 2.3mA-5mA, and the range of IDDQ is 0.04mA-0.08 mA. Since the current of the chip 11 to be tested in the standby state increases with the increase of the bad blocks of the chip 11 to be tested, the chip 11 to be tested can be classified by comparing the currents of the chip 11 to be tested in the standby state, and the smaller the current of the chip 11 to be tested in the standby state is, the better the chip 11 to be tested is.

The processing circuit 40 may include a Microprocessor (MCU), and may further include a FLASH memory and a ROM memory, etc. adapted to the microprocessor, so as to store the relevant data of the test circuit 10, the power supply circuit 20 and the detection circuit 31, etc., and ensure the normal operation of the test process.

Referring to fig. 4, fig. 4 is a schematic structural diagram of an embodiment of the test system of the present application. The test system 4 includes a test apparatus 41 and a host 42, and the test apparatus 41 is the test apparatus 1 disclosed in the above embodiments and will not be described herein again.

The host 42 is connected with the processing circuit 40 through a serial port, the host 42 sends a test instruction to the chip 11 to be tested through the processing circuit 40, and the chip 11 to be tested performs testing according to the test instruction. Optionally, the serial port includes at least one of a USB serial port and a network serial port.

Specifically, the host 42 sends an instruction to the processing circuit 40 through the serial port, and the processing circuit 40 receives the instruction and performs verification. When the check instruction is incomplete, the processing circuit 40 reports an instruction error to the host 42; when the instruction is verified to be complete, the processing circuit 40 further determines the type of the instruction and performs the corresponding operation. Optionally, the type of the instruction specifically includes at least one of reading device information, upgrading the device, setting information of the chip 11 to be tested, and a test command. The test command may include at least one of a test of the chip 11 to be tested and a power-on/power-off test of the test circuit 10.

Referring to fig. 5, fig. 5 is a schematic flowchart of an embodiment of the testing method of the present application, and specific testing steps are shown in fig. 5.

S11: receiving a power-on instruction of a host through a processing circuit;

s12: performing short circuit test on the chip to be tested through the detection circuit;

s13: if the short circuit is not detected, the power supply circuit supplies power to the test circuit, and the processing circuit sends a test instruction to the test circuit;

the host 42 is connected with the processing circuit 40 through a serial port, the processing circuit 40 is connected with the test circuit 10 through a serial port, and the host 42 sends a test instruction to the test circuit 10 through the processing circuit 40.

S14: outputting a first voltage to the chip to be tested through the power supply circuit and the test circuit, and performing system test on the chip to be tested under the first voltage by the test circuit in response to a test instruction;

s15: the processing circuit controls the power supply circuit to output a second voltage to the chip to be tested through the detection circuit to replace the first voltage, so that the test circuit performs system test on the chip to be tested under the second voltage, and the chip to be tested performs voltage deviation limit test under the second voltage;

s16: and detecting the electrical signal state of the chip to be detected during the pull-bias limit test through the detection circuit.

The electrical signal comprises a detection current signal and a detection voltage signal.

The processing circuit 40 compares the detected current signal with the current threshold range, and when the detected current signal exceeds the current threshold range, the processing circuit 40 determines that the circuit is abnormal, controls the power supply circuit 20 to stop working, and reports the current signal to the host 42.

When the detected current signal is within the current threshold range, the processing circuit 40 compares the detected voltage signal with the voltage threshold range. When the detected voltage signal exceeds the voltage threshold range, the processing circuit 40 adjusts the potentiometer 3111 so that the output voltage of the power chip 311 is within the voltage threshold range.

When the output voltage of the power supply chip 311 is adjusted to be within the voltage threshold range by the processing circuit 40, if the current detection signal is outside the current threshold range, the processing circuit 40 determines that the circuit is abnormal, controls the power supply circuit 20 to stop working, and reports the current to the host 42.

The voltage hot replacement under the working state is realized by using the second voltage to replace the first voltage; meanwhile, the chip 11 to be tested is subjected to a pull-out limit test, the maximum bearing voltage and the minimum working voltage of the chip 11 to be tested can be obtained, and the working state of the chip 11 to be tested is detected and regulated in real time by using the detection circuit 31. Meanwhile, the processing circuit 40 can make the output voltage of the power chip 311 respectively located in the first voltage range, the second voltage range and the third voltage range of the chip 11 to be tested by adjusting the potentiometer 3111 to perform testing at different operating voltages. In addition, by obtaining the current of the chip 11 to be tested in the standby state, the chip 11 to be tested can be classified. In addition, when the chip 11 to be tested is short-circuited, the processing circuit 40 controls the power supply circuit 20 to stop outputting the power supply voltage to the test circuit 10, so that automatic overcurrent protection can be realized, and abnormal power supply of the power supply circuit 20 caused by short circuit of the chip 11 to be tested is prevented, and the test device 1 is further damaged.

The above embodiments are merely examples, and not intended to limit the scope of the present application, and all modifications, equivalents, and flow charts using the contents of the specification and drawings of the present application, or those directly or indirectly applied to other related arts, are included in the scope of the present application.

Claims

1. The utility model provides a testing arrangement which characterized in that for bear the weight of the chip that awaits measuring and to the chip that awaits measuring tests, include:

the detection circuit is connected with the test circuit and is used for detecting the electric signal of the chip to be detected;

the processing circuit is connected with the detection circuit;

the processing circuit is used for controlling the power supply circuit to output a first voltage to the chip to be tested through the test circuit, so that the test circuit performs the system test on the chip to be tested under the first voltage; the processing circuit is also used for controlling the power supply circuit to output a second voltage to the chip to be tested through the detection circuit so as to replace the first voltage, so that the test circuit is right for the chip to be tested to be carried out under the second voltage for system test, and the chip to be tested is subjected to voltage deviation limit test under the second voltage, and the detection circuit detects an electrical signal when the chip to be tested is subjected to the deviation limit test.

2. The test device of claim 1, wherein the electrical signal comprises a sense current signal and a sense voltage signal, the sense circuit comprising:

the AD conversion chip is connected with one end of the sampling resistor, and is used for detecting the current of the sampling resistor to obtain a detection current and AD converting the detection current into a detection current signal;

the AD conversion chip is further connected with one end of the electrical detection module and is used for AD converting the detection voltage into the detection voltage signal;

3. The test device of claim 2, wherein the power supply chip is provided with a potentiometer for adjusting the output voltage of the power supply chip under control of the processing circuit.

4. A test device according to claim 3, wherein the processing circuit is pre-set with a current threshold range, the processing circuit being configured to compare the detected current signal with the current threshold range; and the processing circuit responds to the fact that the detection current signal exceeds the current threshold range, and then controls the power supply circuit to stop outputting power supply voltage to the power supply chip.

5. The testing device of claim 4, wherein the processing circuit is preset with a voltage threshold range, and the processing circuit responds to the detection current signal being within the current threshold range to adjust a potentiometer of the power supply chip so as to control the output voltage of the power supply chip;

and if the output voltage of the power supply chip is controlled to be within the voltage threshold range and output as a plurality of different voltages, the processing circuit is used for detecting the detection current under the plurality of different voltages in real time through the AD conversion chip.

6. The test device of claim 5,

if the output voltage of the power supply chip is controlled to be the second voltage, the chip to be tested performs the voltage bias limit test, the processing circuit is used for detecting the detection current under the second voltage in real time through the AD conversion chip, and the second voltage is greater than or equal to the maximum voltage within the voltage threshold range or is less than or equal to the minimum voltage within the voltage threshold range.

7. The test device according to claim 6, wherein the power supply chip is preset with a threshold current and a cut-off voltage, and the processing circuit is preset with a test time;

the detection current is larger than the threshold current, the output voltage of the power supply chip is the cut-off voltage, and the processing circuit receives the detection voltage signal corresponding to the cut-off voltage in the test time, and then the power supply chip is turned off.

8. The test device of claim 7, wherein the power supply circuit further comprises switches connected to the test circuit and the processing circuit, respectively;

the processing circuit is used for receiving the detection voltage signal as the detection voltage signal corresponding to the cut-off voltage within the test time, closing the switch, and stopping outputting the power supply voltage to the test circuit by the power supply circuit.

9. The testing device of claim 8, wherein the power supply circuit comprises a first voltage regulator and a second voltage regulator, the first voltage regulator is connected to the power supply and is configured to convert the high voltage direct current into a first threshold voltage, and the second voltage regulator is respectively connected to the first voltage regulator, the power chip and the processing circuit and is configured to convert the first threshold voltage into a second threshold voltage so as to supply power to the power chip and the processing circuit.

10. A test system, comprising the test apparatus according to any one of claims 1 to 9 and a host, wherein the host is connected to the processing circuit via a serial port, the host sends a test command to the chip to be tested via the processing circuit, and the chip to be tested performs a test according to the test command.