CN212627702U - Frequency converter and control system thereof - Google Patents
Frequency converter and control system thereof Download PDFInfo
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- CN212627702U CN212627702U CN202021234408.2U CN202021234408U CN212627702U CN 212627702 U CN212627702 U CN 212627702U CN 202021234408 U CN202021234408 U CN 202021234408U CN 212627702 U CN212627702 U CN 212627702U
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Abstract
The utility model discloses a converter and control system thereof. Wherein, this system includes: a master controller, comprising: the main controller is used for generating control information of the frequency converter; and the first microprocessor is connected with the at least one high-speed communication interface and is used for carrying out algorithm control of rectification and inversion on the output voltage of the frequency converter based on the control information. The utility model provides a control harmony of converter is not enough in the correlation technique, leads to the poor technical problem of high-power converter operational effect.
Description
Technical Field
The utility model relates to a high-power converter field of magnetic suspension particularly, relates to a converter and control system thereof.
Background
The magnetic suspension high-power frequency converter is used on a magnetic suspension centrifugal water chilling unit and used for driving a motor. The frequency converter adopts a four-quadrant frequency conversion technology on a hardware topology, and the four-quadrant frequency conversion adopts a fully-controlled rectification topology at a rectification end and an inversion end. The frequency converter can operate in four quadrants corresponding to the I-U (current-voltage) curve, and is therefore called a four quadrant frequency converter.
Because rectification and inversion are full-control rectification topology, a controller is required to provide driving signals at two ends, and then a full-control device IGBT (Insulated Gate Bipolar Transistor) is driven. Therefore, as shown in fig. 1, a PFC (Power Factor Correction) control board, a motor control board and a relay control board are required in the four-quadrant inverter, wherein the PFC board is used for controlling rectification, the motor control board is used for controlling inversion, and the relay control board is used for executing inverter control logic. As shown in fig. 2, communication between the controllers is typically CAN (Controller Area Network) communication or fiber communication. However, due to the limited communication rate, timely transmission of data between boards is difficult to meet, and the control cooperativity of the frequency converter is insufficient; the optical fiber communication has the disadvantages of lack of communication protocol, high cost and the like, and is not suitable for mass use.
In view of the above problems, no effective solution has been proposed.
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model provides a converter and control system thereof to solve the control harmony of converter in the correlation technique not enough at least, lead to the poor technical problem of high-power converter operational effect.
According to the utility model discloses an aspect of the embodiment provides a control system of converter, include: a master controller, comprising: the main controller is used for generating control information of the frequency converter; and the first microprocessor is connected with the at least one high-speed communication interface and is used for carrying out algorithm control of rectification and inversion on the output voltage of the frequency converter based on the control information.
Optionally, the system further comprises: the switching power panel is connected with the main controller and the first microprocessor and used for triggering the main controller and the first microprocessor to be electrified; the high-speed communication interface is used for establishing a communication relation with the first microprocessor which completes initialization.
Optionally, the switching power panel is powered by at least two voltage sources, the voltage sources including: three-phase input power supply and busbar voltage power supply, wherein, main control unit still includes: and the control module is used for controlling the switch power panel to use different voltage sources to supply power based on the bus voltage of the frequency converter.
Optionally, the first microprocessor comprises: the first processing module is used for modulating a first driving signal for carrying out rectification control on a voltage loop and a current loop or a second driving signal for carrying out open-loop inversion modulation or closed-loop inversion modulation on the motor; the signal loading module is used for outputting a first driving signal or a second driving signal; the main controller includes: and the drive protection module is used for logically interlocking the first drive signal or the second drive signal.
Optionally, the driving protection module is configured to disable the output of the driving signal that is at the same high level, and determine whether to allow the level inversion based on detecting a dead time of the driving signal.
Optionally, the system further comprises: the external sampling chip is used for collecting sampling data; a first external memory for storing the sampling data; the high-speed communication interface is also used for receiving a sampling request sent by the first microprocessor; the main controller further includes: the sampling control interface is connected with the external sampling chip and is used for controlling the external sampling chip and receiving sampling data; and the first storage control module is connected with the first external storage and is used for storing the sampling data to the first external storage.
Optionally, the system further comprises: the external protection chip is used for outputting set data corresponding to the sampling data; the comparison circuit is connected with the external protection chip and a drive circuit at the rear stage of the main controller and is used for carrying out output protection control on the drive circuit based on the comparison result of the sampling data and the set data; the main controller further includes: and the protection control interface is connected with the external protection chip and used for controlling the external protection chip.
Optionally, sampling the data comprises: a plurality of analog signals; the main controller further includes: the second processing module is used for dividing the multi-path analog signals into at least one signal set; the system further comprises: the sampling circuit is connected with the second processing module and is used for processing at least one path of analog signal in each signal set; and the comparison circuit is connected with the sampling circuit and used for comparing the target analog signal obtained by the processing with the set analog signal corresponding to the target analog signal.
Optionally, the sampling circuit comprises: a first circuit comprising: the first operational amplifier has a first input end for inputting at least one path of analog signal in each signal set, a second input end for inputting a target analog signal, and an output end connected with the second input end of the first operational amplifier through the first diode; a second circuit comprising: the first input end of the second operational amplifier is grounded, at least one path of analog signal and a target analog signal in each signal set are input to the second input end of the second operational amplifier, and the output end of the second operational amplifier outputs the target analog signal through the second diode.
Optionally, the system further comprises: the upper computer is used for sending transmission data; the main controller includes: a dual-port random access memory; and the second microprocessor is in Ethernet communication connection with the upper computer, is connected with the dual-port random access memory and is used for respectively carrying out data interaction with the main controller and the upper computer.
Optionally, the system further comprises: a second external memory for storing transmission data; the first microprocessor includes: the cache module is used for caching the transmission data forwarded by the second microprocessor; and the second storage control module is connected with the buffer module and the second external storage and is used for transferring the buffered transmission data to the second external storage.
Optionally, the first microprocessor further comprises: and the checking module is connected with the cache module and used for analyzing and checking the transmission data under the condition of receiving the burning instruction sent by the upper computer.
Optionally, the system further comprises: a first external memory; the main controller further includes: the plurality of comparison modules run in parallel, and each comparison module is used for comparing the acquired detection parameters with preset fault parameters; the second processing module is connected with the plurality of comparison modules and used for determining whether the frequency converter has faults or not based on comparison results output by the plurality of comparison modules; the control unit is connected with the second processing module and used for blocking output of interactive data under the condition that the frequency converter fails; and the first storage control module is connected with the first external storage and is used for storing the fault information to the first external storage.
Optionally, the system further comprises: a third external memory for storing the first configuration information; a fourth external memory for storing second configuration information; the data selector is connected with the third external memory and the fourth external memory and is used for acquiring the configuration information stored in the third external memory or the fourth external memory; and the main controller is connected with the data selector and is used for configuring based on the configuration information acquired by the data selector.
According to the utility model discloses on the other hand, still provide a converter, include: the control system of the frequency converter.
The embodiment of the utility model provides an in, main control unit generates the control information of converter to send to at least one first microprocessor through at least one high-speed communication interface, at least one first microprocessor can carry out the algorithm control of rectification and contravariant to the output voltage of converter after receiving control information, thereby realizes the control purpose of high-power converter. Because the converter includes main control unit and at least one first microprocessor to carry out data interaction through high-speed communication interface between main control unit and the first microprocessor, thereby improve the data interaction volume of converter rectification and contravariant end, be convenient for carry out the optimization of algorithm, reached the technical effect who promotes the cooperativity of the operation control of high-power converter, and then solved the control harmony of converter in the correlation technique not enough, lead to the poor technical problem of high-power converter operation effect.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without undue limitation to the invention. In the drawings:
FIG. 1 is a schematic diagram of a magnetically levitated high power frequency converter topology according to the prior art;
FIG. 2 is a schematic diagram of a magnetic levitation high-power frequency converter hardware according to the prior art;
fig. 3 is a schematic diagram of a control system of a frequency converter according to an embodiment of the present invention;
fig. 4a is a schematic diagram of an alternative "one-to-one" uPP high-speed communication connection and data flow between an FPGA and a DSP according to an embodiment of the present invention;
fig. 4b is a schematic diagram of an alternative "one-to-two" uPP high-speed communication connection and data flow between the FPGA and the DSP according to an embodiment of the present invention;
fig. 5 is a schematic diagram of an alternative three-processor master control platform topology according to an embodiment of the present invention;
fig. 6 is a flow chart of power supply switching logic for an alternative switching power panel in accordance with an embodiment of the present invention;
fig. 7 is a flowchart of an alternative power-on timing control within a host platform according to an embodiment of the present invention;
fig. 8 is a schematic diagram of an alternative master control platform software and hardware dual drive signal protection according to an embodiment of the present invention;
fig. 9 is a schematic diagram of an alternative master control platform data sampling and output protection according to an embodiment of the present invention;
fig. 10a is a schematic diagram of an alternative positive half-cycle sampling envelope circuit in accordance with an embodiment of the present invention;
fig. 10b is a schematic diagram of an alternative negative half-cycle sampling envelope circuit in accordance with an embodiment of the present invention;
fig. 11 is a schematic diagram of an alternative absolute value envelope sampling circuit output waveform according to an embodiment of the present invention;
fig. 12 is a schematic diagram of an alternative FPGA mode switching and data observation according to an embodiment of the present invention;
fig. 13 is a flow chart of an alternative DSP remote program burning according to an embodiment of the present invention;
fig. 14 is a flow chart of an alternative master control platform internal fault protection control in accordance with an embodiment of the present invention;
fig. 15 is a schematic diagram of the allocation of functions to processors of an alternative host platform according to an embodiment of the present invention; and
fig. 16 is a flow diagram of an alternative multi-core processing architecture operational timing sequence in accordance with an embodiment of the present invention.
Detailed Description
In order to make the technical solution of the present invention better understood, the technical solution of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts shall belong to the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a system, article, or apparatus that comprises a list of elements is not necessarily limited to those elements explicitly listed, but may include other elements not expressly listed or inherent to such system, article, or apparatus.
According to the embodiment of the utility model provides a control system of converter is provided.
Fig. 3 is a schematic diagram of a control system of a frequency converter according to an embodiment of the present invention, and as shown in fig. 3, the system includes: a main controller 10 and at least one first microprocessor 20 (two shown), the main controller 10 comprising: at least one high-speed communication interface 11, and at least one first microprocessor 20 connected to the at least one high-speed communication interface 11 (one shown).
The main controller 10 is configured to generate control information of the frequency converter; the first microprocessor 20 is used for performing algorithm control of rectification and inversion of the output voltage of the frequency converter based on the control information.
The frequency converter may be a magnetic levitation high-power frequency converter, but is not limited thereto. The main controller may be an FPGA (Field-Programmable Gate Array), and is mainly responsible for logic control, fault protection control, analog sampling control, operation data storage control, driving signal detection control, and the like of the frequency converter. The first microprocessor may be a DSP (Digital Signal Processing), and is mainly responsible for algorithm control of rectification and inversion.
In an optional embodiment, an FPGA + DSP architecture can be adopted, one DSP controls rectification and the other DSP controls inversion, and the FPGA can be used as an upper computer of the two to cooperatively control the algorithm operation of the DSP.
The high-speed communication interface can be a Universal Parallel Port (uPP), uPP communication is a high-speed external communication interface protocol, the address line is cancelled, the data transmission speed is increased, and the maximum speed can reach 70 MHz.
In an alternative embodiment, a one-to-one mode can be adopted, and a general uPP communication protocol interface is constructed in the FPGA, that is, only one uPP control module can realize communication control between one FPGA and one DSP. As shown in fig. 4a, for two DSPs, two uPP control modules may be built in the FPGA, each uPP control module performs data interaction with the uPP control module in the DSP through uPP channels, and the uPP control module in the FPGA may perform data interaction with the FPGA through an internal data channel of the FPGA.
However, the data of communication needs to enter the row and column communication links of the FPGA to complete the data interaction of rectification and inversion, thereby realizing the cooperative control of rectification and inversion. Compared with CAN communication between control panels, the cooperative work of rectification and inversion CAN be improved to a greater extent.
In an alternative embodiment, the uPP control module may be optimized for improved interoperability to a "one-to-many" mode. As shown in fig. 4b, for two DSPs, an uPP control module may be constructed in the FPGA, and the data interaction is performed with the uPP control module in the two DSPs through the uPP channel, and with the data interaction in the FPGA through the internal data channel of the FPGA.
Through the scheme, data interaction of rectification and inversion can be realized in the uPP control module, the pressure of data transmission in the FPGA is reduced, and the uPP control module in a one-to-many mode can realize synchronous control of rectification and inversion, namely the same clock control signal is adopted, so that the control cooperativity of rectification and inversion is further improved.
The control information can be logic control information of the frequency converter, and controls the DSP to generate driving signals of the full-control rectifier bridge and the full-control inverter bridge.
In an optional embodiment, three controllers, namely a PFC board, a motor board and a relay board, may be combined into one controller to obtain a three-processor main control platform, and the three-processor main control platform may perform rectification modulation and driving, inversion modulation and driving, frequency converter operation logic control, communication control, and the like at the same time. The main control platform can adopt an FPGA + DSP architecture, uPP communication is used between the FPGA and the DSP to replace EMIF (External Memory Interface) communication, and therefore the cooperative work of rectification and inversion is improved to a large extent.
Through the utility model discloses above-mentioned embodiment, main control unit generates the control information of converter to send to at least one first microprocessor through at least one high-speed communication interface, at least one first microprocessor can carry out the algorithm control of rectification and contravariant to the output voltage of converter after receiving control information, thereby realizes the control purpose of high-power converter. Because the converter includes main control unit and at least one first microprocessor to carry out data interaction through high-speed communication interface between main control unit and the first microprocessor, thereby improve the data interaction volume of converter rectification and contravariant end, be convenient for carry out the optimization of algorithm, reached the technical effect who promotes the cooperativity of the operation control of high-power converter, and then solved the control harmony of converter in the correlation technique not enough, lead to the poor technical problem of high-power converter operation effect.
In the above embodiments of the present invention, as shown in fig. 3, the system further includes: and a switching power supply board 30, wherein the switching power supply board 30 is connected with the main controller 10 and the first microprocessor 20.
The switching power panel 30 is used for triggering the main controller and the first microprocessor to be powered on; the high-speed communication interface 11 is used to establish a communication relationship with the first microprocessor 20 that completes the initialization.
Optionally, the switching power panel is powered by at least two voltage sources, the voltage sources including: three-phase input power supply and busbar voltage power supply, wherein, main control unit still includes: and the control module is used for controlling the switch power panel to use different voltage sources to supply power based on the bus voltage of the frequency converter.
Further, when the bus voltage is lower than the preset voltage, the three-phase input end is adopted for supplying power, and when the bus voltage is higher than the preset voltage, the bus voltage is adopted for supplying power. The preset voltage may be 470V, but is not limited thereto, and may be set according to actual needs.
In an alternative embodiment, as shown in fig. 5, the three-processor master control platform provides driving signals to the fully-controlled rectifier bridge and the fully-controlled inverter bridge simultaneously, and the 24V power supply of the master control platform is provided by the switching power panel. The switch power panel is provided with input by two parts of voltage sources, namely, a certain two phases (such as V and W) of a three-phase input end of the frequency converter, and the other two phases are provided by bus voltage of the frequency converter. As shown in fig. 6, after the frequency converter starts to be powered on, the switching power panel is powered by the three-phase input, the main control platform is triggered to be powered on, the main control platform controls the frequency converter to enter a charging state, then the bus voltage is judged, and when the bus voltage is lower than 470V, the three-phase input continues to supply power; when the bus voltage is higher than 470V, the power is supplied by the bus voltage.
By optimizing the topological structure of the frequency converter, the power supply logic of the switching power panel is reconstructed, and the adaptability between the master control platform and the frequency converter is improved.
In the above embodiments of the present invention, the switching power supply board is further configured to obtain voltage levels of the main controller and the first microprocessor; and controlling power supply enabling signals on the main controller and the first microprocessor according to the sequence of the voltage grades to trigger the main controller and the first microprocessor to be powered on.
At the instant the main controller and the first microprocessor are powered on, the main controller and the first microprocessor are in an unknown uncontrollable state. Because the designed voltage levels in the controller are more, for example, the voltage levels of 24V, 15V, ± 15V, 5V, 3.3V and 1.2V, when level conversion is performed on the voltages step by step, the voltage establishment time of different voltage levels is different, and the sequence is difficult to grasp, so that signals in uncertain states are generated or error signals are acquired, and certain potential safety hazards are caused for a high-power frequency converter. In an optional embodiment, the power-on control logic of the main control platform can be established in the FPGA, and the main controller and the first microprocessor are sub-modularized to establish a power-on time sequence by controlling enable signals of power supplies on the main controller and the first microprocessor, so that all power supply signals are always in a controllable state in the power-on process of the main controller and the first microprocessor, thereby eliminating potential safety hazards in the power-on process of the main controller and the first microprocessor and ensuring that the power-on of the main control platform is in the controllable state.
For example, as shown in fig. 7, after the main control platform is powered on, the control digital area 5V is powered on, the FPGA core is powered on at 1.2V, whether the initialization of the FPGA is completed is further determined, if the initialization of the FPGA is not completed, the initialization of the FPGA is waited to be completed, then the FPGA I/O3.3V is powered on, the DSP and the ARM are powered on, then whether the initialization of the DSP and the ARM is completed and the connection with the FPGA is established is determined, if the initialization of the DSP and the ARM is not completed, or the DSP and the ARM are not connected with the FPGA, the initialization of the FPGA is waited to be completed and the connection with the FPGA is established, then ± 15V power on is simulated sampling.
In the above embodiments of the present invention, the first microprocessor includes: first processing module and signal load module, main controller includes: and driving the protection module.
The first processing module is used for modulating a first driving signal for rectifying and controlling a voltage loop and a current loop, or modulating a second driving signal for performing open-loop inversion modulation or closed-loop inversion modulation on the motor; the signal loading module is used for outputting a first driving signal or a second driving signal; the drive protection module is used for logically interlocking the first drive signal or the second drive signal.
The first driving signal and the second driving signal may be PWM (Pulse Width Modulation) signals, and the full-controlled rectifier bridge and the full-controlled inverter bridge may be controlled by the PWM signals.
In an alternative embodiment, the DSP1 is controlled to enter a commutation control algorithm when the FPGA receives a start command. The algorithm of the DSP1 modulates the output PWM signal, and outputs the PWM signal to a driving circuit at the rear stage of the main controller through the internal logic interlock of the FPGA. After the FPGA receives a starting instruction, controlling the DSP2 to enter an inversion control algorithm; the DSP2 performs open-loop modulation on the motor, drags the motor to rotate, and switches into closed-loop algorithm modulation when analog data acquisition can be performed. The algorithm of the DSP2 modulates the output PWM signal, and outputs the PWM signal to a driving circuit at the rear stage of the main controller through the internal logic interlock of the FPGA.
In the above embodiments of the present invention, the driving protection module is configured to prohibit the output of the driving signal that is at the high level, and determine whether to allow the level inversion based on the dead time of the detection driving signal.
In order to prevent the PWM driving signal from going straight through up and down, in an alternative embodiment, a software and hardware dual anti-straight-through protection design may be designed. As shown in fig. 8, the DSP is an algorithm control core of the main control platform, the algorithm modulation of rectification and inversion is implemented in the DSP, and the PWM signal is also generated in the DSP. After the PWM signal is generated, the PWM signal enters a driving protection module in the FPGA, and the driving protection module prohibits the upper driving signal and the lower driving signal from being output as high-level signals by comparing the driving signals of the upper pipe and the lower pipe; and the dead time of the PWM signal is detected, and the level inversion is allowed only if the dead time of 2us is met. And simultaneously, the driving protection module is enabled by the fault protection signal. When the fault protection module acts, the drive protection module enables interruption, and the resistance value PWM drives the later-stage transmission of signals. The rear stage of the FPGA is a driving and logic circuit, and the driving circuit is used for increasing the driving current of the PWM signal; the logic circuit is designed for hardware anti-shoot-through protection. And the PWM driving signal is connected to a driving board at the rear stage, and the driving board is used for driving a gate pole of the full-control device so as to control the on-off of the full-control device.
In the above embodiments of the present invention, as shown in fig. 3, the system further includes: an external sampling chip 40 and a first external memory 50, the main controller 10 further comprising: the sampling control interface 12 is connected with the external sampling chip 40, and the first storage control module 13 is connected with the first external memory 50.
The external sampling chip 40 is used for collecting sampling data; the first external memory 50 is used for storing sample data; the high-speed communication interface 11 is also used for receiving a sampling request sent by the first microprocessor 20; the sampling control interface 12 is used for controlling the external sampling chip 40 and receiving sampling data; the first storage control module 13 is configured to store the sample data in the first external memory 50.
The sampling request may be an analog data sampling request. The external sampling chip can be an external AD (Analog-to-Digital) sampling chip, has the characteristics of high speed and high parallelism, and can restore Analog signal data to the maximum extent. The first external memory may be NAND FLASH, but is not limited thereto.
In an alternative embodiment, when analog data acquisition is required, the DSP may send a sampling request to the FPGA for analog sampling. As shown in fig. 9, an AD control module may be constructed in the FPGA to control an external AD chip to perform sampling, and data acquired by the analog sampling interface is acquired by the AD chip and returned to the FPGA after passing through the filter circuit and the amplifier circuit, where a parallel bus and a serial bus are provided between the AD chip and the FPGA. The FPGA can transmit the data to the DSP through an uPP bus and store the data with high sampling precision into NAND FLASH, so that later data observation and problem analysis are facilitated.
It should be noted that, limited by the dominant frequency of the DSP, the data points participating in the calculation in each period of the algorithm modulation are limited. Therefore, the AD sampling clock and the DSP algorithm modulation clock are separated, and the AD sampling clock is larger than the DSP algorithm modulation clock, so that the precision requirement of restoring the running data is met, and the operation requirement of algorithm modulation is also met.
In the above embodiment of the present invention, the system includes: external protection chip and comparison circuit, main controller still includes: and the comparison circuit is connected with an external protection chip and a drive circuit at the rear stage of the main controller, and the protection control interface is connected with the external protection chip.
The external protection chip is used for outputting set data corresponding to the sampling data; the comparison circuit is used for carrying out output protection control on the drive circuit based on the comparison result of the sampling data and the set data; the protection control interface is used for controlling the external protection chip.
The setting data may be a preset sampling protection value, and different protection values are set for different sampling requirements.
In an alternative embodiment, as shown in fig. 9, a DA (Digital-to-Analog) control module may be built in the FPGA, and the DA control module controls an external DA chip to output the sampling protection value to the comparison circuit, where a parallel bus and a serial bus are disposed between the AD chip and the FPGA. The sampling value and the protection value are compared through the comparison circuit, so that the output protection function of the driving and wave shaping circuit is realized, and the precision, the reconfigurability and the speed of protection action of sampling protection are improved.
In the above embodiments of the present invention, the sampling data includes: multichannel analog signal, main controller still includes: a second processing module, the system further comprising: and the sampling circuit is connected with the second processing module, and the comparison circuit is connected with the sampling circuit.
The second processing module is used for dividing the multi-path analog signals into at least one signal set; the sampling circuit is used for processing at least one path of analog signal in each signal set; the comparison circuit is used for comparing the target analog signal obtained by the processing with a set analog signal corresponding to the target analog signal.
The sampling circuit can be an absolute value envelope sampling circuit and is used for sampling a maximum value curve for protection. The absolute value envelope sampling circuit may be specifically divided into a positive half-cycle envelope (as shown in fig. 10 a) and a negative half-cycle envelope circuit (as shown in fig. 10 b), and may form a negative feedback loop through a diode by using an operational amplifier, and make V by using the single-phase conduction characteristic of the diodeOUTIs equal to or slightly less than VINMaximum absolute value, only the feedback diode of the path is on, the diodes of the other paths are all in reverse cut-off, VOUTIs shown as a solid line in fig. 11.
It should be noted that the large-power frequency converter needs to collect more analog signals, and the analog signals may include: 6-12 paths of current signals, 6-12 paths of voltage signals, 6-12 paths of temperature signals and the like. If the hardware protection design is performed on each path of analog signal, a large hardware resource pressure is caused. In an optional embodiment, for the analog signals of the same type and having the same protection value, the maximum value curve can be obtained through the absolute value envelope sampling circuit for protection, so that the wiring difficulty is simplified, the resource requirement is reduced, and the fault observation is facilitated.
In the above embodiment of the present invention, the sampling circuit includes: a first circuit comprising: the first operational amplifier has a first input end for inputting at least one path of analog signal in each signal set, a second input end for inputting a target analog signal, and an output end connected with the second input end of the first operational amplifier through the first diode; a second circuit comprising: the first input end of the second operational amplifier is grounded, at least one path of analog signal and a target analog signal in each signal set are input to the second input end of the second operational amplifier, and the output end of the second operational amplifier outputs the target analog signal through the second diode.
The first circuit described above may be as shown in fig. 10a and the second circuit may be as shown in fig. 10b, wherein the first and second operational amplifiers are connected to +15V and-15V voltages and are connected in series with a resistor R1 and a resistor R2 before the input terminals of the first and second operational amplifiers, respectively.
In the above embodiments of the present invention, as shown in fig. 3, the system further includes: host computer 60 and second microprocessor 70, main controller 10 includes: the dual-port random access memory 14 and the second microprocessor 70 are connected with the upper computer 60 in an Ethernet communication mode and are connected with the dual-port random access memory 14.
The upper computer 60 is configured to send transmission data; the second microprocessor 70 is used for data interaction with the main controller 10 and the upper computer 60 respectively.
Foretell host computer can be to the converter monitor, program burn record computer terminal, mobile terminal etc. of waiting, the utility model discloses do not specifically limit to this. The second microprocessor may be an arm (advanced riscmachines) processor, but is not limited thereto. The ARM processor is mainly responsible for communication control with an upper computer, and various external communication functions can be realized by utilizing a communication module built in the ARM.
In an alternative embodiment, as shown in fig. 12, a dual-port RAM (Random Access Memory) may be constructed on the FPGA to implement high-speed parallel communication with the ARM, and the ARM performs communication control of the frequency converter and implements data interaction with the upper computer through the ethernet. Through Ethernet communication, the remote burning and historical data online observation functions of the DSP algorithm program are realized.
It should be noted that, as shown in fig. 12, in order to implement access to the operation history data of the frequency converter, an NAND FLASH controller may be built on the FPGA, and the NAND FLASH controller controls the external NAND FLASH memory to store and read the history data, so that high-speed and high-density data storage may be implemented, and sufficient data for troubleshooting and status observation of the frequency converter is provided.
In the above embodiments of the present invention, as shown in fig. 3, the system further includes: the second external memory 80, the first microprocessor 20 includes: the cache module 21 and the second storage control module 22, and the second storage control module 22 is connected to the cache module 21 and the second external memory 80.
Wherein, the second external memory 80 is used for storing the transmission data; the buffer module 21 is configured to buffer the transmission data forwarded by the second microprocessor 70; the second memory control module 22 is used for unloading the buffered transmission data into the second external memory 80.
The second external memory may be an external NOR FLASH connected to the DSP, but is not limited thereto.
It should be noted that most DSP programs of the frequency converter are burned through JTAG (Joint Test Action Group), but in applications such as testing and after-sales, burning programs through the simulator has the disadvantages of poor convenience and low security.
In an alternative embodiment, the DSP running program may be guided by an external memory NOR FLASH, that is, after being powered on, the DSP reads the program code of the external memory to complete the program importing work of the DSP itself. Therefore, the program can be changed only by rewriting the data in the external memory. The process of implementing program remote burning through the external network is shown in fig. 13, after the program remote burning is started, the DSP can configure ethernet information, after the DSP establishes the connection of the hardware bottom layer of the ethernet communication with the upper computer, the upper computer transmits the compiled DSP program code to the data cache area inside the DSP through the ethernet, and the DSP then transfers the program data to the address of the corresponding start program of the external memory. After the program is recorded into the external memory, the DSP can read in the new program in the external memory only by powering off the DSP again and then powering on the DSP, thereby realizing the program updating of the DSP. Through Ethernet communication, the remote updating function of the frequency converter program is realized, and the portability of experimental testing and after-sales maintenance is improved.
In the above embodiments of the present invention, the first microprocessor further includes: and the checking module is connected with the cache module.
The verification module is used for analyzing and verifying the transmission data under the condition of receiving the burning instruction sent by the upper computer.
In an alternative embodiment, as shown in fig. 13, after receiving the burning command sent by the upper computer, data analysis and verification may be performed, and if the verification is successful, the burning program is written into the NOR FLASH until the burning of the program is completed, and then the remote burning of the program is completed.
Alternatively, the master controller may provide a communication path between different microprocessors, wherein the different microprocessors use the communication path for direct information exchange.
In an optional embodiment, by using the programmable logic characteristics of the FPGA, a high-speed bottom layer interface, such as an AD control interface, an uPP high-speed communication interface, a dual-port RAM, etc., can be constructed, so that the DSPs can communicate with each other quickly through a uPP high-speed communication bottom layer channel of the FPGA, thereby realizing quick information interaction between the DSPs, realizing higher-cooperativity rectification inversion control, and avoiding a frequency converter system fault caused by modulation time difference between the two; the DSP and the ARM can realize information interaction through an uPP high-speed communication bottom layer path of the FPGA and a double-port RAM bottom layer path.
In the above embodiment of the present invention, the system further includes: a first external memory; the main controller further includes: the device comprises a plurality of comparison modules, a second processing module, a control unit and a first storage control module, wherein the comparison modules run in parallel, the second processing module is connected with the control unit and the comparison modules, and the first storage control module is connected with a first external storage.
Each comparison module is used for comparing the acquired detection parameters with preset fault parameters; the second processing module is connected with the plurality of comparison modules and used for determining whether the frequency converter has faults or not based on comparison results output by the plurality of comparison modules; the control unit is used for blocking output interactive data under the condition that the frequency converter fails; the first storage control module is used for storing the fault information to a first external memory.
The above-mentioned detection parameters may be, but are not limited to, current, voltage, temperature, communication, and the like as shown in fig. 14.
Fault protection is implemented in microprocessors (e.g., DSPs, ARM) requiring round-robin access to fault protection conditions, i.e., through serial processing. However, in the above serial processing mode, when the number of fail-safe conditions increases, more clock cycles are consumed, which affects the timeliness of protection. Due to the characteristics of the FPGA, the high parallelism of the processing data of the FPGA can be realized, and the application with small calculation amount and high repeatability can be realized. Therefore in the embodiment of the utility model provides an in, can realize the fault protection logic of converter through FPGA, guarantee the fault protection's of converter instantaneity. The comparison module (such as the comparison circuit shown in fig. 9) of various fault protection values is constructed through hardware programming, and when a fault occurs, the output of the relevant control unit in the FPGA can be quickly blocked by controlling the enable or clear signal of the control unit in the FPGA, so that the fault protection function with higher real-time performance is realized. In addition, the fault data information can be stored in the external NAND FLASH, so that subsequent checking and maintenance are facilitated, the frequency converter is informed to stop, and the purpose of fault stop is achieved.
Optionally, when the bus voltage of the frequency converter reaches a set threshold, the fault detection function of the main controller is controlled to be in an enabled state, and if the frequency converter is detected to have a fault, the standby starting state is returned.
The set threshold may be 670V, but is not limited thereto.
In an optional embodiment, the bus voltage is maintained at 670V in the normal working state of the frequency converter, and the switching power supply board is powered by the bus, so that the condition of sudden power loss of the main control platform during emergency shutdown or power failure can be avoided, and further energy feedback is realized. In addition, when the fault detection logic (i.e. the above-mentioned fault detection function) is always in the enabled state, when any sampling value exceeds the protection value, it indicates that the frequency converter is in fault, and can trigger the frequency converter to return to the standby starting state.
In the above embodiment of the present invention, the system further includes: the data selector is connected with the third external memory, the fourth external memory and the main controller.
The third external memory is used for storing the first configuration information; the fourth external memory is used for storing the second configuration information; the data selector is used for acquiring the configuration information stored in the third external memory or the fourth external memory; the main controller is used for configuring based on the configuration information acquired by the data selector.
The third external memory and the fourth external memory may be two pieces of NOR FLASH as configuration chips of the FPGA, but are not limited thereto. Different programs can be stored in the third external memory and the fourth external memory, for example, a product program is written in the third external memory, an experimental test program is written in the fourth external memory, wherein the product program does not include functions of reading the running data of the frequency converter, debugging parameters and the like; and the debugging program can realize the functions of reading NAND FLASH the operation history data of the frequency converter, debugging parameters and the like. The data selector may be a two-way selector, connected to the third external memory and the fourth external memory, and may select from the two external memories.
Because the characteristics of the FPGA device are programmable and reconfigurable, the FPGA can configure internal logic resources when being electrified every time, and the logic disappears after the power is off. On the basis, the FPGA can carry out power-on logic resource configuration through the external memory. In an alternative embodiment, as shown in fig. 12, two pieces of NOR FLASH may be provided as a configuration chip of the FPGA, and the FPGA may be configured differently through one data selector, so as to implement convenience of debugging, implement flexible switching of operation modes of the FPGA, and effectively increase information security performance of the frequency converter.
A preferred embodiment of the present invention will be described in detail with reference to fig. 15 and 16, and the three controllers of the PFC board, the motor board and the relay board can be combined into one controller, that is, a three-processor main control platform, which is built with the architecture of the three types of processors, namely FPGA + DSP + ARM, and is formed with the peripheral circuit.
As shown in fig. 15, the main control platform uses the FPGA as a main control core and is mainly responsible for logic control, fault protection control, analog sampling control, operation data storage control, drive signal detection control, and the like of the frequency converter; the DSP is mainly responsible for algorithm control of rectification and inversion; the ARM is mainly responsible for communication control with an upper computer. Constructing a high-speed bottom layer interface such as an AD (analog-to-digital) control interface and a 'one-to-two' uPP high-speed communication interface by utilizing the programmable logic characteristic of the FPGA; and through the characteristic of high parallelism, the construction of logic protection and a comprehensive state machine is realized, including the relay control and electric shock feedback detection for controlling the starting and state switching of the frequency converter, and the time sequence control of bottom layer interfaces of each part, communication control, storage control and the like. The high-speed computing capability of the digital signals in the DSP is utilized, and the realization of executing the control algorithm is focused. When a closed-loop algorithm program is triggered, the DSP sends a sampling data request through the EPWM-SOCA, and an AD control interface of the FPGA feeds back sampling data through a one-to-two uPP high-speed communication interface. The sampling data is returned to trigger the internal interruption of the DSP, high-speed algorithm modulation operation is carried out by using the data, and PWM signal output is realized through a PWM signal loading module. A plurality of communication functions outside the network are realized by utilizing rich communication modules built in the ARM, and the network communication between the ARM and the FPGA realizes high-speed information interaction between two processors by using a dual-port RAM built in the common FPGA.
The flow chart of the working timing of the main control core (FPGA), the algorithm core (DSP) and the communication core (ARM) is shown in fig. 16. After the frequency converter is electrified, the controller is supplied with power through the switching power panel, and the electrification logic of the controller is triggered. After the power-on is finished, the FPGA inquires whether normal communication is established between the DSP and the ARM. After normal communication is established among the processors, all logic control modules including frequency converter state control logic, AD sampling control, FLASH storage control and the like are synchronously started in the FPGA. And when the bus voltage reaches a set threshold value, entering switching logic of the switching power panel. Thus, the standby starting state of the frequency converter is realized. The fault detection logic is always in an enabling state, and when any sampling value exceeds a set threshold value, the standby starting state is started. And after the FPGA receives the starting instruction, the DSP1 is controlled to enter a rectification control algorithm. The DSP1 requests analog sample data from the FPGA through uPP high speed communications. And the PWM signal output by the algorithm modulation is output to a drive circuit at the rear stage of the controller through logic interlocking in the FPGA. After the FPGA receives a starting instruction, controlling the DSP2 to enter an inversion control algorithm; the DSP2 performs open-loop modulation on the motor, drags the motor to rotate, and switches into closed-loop algorithm modulation when analog data acquisition can be performed. The DSP2 requests analog sample data from the FPGA through uPP high speed communications. And the PWM signal output by the algorithm modulation is output to a drive circuit at the rear stage of the controller through logic interlocking in the FPGA. The DSP1 and the DSP2 can realize rapid information interaction between the two DSPs through a uPP high-speed communication bottom layer channel of the FPGA, can realize rectification inversion control with higher cooperativity, and avoids the frequency converter system fault caused by the modulation time difference of the two DSPs. And after the ARM completes initialization, waiting for a network connection establishment request of the upper computer. After the connection with the upper computer is established, the ARM performs data interaction to the FPGA and transmits the returned information to the upper computer platform through network communication.
By the scheme, the problems of communication delay and limitation of communication data quantity between four-quadrant frequency converters are solved by using an FPGA, DSP and ARM three-processor architecture, and the cooperativity of operation control is improved; by adding a large-capacity data storage chip and an Ethernet communication function, the portability of troubleshooting and frequency converter debugging is solved; through the programmability and reconfigurability of the FPGA and rich interfaces and internal resources of the ARM and the DSP, a hardware basis for function optimization and expansion is provided for the controller; by improving the hardware architecture and design, the performance and reliability of the frequency converter are improved from the links of data acquisition, data processing, data transmission and the like.
According to the utility model discloses the embodiment still provides a converter, include: the control system of the frequency converter.
The frequency converter may be a magnetic levitation high-power frequency converter, but is not limited thereto.
Through the utility model discloses above-mentioned embodiment, main control unit generates the control information of converter to send to at least one first microprocessor through at least one high-speed communication interface, at least one first microprocessor can carry out the algorithm control of rectification and contravariant to the output voltage of converter after receiving control information, thereby realizes the control purpose of high-power converter. Because the frequency converter includes main control unit and at least one first microprocessor to carry out data interaction through high-speed communication interface between main control unit and the first microprocessor, thereby improve the data interaction volume of frequency converter rectification and contravariant end, be convenient for carry out the optimization of algorithm, reached the cooperativity that promotes the operation control of high-power frequency converter, and then solved the control harmony of frequency converter in the correlation technique not enough, lead to the poor technical problem of high-power frequency converter operation effect.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (13)
1. A control system for a frequency converter, comprising:
a master controller, comprising: the main controller is used for generating control information of the frequency converter;
the first microprocessor is connected with the at least one high-speed communication interface and used for carrying out rectification and inversion algorithm control on the output voltage of the frequency converter based on the control information;
wherein the system further comprises: the switching power panel is connected with the main controller and the first microprocessor and used for triggering the main controller and the first microprocessor to be electrified;
the high-speed communication interface is used for establishing a communication relation with the first microprocessor which completes initialization;
the switching power panel is powered by at least two voltage sources, the voltage sources including: three-phase input power supply and busbar voltage power supply, wherein, main controller still includes:
and the control module is used for controlling the switching power panel to supply power by using different voltage sources based on the bus voltage of the frequency converter.
2. The system of claim 1,
the first microprocessor includes: the first processing module is used for modulating a first driving signal for carrying out rectification control on a voltage loop and a current loop or a second driving signal for carrying out open-loop inversion modulation or closed-loop inversion modulation on the motor;
the signal loading module is used for outputting the first driving signal or the second driving signal;
the main controller includes: and the drive protection module is used for carrying out logic interlocking on the first drive signal or the second drive signal.
3. The system of claim 2,
and the drive protection module is used for forbidding the output of the drive signal with the same high level and determining whether the level inversion is allowed or not based on the dead time for detecting the drive signal.
4. The system of claim 1,
the system further comprises: the external sampling chip is used for collecting sampling data;
a first external memory for storing the sampling data;
the high-speed communication interface is also used for receiving a sampling request sent by the first microprocessor;
the main controller further includes: the sampling control interface is connected with the external sampling chip and used for controlling the external sampling chip and receiving the sampling data;
and the first storage control module is connected with the first external storage and is used for storing the sampling data to the first external storage.
5. The system of claim 4,
the system further comprises: the external protection chip is used for outputting the set data corresponding to the sampling data;
the comparison circuit is connected with the external protection chip and a drive circuit at the rear stage of the main controller and is used for carrying out output protection control on the drive circuit based on the comparison result of the sampling data and the set data;
the main controller further includes: and the protection control interface is connected with the external protection chip and used for controlling the external protection chip.
6. The system of claim 5, wherein the sampled data comprises: a plurality of analog signals;
the main controller further includes: the second processing module is used for dividing the multi-path analog signals into at least one signal set;
the system further comprises: the sampling circuit is connected with the second processing module and is used for processing at least one path of analog signal in each signal set;
the comparison circuit is connected with the sampling circuit and used for comparing the target analog signal obtained by processing with the set analog signal corresponding to the target analog signal.
7. The system of claim 6, wherein the sampling circuit comprises:
a first circuit comprising: the first input end of the first operational amplifier inputs at least one path of analog signal in each signal set, the second input end of the first operational amplifier inputs the target analog signal, and the output end of the first operational amplifier is connected with the second input end of the first operational amplifier through the first diode;
a second circuit comprising: the first input end of the second operational amplifier is grounded, the second input end of the second operational amplifier inputs at least one path of analog signal in each signal set and the target analog signal, and the output end of the second operational amplifier outputs the target analog signal through the second diode.
8. The system of claim 1, further comprising:
the upper computer is used for sending transmission data;
the main controller includes: a dual-port random access memory;
and the second microprocessor is in Ethernet communication connection with the upper computer, is connected with the dual-port random access memory and is used for respectively carrying out data interaction with the main controller and the upper computer.
9. The system of claim 8,
the system further comprises: a second external memory for storing the transmission data;
the first microprocessor includes: a buffer module for buffering the transmission data forwarded via the second microprocessor;
and the second storage control module is connected with the cache module and the second external storage and is used for transferring the cached transmission data to the second external storage.
10. The system of claim 9, wherein the first microprocessor further comprises:
and the checking module is connected with the cache module and used for analyzing and checking the transmission data under the condition of receiving the burning instruction sent by the upper computer.
11. The system of claim 1,
the system further comprises: a first external memory;
the main controller further includes: the system comprises a plurality of comparison modules, a plurality of detection modules and a plurality of fault detection modules, wherein the comparison modules run in parallel, and each comparison module is used for comparing an acquired detection parameter with a preset fault parameter;
the second processing module is connected with the plurality of comparison modules and used for determining whether the frequency converter has faults or not based on comparison results output by the plurality of comparison modules;
the control unit is connected with the second processing module and used for blocking output of interactive data under the condition that the frequency converter fails;
and the first storage control module is connected with the first external storage and is used for storing the fault information to the first external storage.
12. The system of claim 1, further comprising:
a third external memory for storing the first configuration information;
a fourth external memory for storing second configuration information;
a data selector, connected to the third external memory and the fourth external memory, for acquiring configuration information stored in the third external memory or the fourth external memory;
and the main controller is connected with the data selector and is used for configuring based on the configuration information acquired by the data selector.
13. A frequency converter, comprising: a control system for a frequency converter according to any one of claims 1 to 12.
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| CN116107261A (en) * | 2023-04-12 | 2023-05-12 | 天津市伟利达科技发展有限公司 | Control method and system of frequency converter |
| CN116107261B (en) * | 2023-04-12 | 2023-06-13 | 天津市伟利达科技发展有限公司 | Control method and system of frequency converter |
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