CN212572418U

CN212572418U - Full-bridge inverter circuit

Info

Publication number: CN212572418U
Application number: CN202021549423.6U
Authority: CN
Inventors: 马承
Original assignee: Wuhan Handewell Electric Technology Co ltd
Current assignee: Wuhan Handewell Electric Technology Co ltd
Priority date: 2020-07-30
Filing date: 2020-07-30
Publication date: 2021-02-19
Anticipated expiration: 2030-07-30

Abstract

The utility model provides a full-bridge inverter circuit, include the dc-to-ac converter that comprises MOS pipe S1 ~ S4, MOS pipe S1 constitutes first bridge arm with MOS pipe S2, and MOS pipe S3 constitutes the second bridge arm with MOS pipe S4, full-bridge inverter circuit still includes inductance L1, resistance R1 and electric capacity C1 ~ C5. The middle point of the first bridge arm is connected with the middle point of the second bridge arm through a resistor R1, an inductor L1 and a capacitor C5 which are connected in series in sequence, the capacitor C1 is connected with the MOS tube S1 in parallel, the capacitor C2 is connected with the MOS tube S2 in parallel, the capacitor C3 is connected with the MOS tube S3 in parallel, and the capacitor C4 is connected with the MOS tube S4 in parallel. The utility model discloses a parallel resonance electric capacity and at output series connection LCR resonant circuit on every MOS pipe of dc-to-ac converter, the resonance through the circuit has realized that the zero voltage of switch tube switches on and close zero voltage and turn-offs, very big reduction the switching loss of dc-to-ac converter.

Description

Full-bridge inverter circuit

Technical Field

The utility model relates to an inverter circuit technical field especially relates to a full-bridge inverter circuit.

Background

In the application occasions of medium and small power, the full-bridge inverter circuit is widely used due to the simple structure, few power devices and small voltage stress borne by the power tube. The full-bridge inverter circuit is used for inverting the direct current input into alternating current output, the four switching tubes are core devices of the full-bridge inverter circuit, and the inversion of the voltage is realized by controlling the four switching tubes to be conducted in turn. In a traditional full-bridge inverter circuit, a switch tube usually adopts a hard switching mode, and the switching loss of the switch tube is large.

SUMMERY OF THE UTILITY MODEL

In view of this the utility model provides a full-bridge inverter circuit to solve traditional full-bridge inverter and adopt the hard switching mode to lead to the big problem of switching loss.

The technical scheme of the utility model is realized like this: a full-bridge inverter circuit comprises an inverter formed by MOS tubes S1-S4, a first bridge arm formed by MOS tubes S1 and S2, a second bridge arm formed by MOS tubes S3 and S4, an inductor L1, a resistor R1 and capacitors C1-C5;

the middle point of the first bridge arm is connected with the middle point of the second bridge arm through a resistor R1, an inductor L1 and a capacitor C5 which are connected in series in sequence, the capacitor C1 is connected with the MOS tube S1 in parallel, the capacitor C2 is connected with the MOS tube S2 in parallel, the capacitor C3 is connected with the MOS tube S3 in parallel, and the capacitor C4 is connected with the MOS tube S4 in parallel.

Optionally, the full-bridge inverter circuit further includes an SG3524 chip, a potentiometer R5, a potentiometer R6, and an optocoupler isolator;

no. 6 pin of SG3524 chip is connected with the middle end of potentiometre R5, the one end ground connection of potentiometre R5, the other end of potentiometre R5 is unsettled, No. 2 pin of SG3524 chip is connected with the middle end of potentiometre R6, No. 16 pin of SG3524 chip is through potentiometre R6 ground connection, No. 9 pin of SG3524 chip is connected with MOS pipe S1, the grid of MOS pipe S4 respectively through the opto-coupler isolator, No. 14 pin of SG3524 chip is connected with MOS pipe S2, the grid of MOS pipe S3 respectively through the opto-coupler isolator.

Optionally, the full-bridge inverter circuit further includes an ACS712 chip, a comparator, a resistor R7, and a JK flip-flop;

an IP + pin of the ACS712 chip is connected with the midpoint of the first bridge arm, an IP-pin is connected with the midpoint of the second bridge arm, a VIOUT pin is connected with an inverting input end of a comparator, a non-inverting input end of the comparator is connected with a reference voltage, an output end of the comparator is connected with a CLK end of the JK trigger through a resistor R7, a common end of the resistor R7 and the CLK end of the JK trigger is connected with a power supply VCC, and a J end and an R end of the JK trigger are respectively connected with the power supply VCC.

Optionally, the comparator is model LM 339.

Optionally, the full-bridge inverter circuit further includes a capacitor C6, and the capacitor C6 is connected between a common terminal of the resistor R7-JK flip-flop CLK terminal and the power supply VCC.

Optionally, the full-bridge inverter circuit further includes a resistor R8, and the resistor R8 is connected in series between the power VCC and the R terminal of the JK flip-flop.

Optionally, the full-bridge inverter circuit further includes a capacitor C7, and a common terminal between the resistor R8 and the end R of the JK flip-flop is grounded via the capacitor C7.

The utility model discloses a full-bridge inverter circuit has following beneficial effect for prior art:

(1) the utility model discloses a full-bridge inverter circuit is on the basis of traditional dc-to-ac converter, through parallelly connected resonance electric capacity on every MOS pipe of dc-to-ac converter and establish ties LCR resonant circuit at the output, through the resonance of circuit realized that the zero voltage of switch tube switches on and near zero voltage turn-off, very big reduction the switching loss of dc-to-ac converter;

(2) the utility model adopts a driving circuit composed of a SG3524 chip, 5 resistors and 1 capacitor, which has simple structure, adjustable frequency and duty ratio and stable output;

(3) the utility model discloses a sensor ACS712 chip detects the current signal that flows through in to the inverter, and ACS712 chip output signal gets into comparator LM339 and judges whether overflow to export JK trigger to the comparison result, JK trigger confirm overflow the back locking overflow the signal and export drive signal and take place the trouble input 10 feet of chip SG3524N, thereby turn-off drive signal, avoid overflowing and burn out the switch tube.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a circuit diagram of an inverter part of the present invention;

fig. 2 is a circuit diagram of a driving circuit of the present invention;

fig. 3 is a circuit diagram of the over-current protection circuit of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work all belong to the protection scope of the present invention.

As shown in fig. 1, the full-bridge inverter circuit of the present embodiment includes an inverter including MOS transistors S1 to S4, MOS transistor S1 and MOS transistor S2 form a first arm, MOS transistor S3 and MOS transistor S4 form a second arm, and further includes an inductor L1, a resistor R1, and capacitors C1 to C5. The middle point of the first bridge arm is connected with the middle point of the second bridge arm through a resistor R1, an inductor L1 and a capacitor C5 which are connected in series in sequence, the capacitor C1 is connected with the MOS tube S1 in parallel, the capacitor C2 is connected with the MOS tube S2 in parallel, the capacitor C3 is connected with the MOS tube S3 in parallel, and the capacitor C4 is connected with the MOS tube S4 in parallel.

The MOS transistors S1 to S4 constitute a conventional inverter, and the MOS transistors S1 and S4 operate in synchronization with each other, and the MOS transistors S2 and S3 operate in synchronization with each other. In fig. 1, diodes D1 to D4 are body diodes of MOS transistors S1 to S4, capacitors C1 to C4 are parallel resonant capacitors having the same capacitance, an inductor L1, a resistor R1, and a capacitor C5 are loads, an inductor L1, a resistor R1, and a capacitor C5 form an LCR series resonant circuit, and capacitors C1 to C4 form a CLCR resonant circuit together with the LCR series resonant circuit. The CLCR resonant tank has two resonant frequencies,

l is the inductance of inductor L1, C is the capacitance of capacitor C5, C0 is the parallel resonant capacitor, f1 is the resonant frequency of the LCR series resonant circuit, and f2 is the resonant frequency of the CLCR resonant circuit. The working frequency of the circuit of the embodiment is in the interval [ f1, f2 ]]。

The full-bridge inverter circuit of the embodiment works as follows: at the start of the first stage, the driving signals of the MOS transistors S1 and S4 are turned on, and the driving signals of the MOS transistors S2 and S3 are turned off, so that the currents of the MOS transistors S2 and S3 are transferred to the capacitor C2 and the capacitor C3, and the voltages of the capacitor C2 and the capacitor C3 rise in a sinusoidal manner, and the rising slope is low, so that the turn-off loss of the MOS transistors S2 and S3 is small. The load current at this stage is less than zero, and the current flows through the diode D1 and the diode D4. In the second stage, the currents of the diode D1 and the diode D4 are commutated to the MOS transistors S1 and S4, the currents start to rise in resonance, and the MOS transistors S1 and S4 achieve zero-voltage switching-on. In the third stage, the load resonant voltage reaches the maximum value, the load current starts to commutate when zero crossing, and the currents on the capacitor C2 and the capacitor C3 zero cross and start to commutate. In the fourth stage, the resonant voltage on the load is zero, the driving signals of the MOS transistors S2 and S3 are turned on, the driving signals of the MOS transistors S1 and S4 are turned off, at this time, the currents of the MOS transistors S1 and S4 are converted to the capacitors C1 and C4, the voltages at the drain and source terminals of the MOS transistors S1 and S4 start to rise in a sinusoidal form, the rising slope is low, so the turn-off loss of the MOS transistors S1 and S4 is small, the load current is still greater than zero at this stage, and the current flows through the diode D2 and the diode D3. In the fifth stage, the load current crosses zero, the currents on the diode D2 and the diode D3 are commutated to the MOS tubes S2 and S3, the currents start to rise in resonance, and the MOS tubes S2 and S3 achieve zero-voltage switching-on. At the start of the sixth phase, the load resonant voltage reaches a maximum value, at this time, the currents on the capacitor C1 and the capacitor C4 are zero, the currents on the capacitor C1 and the capacitor C4 start to commutate to the diode D1 and the diode D4, and at the end of the sixth phase, the voltage on the load resonates to zero.

Therefore, on the basis of the traditional inverter, the zero-voltage switching-on and near-zero-voltage switching-off of the switching tubes are realized through the resonance of the circuit by connecting the resonant capacitor in parallel on each MOS tube of the inverter and connecting the LCR resonant circuit in series at the output end, and the switching loss of the inverter is greatly reduced.

As shown in fig. 2, the full-bridge inverter circuit of the present embodiment further includes an SG3524 chip, a potentiometer R5, a potentiometer R6, and an optocoupler isolator. No. 6 pin of SG3524 chip is connected with the middle end of potentiometre R5, the one end ground connection of potentiometre R5, the other end of potentiometre R5 is unsettled, No. 2 pin of SG3524 chip is connected with the middle end of potentiometre R6, No. 16 pin of SG3524 chip is through potentiometre R6 ground connection, No. 9 pin of SG3524 chip is connected with MOS pipe S1, the grid of MOS pipe S4 respectively through the opto-coupler isolator, No. 14 pin of SG3524 chip is connected with MOS pipe S2, the grid of MOS pipe S3 respectively through the opto-coupler isolator. The SG3524 chip, the potentiometer R5, the potentiometer R6, and the optocoupler isolator constitute a driving circuit of the inverter switching tube in this embodiment, and the circuit structure of the optocoupler isolator refers to a conventional circuit.

The switch tube can be driven by using special driving chips such as IR2111, EXB841 and the like and an auxiliary circuit, but the driving output power and the output positive and negative voltages of the type are limited by the chip and cannot be flexibly designed, the driving chip has higher cost, and the auxiliary circuit is relatively complex. The driving circuit in the embodiment has a simple structure, is only composed of one SG3524 chip, 5 resistors and 1 capacitor, and has adjustable frequency and duty ratio and stable output. SG3524 is a double-end output type pulse width modulation chip, the working frequency can reach 300 potentiometer R5kHz, the frequency value of a potentiometer R6 connected with a pin 6 of the chip can be adjusted, and the duty ratio of a potentiometer R5 connected with a pin 2 can be adjusted. The VCC value is normally set to 5 potentiometer R5V, and the voltage value of the output signal can be changed by changing the value of VCC. Changing the value of resistor R2 in fig. 2 changes the output current and power level. The 10 pin of the SG3524 chip is a fault input end, and when the voltage of the pin is greater than about 0.76 potentiometer R5V, an output signal is closed, so that the overvoltage and overcurrent protection control can be realized.

As shown in fig. 3, the full-bridge inverter circuit of the present embodiment further includes an ACS712 chip, a comparator, resistors R7-R8, capacitors C6-C7, and a JK flip-flop. An IP + pin of the ACS712 chip is connected with a midpoint of the first bridge arm, an IP-pin is connected with a midpoint of the second bridge arm, a VIOUT pin is connected with an inverting input end of a comparator, a non-inverting input end of the comparator is connected with a reference voltage, an output end of the comparator is connected with a CLK end of the JK trigger through a resistor R7, a common end of a resistor R7 and the CLK end of the JK trigger is connected with a power supply VCC through a capacitor C6, a J end of the JK trigger is directly connected with the power supply VCC, an R end of the JK trigger is connected with the power supply VCC through a resistor R8, and a common end of a resistor R8 and the R end of the JK trigger is grounded through. Among them, the model of the comparator is preferably LM 339.

Since the short-circuit time that the switching tube can withstand depends on the magnitude of its saturation voltage drop and short-circuit current, which is generally very small, effective protection measures must be taken when short-circuit overcurrent occurs. In an inverter circuit with an MOS transistor as a switching device, a reactance element generally exists in the circuit, and in addition, the switching speed potentiometer R5 of the MOS transistor is high, so that when the MOS transistor is turned off and a reverse recovery diode connected in parallel with the MOS transistor reversely recovers, the stored energy of the inductor is released and generates a large surge voltage, which may cause the device to be damaged. In this embodiment, a current signal flowing through the inverter is detected by the ACS712 chip, an output signal of the ACS712 chip enters the comparator LM339 to determine whether the current signal is over-current, and the comparison result is output to the JK flip-flop, and the JK flip-flop determines that the current signal is over-current, locks the over-current signal, and outputs the over-current signal to the fault input terminal 10 of the driving signal generation chip SG3524N, thereby turning off the driving signal. The JK trigger adopts 74LS112 with effective falling edge, the sensor outputs a midpoint voltage of 2.5V when no overcurrent normally exists, and the output of the comparator LM339 is high level. When overcurrent occurs, the comparator LM339 outputs low level, the capacitor C6 charges and generates 1 falling edge at the CLK clock end to enable the JK flip-flop, and since J is 1 and K is 0 at this time, the output is set to 1, i.e. Q is 1, thereby turning off the output signal, and at the same time, the JK flip-flop enters a hold state to keep the drive off. The drive can be output again only by restarting after the overcurrent is cut off, so that the power supply can be ensured to stop outputting after the overcurrent occurs. The R end of the zero clearing end of the JK trigger is initially used for initializing circuit output, the R end is connected with a capacitor C7, and the R end is enabled to be at a low level and effectively reset when the JK trigger is started by utilizing the characteristic that the voltage at two ends of the capacitor cannot suddenly change, so that the initial output of the JK trigger is ensured to be at the low level, the JK trigger is enabled to be normally output, and the driving signal is prevented from being turned off by mistake when the JK trigger is started. The function of the capacitor C6 connected to the CLK terminal is to ensure that the CLK terminal is at high level when the JK flip-flop is turned on, charge the capacitor when an overcurrent is detected and delay the CLK to be at low level to provide a falling edge, and the charging time constant τ R7 × C6 prevents the CLK terminal from being directly at low level by overcurrent upon turning on and does not detect the falling edge.

The above description is only a preferred embodiment of the present invention, and should not be taken as limiting the invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A full-bridge inverter circuit comprises an inverter formed by MOS tubes S1-S4, a first bridge arm formed by MOS tube S1 and MOS tube S2, and a second bridge arm formed by MOS tube S3 and MOS tube S4, and is characterized by further comprising an inductor L1, a resistor R1 and capacitors C1-C5;

2. The full-bridge inverter circuit according to claim 1, further comprising an SG3524 chip, a potentiometer R5, a potentiometer R6 and an opto-isolator;

3. The full-bridge inverter circuit according to claim 2, further comprising an ACS712 chip, a comparator, a resistor R7 and a JK flip-flop;

4. The full-bridge inverter circuit of claim 3, wherein the comparator has a model number LM 339.

5. The full-bridge inverter circuit according to claim 3, further comprising a capacitor C6, wherein the capacitor C6 is connected between the common terminal of the R7-JK flip-flop CLK terminal and the power supply VCC.

6. The full-bridge inverter circuit as claimed in claim 3, further comprising a resistor R8, wherein the resistor R8 is serially connected between the power source VCC and the R terminal of the JK flip-flop.

7. The full-bridge inverter circuit as claimed in claim 6, further comprising a capacitor C7, wherein the common terminal of the resistor R8 and the R terminal of the JK flip-flop is grounded via a capacitor C7.