CN111010029A

CN111010029A - Light-load frequency reduction circuit of charge pump based on current control

Info

Publication number: CN111010029A
Application number: CN201911394436.2A
Authority: CN
Inventors: 马俊
Original assignee: Southchip Semiconductor Technology Shanghai Co Ltd
Current assignee: Shanghai Southchip Semiconductor Technology Co Ltd
Priority date: 2019-12-30
Filing date: 2019-12-30
Publication date: 2020-04-14
Anticipated expiration: 2039-12-30
Also published as: CN111010029B

Abstract

The invention discloses a light-load frequency reduction circuit of a charge pump based on current control, which mainly solves the problems of low light-load frequency reduction efficiency and low reliability of the existing charge pump circuit. The light-load frequency reduction circuit comprises an output current sampling circuit connected with a charge pump circuit, a highest switching frequency clamping circuit connected with the output current sampling circuit, a lowest switching frequency limiting circuit connected with the highest switching frequency clamping circuit, and a clock generating circuit connected with the lowest switching frequency limiting circuit and the charge pump circuit. The invention utilizes the reverse blocking pipe QB of the original charge pump system to generate a clock linearly related to the output load, so that the conversion efficiency of the charge pump can also keep high conversion efficiency under light load. And the hysteresis problem of adjusting the clock frequency by using the average current ensures the safety and reliability of the system under the conditions of sudden change of a power supply/load, even short circuit of a capacitor/input/output instant and the like. Therefore, the method is suitable for popularization and application.

Description

Light-load frequency reduction circuit of charge pump based on current control

Technical Field

The invention relates to the technical field of charge pumps, in particular to a light-load frequency reduction circuit of a charge pump based on current control.

Background

Charge pumps are switching converters that store energy using capacitors, wherein the capacitors are switched between a supply and a discharge state using switches, so that the supply voltage can be raised or lowered. In a mobile terminal or a portable electronic device, the voltage of the power supply may be lower than the operating voltage, and the charge pump may provide the voltage of the power supply to operate the system, for example, the voltage generated by the charge pump is in a range of 3.3V to 4.0V, so as to meet the operating requirement of the electronic device.

As shown in fig. 1, which is a schematic circuit diagram of the charge pump, four power tubes are divided into two phases Φ 1 and Φ 2, and are respectively turned on, and in an ideal case of no load, VX is 2 × VY. The most common application is to use VX as the input power source, resulting in approximately half the output voltage VY. Similarly, if VY is used as the input power, then approximately twice the output voltage VX will be obtained.

As shown in fig. 2, a typical application of the charge pump is shown, VBUS is an input power source, and OUT is connected to an output load; Q1-Q4 and Q5-Q8 form two branches with the phase difference of 180 degrees; wherein QB keeps off reverse switch tube (the source of QB connects in the high side, and its parasitic diode is pointed to PMID by VBUS), switches on QB during normal work, if the unexpected turn-off QB takes place, can avoid the reverse current route from PMID to VBUS.

For voltage converters, the most important core indicator must be efficiency. How to minimize self-loss is the most central consideration in transferring energy from the input to the output.

In general, for voltage converters, losses come from three aspects, one is "turn-on losses" related to the load but not to the switching frequency, i.e. the switching tube, the parasitic resistance in the current path is the heat loss generated by the resistance when conducting the current; one is both load-dependent and proportional to the switching frequency, and the "switching tube voltage current overlap loss" (the switch conducts a large current and has a large voltage drop during the switching on or off process); the last one is load independent but proportional to the switching frequency, the "switching tube parasitic capacitance charge-discharge loss" (the parasitic capacitance of the switching tube is charged and discharged every time the switching tube is switched on and off).

The charge pump architecture has the greatest advantage over other voltage converter architectures in that it is "soft-switched" both on and off, i.e., there is little "switching tube voltage current crossover loss". The main losses are from "conduction losses" and "switching tube parasitic capacitance charge-discharge losses". During heavy load, the 'conduction loss' is dominant; during light load, the charging and discharging loss of the parasitic capacitor of the switching tube is dominant.

The "conduction loss" is mainly determined by the tube size, and there is not much design freedom; however, the "charging and discharging loss of the parasitic capacitor of the switching tube" is related to the switching frequency, so that the switching frequency of the charge pump can be reduced as much as possible on the premise of maintaining the output voltage when the load is light, and high-efficiency voltage conversion can be realized.

Disclosure of Invention

The invention aims to provide a light-load frequency reduction circuit of a charge pump based on current control, which mainly solves the problems of low light-load frequency reduction efficiency and low reliability of the existing charge pump circuit.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows:

a light-load frequency reduction circuit of a charge pump based on current control comprises an output current sampling circuit connected with a charge pump circuit, a highest switching frequency clamping circuit connected with the output current sampling circuit, a lowest switching frequency limiting circuit connected with the highest switching frequency clamping circuit, and a clock generating circuit connected with the lowest switching frequency limiting circuit and the charge pump circuit.

Furthermore, the light-load frequency-reducing circuit also comprises a voltage difference monitoring circuit and an extreme voltage difference protection circuit which are connected with the charge pump circuit.

Further, the current sampling circuit comprises a sampling tube QB _ SNS of which the source is connected with a power input end VBUS of the charge pump circuit, an MOS tube Q _ EA of which the source is connected with the drain of the sampling tube QB _ SNS, and an operational amplifier OP1 of which the negative input end is connected with the drain of the sampling tube QB _ SNS, the positive input end is connected with a PMID port of the charge pump circuit, and the output end is connected with the gate of the MOS tube Q _ EA; the operational amplifier OP1 and the MOS transistor Q _ EA form a feedback loop, so that drain voltages of the sampling transistor QB _ SNS and the reverse blocking switch tube QB in the charge pump circuit are equal.

Further, the highest switching frequency clamping circuit comprises an MOS transistor Q _ lim with a drain connected to the drain of the MOS transistor Q _ EA, an MOS transistor Q _ mirror1, an MOS transistor Q _ mirror2 with a source connected to both the MOS transistor Q _ lim and the source of the MOS transistor Q _ mirror1, a capacitor C _ filter with one end connected to the gate of the MOS transistor Q _ mirror2 and the other end connected to the source of the MOS transistor Q _ mirror2, a resistor R _ lim connected to the drain of the Q _ mirror2, a reference voltage V _ lim with an anode connected to the other end of the resistor R _ lim, an operational amplifier OP2 with a cathode input connected to the cathode of the reference voltage V _ lim, a cathode input connected to the drain of the MOS transistor Q _ mirror2 and an output connected to the gate of the MOS transistor Q _ lim; the source of the MOS transistor Q _ lim is also connected with the GND end in the charge pump circuit, and the gate of the MOS transistor Q _ mirror1 is connected with the lowest switching frequency limiting circuit.

Further, the lowest switching frequency limiting circuit comprises a MOS transistor Q _ mirror3 connected with a gate of the MOS transistor Q _ mirror1, a MOS transistor Q _ mirror4 and a MOS transistor Q _ mirror5, wherein the gate of the MOS transistor Q _ mirror4 is connected with a drain of the MOS transistor Q _ mirror3, a capacitor C _ clk with one end connected with a drain of the MOS transistor Q _ mirror5 and the other end connected with a source of the MOS transistor Q _ mirror3, a MOS transistor Q _ Forcerefresh with a source connected with a source of the MOS transistor Q _ mirror5, a current source I _ Forcerefresh connected with a drain of the MOS transistor Q _ Forcerefresh, a current source I _ lowit connected with a source of the MOS transistor Q _ Forcerefresh, and a MOS transistor Q _ rst with a drain connected with a free end of the current source I _ glitch; the MOS tube Q _ rst is connected with a clock generation circuit.

Further, the clock generation circuit comprises a comparator cmp1 with a negative input end connected with the drain electrode of the MOS transistor Q _ rst and a positive input end connected with the reference voltage Vref, a delay device dly connected with the output end of the comparator cmp1, an inverter inv connected with the output end of the delay device dly, an AND gate A1 with one input end connected with the output end of the comparator cmp1 and the other input end connected with the output end of the inverter inv, a D flip-flop with a clock input end connected with the AND gate A1 and the grid electrode of the MOS transistor Q _ rst, an AND gate A2 with one input end connected with the output end Q of the D flip-flop, and an AND gate A3 with one input end connected with the output end Q' of the D flip-flop.

Further, the voltage difference monitoring circuit comprises feedback resistors RF1 and RF2 which are connected in series, wherein one end of the feedback resistors RF1 and RF2 is connected with the PMID port of the charge pump circuit, the other end of the feedback resistors RF1 is connected with the GND port of the charge pump circuit, a feedback capacitor CF1 is connected in parallel with two ends of the feedback resistor RF1, a feedback capacitor CF2 is connected in parallel with two ends of the feedback resistor RF2, a comparator cmp2 is connected with the positive input end of the feedback resistor RF1, a comparator cmp3 is connected with the negative input end of the feedback resistor RF2, and a not gate a4 is connected with two input ends of the comparator cmp2 and the output end of the comparator cmp 3; two threshold voltage sources VTH which are sequentially connected in series are connected between the negative input end of the comparator cmp2 and the positive input end of the comparator cmp3, and an OUT port of the charge pump circuit is connected between the two threshold voltage sources VTH.

Further, the extreme voltage difference protection circuit comprises feedback resistors RF3 and RF4 which are connected in series, wherein one end of the feedback resistors is connected with the PMID port of the charge pump circuit, the other end of the feedback resistors RF3 is connected with the GND port of the charge pump circuit, the feedback capacitor CF3 is connected with two ends of the feedback resistor RF3 in parallel, the feedback capacitor CF4 is connected with two ends of the feedback resistor RF4 in parallel, a comparator cmp4 is connected with a positive input end of the feedback resistor RF3, a comparator cmp5 is connected with a negative input end of the feedback resistor RF4, and a not gate a5 is connected with two input ends of the comparator cmp4 and the output end of the comparator cmp 5; two threshold voltage sources VTH _ extreme connected in series in sequence are connected between the negative input end of the comparator cmp4 and the positive input end of the comparator cmp5, and an OUT port of the charge pump circuit is connected between the two threshold voltage sources VTH _ extreme.

Compared with the prior art, the invention has the following beneficial effects:

(1) the invention utilizes the reverse blocking pipe QB of the original charge pump system to generate a clock linearly related to the output load, so that the conversion efficiency of the charge pump can also keep high conversion efficiency under light load. And a monitoring protection circuit is formed by two pairs of comparators of 'differential pressure monitoring' and 'extreme differential pressure protection', so that the problem of hysteresis of adjusting clock frequency by using average current is solved, and the safety and reliability of the system under the condition that a power supply/load suddenly changes, even a capacitor is opened and shorted/an input/output is instantaneously shorted and the like at an extreme end are ensured.

(2) The present invention utilizes the average current information of the charge pump to generate the clock frequency, so the response of the whole clock is slow. By using the key differential pressure monitoring circuit (with high speed and response time of hundreds of nanoseconds), the frequency of the charge pump can be immediately improved under the conditions of voltage jump/load jump and the like of the system, so that large instantaneous current is avoided, and the reliability of the system is ensured.

(3) The invention limits the highest frequency of the clock through the adjustable highest frequency limiting circuit, thereby ensuring the reliability and stability of the system; by using the adjustable lowest frequency limiting circuit, the system requiring the working frequency of the charge pump to be higher than the audio frequency is enabled, and the noise is prevented from being heard by an end user.

Drawings

Fig. 1 is a circuit schematic of a prior art charge pump.

Fig. 2 is a schematic diagram of a typical application circuit of a charge pump in the prior art.

Fig. 3 is a schematic circuit diagram of the present invention.

FIG. 4 is a schematic diagram of a differential voltage protection circuit according to the present invention

FIG. 5 is a schematic diagram of a differential pressure monitoring circuit of the present invention.

Detailed Description

The present invention will be further described with reference to the following description and examples, which include but are not limited to the following examples.

Examples

As shown in fig. 3 to 5, the light-load frequency-reducing circuit of a charge pump based on current control according to the present invention includes an output current sampling circuit connected to a charge pump circuit, a highest switching frequency clamping circuit connected to the output current sampling circuit, a lowest switching frequency limiting circuit connected to the highest switching frequency clamping circuit, and a clock generating circuit connected to both the lowest switching frequency limiting circuit and the charge pump circuit.

The light-load frequency-reducing circuit also comprises a voltage difference monitoring circuit and an extreme voltage difference protection circuit which are connected with the charge pump circuit.

The current sampling circuit comprises a sampling tube QB _ SNS of which the source electrode is connected with a power supply input end VBUS of the charge pump circuit, an MOS tube Q _ EA of which the source electrode is connected with the drain electrode of the sampling tube QB _ SNS, and an operational amplifier OP1 of which the negative electrode input end is connected with the drain electrode of the sampling tube QB _ SNS, the positive electrode input end is connected with a PMID port of the charge pump circuit, and the output end is connected with the grid electrode of the MOS tube Q _ EA; the operational amplifier OP1 and the MOS transistor Q _ EA form a feedback loop, so that drain voltages of the sampling transistor QB _ SNS and the reverse blocking switch tube QB in the charge pump circuit are equal. The grid electrodes and the source electrodes of the QB _ SNS tube and the QB tube of the sampling tube are connected to the same node, but the sizes of the sampling tube and the QB tube are 1: and N is added. By making the drain voltages of QB _ SNS and QB equal through the feedback loop of OP1 and Q _ EA, the current through Q _ EA (i.e., QB _ SNS) is 1/N of the current through the QB tube. In a charge pump configuration, if the current through QB is low pass filtered, the current through QB is half the average charge pump output current IOUT. This achieves sampling of the charge pump load current, with the low-pass filtered Q _ EA current "I _ SNS" being 1/2N of the charge pump average output current IOUT.

The clock generation circuit comprises a comparator cmp1 with a negative input end connected with the drain electrode of the MOS transistor Q _ rst and a positive input end connected with a reference voltage Vref, a delayer dly connected with the output end of the comparator cmp1, an inverter inv connected with the output end of the delayer dly, an AND gate A1 with one input end connected with the output end of the comparator cmp1 and the other input end connected with the output end of the inverter inv, a D trigger with a clock input end connected with the AND gate A1 and the grid electrode of the MOS transistor Q _ rst, an AND gate A2 with one input end connected with the output end Q of the D trigger, and an AND gate A3 with one input end connected with the output end Q' of the D trigger.

The sampling current "I _ SNS" flowing through Q _ EA is passed through the current mirror pair "Q _ mirror1/Q _ mirror 3" and "Q _ mirror4/Q _ mirror 5", and the mirror current "I _ mirror" equal to the sampling current of the charge pump load charges the capacitor C _ clk. When the capacitor C _ clk is charged to Vref voltage from 0V by the mirror current, the comparator is triggered to turn from low to high; the rising edge of the comparator output produces a short pulse that releases the charge of C _ clk, and the capacitor voltage returns to 0V, starting the next charge. The short pulse of each comparator triggers the inversion of the charge pump phase, and two phase inversions are a complete cycle, which is realized by the following D flip-flop. The frequency of the clock circuit is also easily calculated:

t _ CLK is 2 × C _ CLK Vref/I _ mirror formula one.

The highest switching frequency clamping circuit comprises an MOS tube Q _ lim and an MOS tube Q _ mirror1, wherein the drain electrode of the MOS tube Q _ EA is connected with the drain electrode of the MOS tube Q _ lim, the source electrode of the MOS tube Q _ mirror1 is connected with the source electrode of the MOS tube Q _ lim 2, one end of the capacitor C _ filter is connected with the grid electrode of the MOS tube Q _ mirror2, the other end of the capacitor C _ filter is connected with the source electrode of the MOS tube Q _ mirror2, a resistor R _ lim is connected with the drain electrode of the Q _ mirror2, a reference voltage V _ lim is connected with the other end of the resistor R _ lim at the positive electrode, the input end of the positive electrode is connected with the negative electrode of the reference voltage V _ lim, the input end of the negative electrode is connected with the drain electrode of the MOS tube Q _ mirror2, and the output end of the operational amplifier OP; the source of the MOS transistor Q _ lim is also connected with the GND end in the charge pump circuit, and the gate of the MOS transistor Q _ mirror1 is connected with the lowest switching frequency limiting circuit.

The larger the I _ SNS (IOUT/2N) current, the higher the clock frequency. However, the switching frequency cannot be too high, and a certain limitation on the switching frequency is required. Alternatively, it may be said that when the load current is greater than a certain threshold, it is desirable that the charge pump operates at a fixed switching frequency, which no longer changes with increasing load. The I _ SNS current is conducted to the resistor R _ lim through the current mirror Q _ mirror1/Q _ mirror2, and a voltage difference of I _ SNS R _ lim is generated. If the voltage difference is less than V _ lim, then the OP-amp OP2 output is low and Q _ lim is turned off. As I _ SNS increases, the voltage differential increases to equal V _ lim, at which time the OP-amp OP2 will drive Q _ lim and clamp the current through the Q _ mirror1 tube. If I _ SNS continues to increase, the increased current will all flow through Q _ lim, and the current flowing through Q _ mirror1 will not increase, thereby limiting the maximum current of Q _ mirror1, as can be seen from equation one, the maximum switching frequency of the charge pump is also limited.

The maximum mirror phase current "I _ mirror _ max" and the maximum switching frequency "F _ CP _ max" can be calculated by the following equations.

I _ mirror _ max is V _ lim/R _ lim formula two;

f _ CP _ max ═ V _ lim/(2 × R _ lim × C _ clk _ Vref) formula three;

the charge pump load of the turning point of the switching frequency working mode which is in proportion to the load and the fixed switching frequency working mode is as follows:

iout _ critical is 2 × N × V _ lim/R _ lim formula four;

when the load current is less than Iout _ critical, the switching frequency of the charge pump is in direct proportion to the load; when the load current is greater than Iout _ critical, the charge pump operates at a constant switching frequency F _ CP _ max.

The lowest switching frequency limiting circuit comprises an MOS tube Q _ mirror3 connected with a grid electrode of an MOS tube Q _ mirror1, an MOS tube Q _ mirror4 and an MOS tube Q _ mirror5, wherein the grid electrode of the MOS tube Q _ mirror4 is connected with a drain electrode of an MOS tube Q _ mirror3, a capacitor C _ clk, one end of which is connected with a drain electrode of the MOS tube Q _ mirror5, and the other end of which is connected with a source electrode of an MOS tube Q _ mirror3, an MOS tube Q _ Forcerefresh, the source electrode of which is connected with a source electrode of the MOS tube Q _ mirror5, a current source I _ Forcerefresh connected with a drain electrode of the MOS tube Q _ Forcerefresh, a current source I _ Lowlit connected with a source electrode of the MOS tube Q _ Forcerefresh and a drain electrode of the MOS tube Q _ rst connected with free ends of the current source I _ Forcerefresh and the current source I _ Lomit; the MOS tube Q _ rst is connected with a clock generation circuit.

In the circuit for charging the C _ clk, there is a fixed constant current I _ lowlimit. This current ensures that the switching frequency can be embedded above a minimum value even when there is no load at all (in particular applications, such as audio rejection, switching frequencies greater than 22KHz are required).

This lowest switching frequency is:

f _ CP _ min ═ I _ lowlimit/(2 × C _ clk ═ Vref) formula five.

The charge pump is "safe" if it is operated at a higher switching frequency. The charge pump has a very strong ability to maintain the relationship of V _ PMID equal to about twice VOUT because CFLY capacitance is very large and the conduction resistance of the internal switch tube is very small. Regardless of any voltage change or load change in VBUS/PMID, the charge pump can react quickly and return to steady state for one or a few cycles.

However, when the operating frequency of the charge pump is reduced, if the input voltage changes or the load changes within a half cycle, the lower operating frequency cannot be maintained continuously, but the switching frequency is increased immediately to refresh the capacitor voltage so that each capacitor voltage follows the changes of the input voltage and the load in time.

Whatever the external condition occurs, the input voltage changes well, the output load changes well, and most importantly, this voltage difference is (V _ PMID/2-VOUT). The external change is reflected by the larger voltage difference, and at the moment, the working phase of the charge pump is switched immediately to refresh the voltage of each capacitor. Therefore, the voltage difference monitoring circuit is required to monitor the voltage difference of the whole circuit so as to ensure that the charge pump can timely follow the change of external conditions during light-load frequency reduction and ensure the safety and reliability of the system.

The voltage difference monitoring circuit comprises feedback resistors RF1 and RF2, wherein one end of the feedback resistors is connected with a PMID port of the charge pump circuit after being connected in series, the other end of the feedback resistors is connected with a GND port of the charge pump circuit, a feedback capacitor CF1 is connected with two ends of a feedback resistor RF1 in parallel, a feedback capacitor CF2 is connected with two ends of a feedback resistor RF2 in parallel, a comparator cmp2 with a positive electrode input end connected with the feedback resistor RF1, a comparator cmp3 with a negative electrode input end connected with the feedback resistor RF2, and a NOT gate A4 with two input ends respectively connected with output ends of the comparator cmp2 and the comparator cmp 3; two threshold voltage sources VTH which are sequentially connected in series are connected between the negative input end of the comparator cmp2 and the positive input end of the comparator cmp3, and an OUT port of the charge pump circuit is connected between the two threshold voltage sources VTH.

The same two feedback resistors RF and two feedback capacitors CF divide the voltage to obtain HALF the PMID voltage, HALF _ PMID. Wherein the resistance is to obtain a steady-state voltage and the capacitance can accelerate the transient response. This voltage is compared to VOUT + VTH and VOUT-VTH, respectively, and if this voltage is higher than VOUT + VTH or lower than VOUT-VTH, the comparator is triggered to toggle, leaving Forcerefresh _ n low. When Forcerefresh _ n is low, the charging current of C _ clk is divided into two paths I _ Forcerefresh, so that the charge pump can maintain a high switching frequency even if the mirror current is small.

If extreme conditions, such as capacitor open short circuit and input/output short circuit, occur during the operation of the charge pump, all power tubes of the charge pump must be immediately turned off, otherwise, the chip will be burned out. Therefore, an extreme differential pressure protection circuit needs to be provided.

The extreme voltage difference protection circuit comprises feedback resistors RF3 and RF4, wherein one end of the feedback resistors is connected with a PMID port of the charge pump circuit after being connected in series, the other end of the feedback resistors is connected with a GND port of the charge pump circuit, a feedback capacitor CF3 is connected with two ends of a feedback resistor RF3 in parallel, a feedback capacitor CF4 is connected with two ends of a feedback resistor RF4 in parallel, a comparator cmp4 is connected with a positive electrode input end of the feedback resistor RF3, a comparator cmp5 is connected with a negative electrode input end of the feedback resistor RF4, and a NOT gate A5 is connected with two input ends of the comparator cmp4 and the output end of the comparator cmp5 respectively; two threshold voltage sources VTH _ extreme connected in series in sequence are connected between the negative input end of the comparator cmp4 and the positive input end of the comparator cmp5, and an OUT port of the charge pump circuit is connected between the two threshold voltage sources VTH _ extreme. The circuit is similar to the key voltage difference monitoring described above, and the difference is that the threshold voltage VTH _ extreme is larger, and the voltage dividing speed of the comparator and the resistor is required to be faster.

Through the design, the reverse blocking pipe QB of the original charge pump system is utilized to generate the clock linearly related to the output load, so that the conversion efficiency of the charge pump can be kept high under light load. And a monitoring protection circuit is formed by two pairs of comparators of 'differential pressure monitoring' and 'extreme differential pressure protection', so that the problem of hysteresis of adjusting clock frequency by using average current is solved, and the safety and reliability of the system under the condition that a power supply/load suddenly changes, even a capacitor is opened and shorted/an input/output is instantaneously shorted and the like at an extreme end are ensured. Therefore, the method has high use value and popularization value.

The above-mentioned embodiment is only one of the preferred embodiments of the present invention, and should not be used to limit the scope of the present invention, but all the insubstantial modifications or changes made within the spirit and scope of the main design of the present invention, which still solve the technical problems consistent with the present invention, should be included in the scope of the present invention.

Claims

1. A light-load frequency reduction circuit of a charge pump based on current control is characterized by comprising an output current sampling circuit connected with a charge pump circuit, a highest switching frequency clamping circuit connected with the output current sampling circuit, a lowest switching frequency limiting circuit connected with the highest switching frequency clamping circuit, and a clock generating circuit connected with the lowest switching frequency limiting circuit and the charge pump circuit.

2. The light-load frequency-reducing circuit of the charge pump based on the current control as claimed in claim 1, further comprising a voltage difference monitoring circuit and an extreme voltage difference protection circuit both connected to the charge pump circuit.

3. The light-load frequency-reducing circuit of the charge pump based on the current control as claimed in claim 1, wherein the current sampling circuit comprises a sampling tube QB _ SNS having a source connected to a power input VBUS of the charge pump circuit, a MOS transistor Q _ EA having a source connected to a drain of the sampling tube QB _ SNS, an operational amplifier OP1 having a negative input connected to the drain of the sampling tube QB _ SNS, a positive input connected to a PMID port of the charge pump circuit, and an output connected to a gate of the MOS transistor Q _ EA; the operational amplifier OP1 and the MOS transistor Q _ EA form a feedback loop, so that drain voltages of the sampling transistor QB _ SNS and the reverse blocking switch tube QB in the charge pump circuit are equal.

4. The light-load frequency reduction circuit of the current-control-based charge pump according to claim 3, wherein the maximum switching frequency clamping circuit comprises a MOS transistor Q _ lim with a drain connected to the drain of the MOS transistor Q _ EA, a MOS transistor Q _ mirror1, a MOS transistor Q _ mirror2 with a source connected to the sources of the MOS transistor Q _ lim and the MOS transistor Q _ mirror1, a capacitor C _ filter with one end connected to the gate of the MOS transistor Q _ mirror2 and the other end connected to the source of the MOS transistor Q _ mirror2, a resistor R _ lim connected to the drain of the Q _ mirror2, a reference voltage V _ lim with a positive electrode connected to the other end of the resistor R _ lim, an operational amplifier 2 with a positive electrode input connected to the negative electrode of the reference voltage V _ lim, a negative electrode input connected to the drain of the MOS transistor Q _ mirror2 and an output end connected to the gate of the MOS transistor Q _ lim; the source of the MOS transistor Q _ lim is also connected with the GND end in the charge pump circuit, and the gate of the MOS transistor Q _ mirror1 is connected with the lowest switching frequency limiting circuit.

5. The light-load frequency reduction circuit of the current-control-based charge pump according to claim 4, wherein the lowest switching frequency limiting circuit comprises a MOS transistor Q _ mirror3 connected to the gate of the MOS transistor Q _ mirror1, a MOS transistor Q _ mirror4 and a MOS transistor Q _ mirror5 both connected to the drain of the MOS transistor Q _ mirror3, a capacitor C _ clk connected to the drain of the MOS transistor Q _ mirror5 at one end and to the source of the MOS transistor Q _ mirror3 at the other end, a MOS transistor Q _ Forcerefresh connected to the source of the MOS transistor Q _ mirror5 at its source, a current source I _ Forcerefresh connected to the drain of the MOS transistor Q _ Forcerefresh, a current source I _ Loimit connected to the source of the MOS transistor Q _ Forcerefresh, and a MOS transistor Q _ free current source Q connected to the drain of the current source I _ Forcerefresh and the MOS transistor I _ free end; the MOS tube Q _ rst is connected with a clock generation circuit.

6. The light-load frequency-reducing circuit of the charge pump based on the current control as claimed in claim 5, wherein the clock generation circuit comprises a comparator cmp1 with a negative input terminal connected to the drain of the MOS transistor Q _ rst and a positive input terminal connected to the reference voltage Vref, a delay dly connected to the output terminal of the comparator cmp1, an inverter inv connected to the output terminal of the delay dly, an AND gate A1 with one input terminal connected to the output terminal of the comparator cmp1 and the other input terminal connected to the output terminal of the inverter inv, a D flip-flop with a clock input terminal connected to the AND gate A1 and the gate of the MOS transistor Q _ rst, an AND gate A2 with one input terminal connected to the output terminal Q of the D flip-flop, and an AND gate A3 with one input terminal connected to the output terminal Q' of the D flip-flop.

7. The light-load frequency-down circuit of the charge pump based on the current control as claimed in claim 2, wherein the voltage difference monitoring circuit comprises feedback resistors RF1, RF2 connected in series with one end connected to the PMID port of the charge pump circuit and the other end connected to the GND port of the charge pump circuit, a feedback capacitor CF1 connected in parallel with both ends of the feedback resistor RF1, a feedback capacitor CF2 connected in parallel with both ends of the feedback resistor RF2, a comparator cmp2 connected with the positive input end of the feedback resistor RF1, a comparator cmp3 connected with the negative input end of the feedback resistor RF2, and a not gate a4 connected with the two input ends of the comparator cmp2 and the output end of the comparator cmp 3; two threshold voltage sources VTH which are sequentially connected in series are connected between the negative input end of the comparator cmp2 and the positive input end of the comparator cmp3, and an OUT port of the charge pump circuit is connected between the two threshold voltage sources VTH.

8. The light-load frequency-down circuit of the charge pump based on the current control as claimed in claim 2, wherein the extreme voltage difference protection circuit comprises feedback resistors RF3, RF4 connected in series with one end connected to the PMID port of the charge pump circuit and the other end connected to the GND port of the charge pump circuit, a feedback capacitor CF3 connected in parallel with both ends of the feedback resistor RF3, a feedback capacitor CF4 connected in parallel with both ends of the feedback resistor RF4, a comparator cmp4 connected with the positive input end of the feedback resistor RF3, a comparator cmp5 connected with the negative input end of the feedback resistor RF4, and a not gate a5 connected with the two input ends of the comparator cmp4 and the output end of the comparator cmp 5; two threshold voltage sources VTH _ extreme connected in series in sequence are connected between the negative input end of the comparator cmp4 and the positive input end of the comparator cmp5, and an OUT port of the charge pump circuit is connected between the two threshold voltage sources VTH _ extreme.