CN113315367A

CN113315367A - Charge pump parallel current-sharing circuit based on frequency control

Info

Publication number: CN113315367A
Application number: CN202110618696.4A
Authority: CN
Inventors: 马俊
Original assignee: Southchip Semiconductor Technology Shanghai Co Ltd
Current assignee: Southchip Semiconductor Technology Shanghai Co Ltd
Priority date: 2021-06-03
Filing date: 2021-06-03
Publication date: 2021-08-27
Anticipated expiration: 2041-06-03
Also published as: CN113315367B

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a frequency control-based parallel current-sharing circuit of a charge pump. The invention mainly changes the equivalent impedance of the charge pump by adjusting the switching frequency so as to realize the output current equalization when the charge pump works in parallel, and particularly realizes the parallel current equalization by enabling the charge pump power tube to work according to the output frequency through a frequency adjusting module connected with the charge pump. The scheme can be generalized to any conversion ratio of the charge pump architecture. The scheme of the invention changes the frequency, thereby being suitable for the charge pump application with non-fixed frequency and supporting the avoidance of energy concentration at a certain frequency point through frequency jitter. The invention provides two implementation modes of analog and digital.

Description

Charge pump parallel current-sharing circuit based on frequency control

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a frequency control-based parallel current-sharing circuit of a charge pump.

Background

The basic architecture of the charge pump is shown in FIG. 1, four power tubes are in accordance with complementary phases φ 1 and

are respectively conducted. In an ideal case of no load, VX is 2 × VY, IX is IY/2(VX end current is half of VY end current). The most common application is to use VX as the input power source, resulting in approximately half the output voltage VY. Similarly, if VY is used as the input power, then approximately twice the output voltage VX will be obtained. If VX is the input and VY is the output, the voltage waveforms of CFLY in two working states in steady state are shown in FIG. 2. In phi 1 phaseUnder the condition of the capacitor, the capacitor voltage is charged between VX and VY in an RC mode; in that

In phase, the capacitor voltage is RC discharged between VY and ground. Accordingly, formulas 1 to 4 can be obtained:

Z_CP＝(VX/2-VY)/I_LOAD(formula 4)

In which COUT is assumed>>The CFLY, i.e., VOUT voltage, can be considered constant (the load is a voltage source). The sum of the on-resistances of M1/M3 is equal to the sum of the on-resistances of M2/M4, and is represented as R_ON. The duty cycle is 50%. TS is a switching period, and FS represents a switching frequency (FS ═ 1/TS). The equivalent impedance Z of the charge pump can be obtained by the formula_CP

The charge pump may operate at a fixed frequency, where the energy of the charge pump is concentrated in the frequency domain mainly at the switching frequency and its harmonic frequencies. In order to avoid concentrating too much energy in a certain frequency point, a system usually adopts a frequency jitter technology. As shown in fig. 3, the operating frequency of the charge pump varies with time, i.e., varies within the ranges of F _ switching _ min and F _ switching _ max, centered on F _ switching. FIG. 3 is an example of five frequency steps, typically the number of frequency steps will be more; the five frequencies in fig. 3 are distributed at equal intervals and are changed step by step, and the implementation method is simple and common practice, and other changing modes also exist. After the dithering, the distribution of energy over the spectrum is changed, as shown in fig. 4. When there is no jitter, the energy is concentrated on the switching frequency and its harmonics, as shown in fig. 4 (a); when the dither technique is adopted, the energy is concentrated in the dither range from F _ switching _ min to F _ switching _ max and its harmonic frequencies, as shown in (b) of fig. 4. After frequency dithering, the energy concentrated on the switching frequency is uniformly distributed in the dithering range, so that the energy peak value is reduced, and the energy is prevented from being concentrated on a certain frequency point.

When a system requires more current capability, it is often necessary to use multiple charge pump chips in parallel, as shown in fig. 5. The inputs and outputs of the different charge pump chips are tied together and the respective CFLY capacitors are used to collectively carry energy from the inputs to the outputs. In order to avoid energy concentration at a certain frequency point, each charge pump chip can be subjected to frequency dithering.

Generally, a charge pump charging chip has the function of detecting input and output currents, and some charging chips also have an ADC (analog-to-digital converter) to convert an analog current signal into a digital signal.

In general, for the detection of the input current, a power tube through which all the input current flows is selected, and the input current flowing through the power tube is indirectly obtained by detecting the current flowing through the Sense tube having the same external condition as the power tube but a much smaller proportion. As shown in fig. 6, the ratio of the power tube to the sense tube is K: 1, the gate and drain terminals of the power tube and the drain are short-circuited together, the source voltages of the power tube and the sense tube are equal through a feedback loop of the operational amplifier, the external conditions of the power tube and the sense tube are the same, and the current I _ SNSx flowing through the sense tube is obtained. Thus, the current flowing through the power tube will be K times the current flowing through the sense tube, i.e., I _ IN ═ I _ SNSx × K.

For the charge pump quick charge chip, the output is connected with two ends of the battery, and the output current of the charge pump is the charging current of the battery. Generally, a power resistor with a small resistance value is connected in series with a battery, and a charging current can be obtained by collecting the voltage at two ends of the power resistor. However, in order to reduce the loss, the resistance of the power resistor is usually small, typically 2mohm, and thus the voltage drop across the power resistor is also small. In order to detect the small voltage drop, the charge pump quick charge chip integrates an amplifying circuit, and the voltage drop is accurately amplified by more than dozens of times.

When a system requires a large current capability, multiple charge pump chips are usually used in parallel. However, due to the difference between the chips themselves and the difference between the external environments such as capacitance and capacitance, and PCB traces, the current between different chips is not uniform in practical use. This can lead to the following disadvantages:

1) the chip with the most concentrated current will generate local hot spots. If the chip itself has negative temperature characteristics (i.e., the higher the temperature, the smaller the equivalent resistance, and the stronger the conductive capability), positive and negative feedback will further increase the current non-uniformity. For system heat dissipation, especially for today's very compact smartphone systems, the core of temperature control is to avoid a single hot spot. The more uniform the heat distribution, the more heat dissipation is facilitated, and further, the greater capacity density (greater charging power) is integrated on the premise that the use experience of a customer is not affected.

2) Current concentration and the creation of localized hot spots also accelerates device aging. Generally, the aging speed of the device is in an exponential relation with the temperature, and the corresponding device is easily scrapped at an accelerated speed due to local hot spots, so that the reliability of the whole system is reduced.

3) Each chip has a maximum current capability limit, and system design needs to ensure that any chip does not exceed the current limit. The current non-uniformity will inevitably result in the total output current of the whole system to be reduced.

4) The system does not know which chip will concentrate the most current at the beginning of design, which causes that each chip can only be designed according to the maximum current during system design, and the design redundancy causes waste of system resources.

Disclosure of Invention

For the above problems, the specific reasons for the non-uniform current of the parallel chips may be derived from the differences of the chips themselves, the differences of the PCB traces, the deviations of the CFLY capacitances, etc., but they can be summarized as the differences of the "equivalent impedances" of the chips. The invention provides that the equivalent impedance of each chip is adjusted by feedback by acquiring the error between the actual output current and the ideal output current of each chip, thereby realizing the current sharing of the output currents of the chips connected in parallel.

The technical scheme of the invention is as follows:

a charge pump parallel current-sharing circuit based on frequency control comprises N charge pumps connected in parallel, and is characterized by further comprising N frequency adjusting modules respectively connected with the N charge pumps in sequence, wherein each frequency adjusting module comprises an error amplifier, a capacitor and a voltage-controlled oscillator, the non-inverting input end of the error amplifier is input current of a charge pump branch circuit connected with the frequency adjusting module, the inverting input end of the error amplifier is output current/2N of the charge pump parallel circuit, the output end of the error amplifier is connected with the input end of the voltage-controlled oscillator, and the connection point of the output end of the error amplifier and the input end of the voltage-controlled oscillator is grounded through the capacitor; the clock signal output by the voltage-controlled oscillator is used as a driving signal of a power tube in the corresponding charge pump branch circuit; the error amplifier is used for integrating the current of the charge pump branch circuit connected with the frequency adjusting module and the total output current of the 1/2N charge pump parallel circuit, converting the accumulated error voltage into a clock signal after passing through the voltage-controlled oscillator, and outputting the clock signal to the charge pump branch circuit connected with the frequency adjusting module, so that all power tubes in the charge pump branch circuit work according to the clock signal.

The scheme is that the duty ratio is regulated and controlled based on a simulation mode to realize parallel current sharing.

Further, the voltage-controlled oscillator comprises an NMOS tube, a plurality of inverters and a frequency divider; the drain electrode of the NMOS tube is connected with a power supply, the grid electrode of the NMOS tube is connected with the output end of the error amplifier, and the source electrode of the NMOS tube is connected with the positive power supply ends of all the phase inverters; all the phase inverters are sequentially connected in series, the negative power supply ends of all the phase inverters are grounded, the input end of the first phase inverter is connected with the output end of the last phase inverter, the output end of the last phase inverter is connected with the input end of the frequency divider, and the output end of the frequency divider outputs clock signals.

Further, the voltage-controlled oscillator comprises an operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a first NMOS transistor, a second NMOS transistor, a plurality of inverters and a frequency divider; the non-inverting input end of the operational amplifier is connected with the output end of the error amplifier, the directional input end of the operational amplifier is connected with the other end of the first resistor and one end of the second resistor, and the output end of the operational amplifier is connected with one end of the first resistor and the positive power supply ends of all the phase inverters; the other end of the second resistor is connected with the drain electrode of the first NMOS tube, the grid electrode of the first NMOS tube is connected with the first pulse control signal, the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, and the third resistor is connected between the drain electrode and the source electrode of the first NMOS tube; the grid electrode of the second NMOS tube is connected with a second pulse control signal, the source electrode of the second NMOS tube is grounded, and the fourth resistor is connected between the drain electrode and the source electrode of the second NMOS tube; all the phase inverters are sequentially connected in series, the negative power supply ends of all the phase inverters are grounded, the input end of the first phase inverter is connected with the output end of the last phase inverter, the output end of the last phase inverter is connected with the input end of the frequency divider, and the output end of the frequency divider outputs a clock signal; the resistance value of the first resistor is denoted as R1, the resistance value of a series circuit formed by the second resistor, the third resistor and the fourth resistor is denoted as R2, the output voltage Vsupply of the operational amplifier is (R1+ R2)/R2 × VC, and VC is the output voltage of the error amplifier, and the first pulse control signal and the second pulse signal are used for changing R2 by controlling the first NMOS transistor and the second NMOS transistor, so that the voltage output by the operational amplifier generates periodic small-amplitude ripples, and VC is not changed in the change period of the first pulse signal and the second pulse signal.

A charge pump parallel current-sharing circuit based on frequency control comprises N charge pumps connected in parallel, and is characterized by further comprising N frequency adjusting modules connected with the N charge pumps in sequence, wherein each frequency adjusting module comprises a logic circuit and a digital control oscillator, one input signal of the logic circuit is input current of a charge pump branch circuit connected with the frequency adjusting module after ADC (analog to digital converter) conversion, the other input signal of the logic circuit is output current of a charge pump parallel circuit of 1/2N after ADC conversion, the output end of the logic circuit is connected with the input end of the digital control oscillator, and a clock signal output by the digital control oscillator is used as a driving signal of a power tube in the corresponding charge pump branch circuit;

the scheme is that the duty ratio is regulated and controlled based on a digital mode to realize parallel current sharing.

The invention has the beneficial effects that: 1) by utilizing feedback, the equivalent impedance of the charge pump is changed by adjusting the frequency, and further, the output current equalization of the parallel work of the charge pump is realized. The scheme is suitable for the application of a charge pump with non-fixed frequency, and the energy concentration at a certain frequency point is avoided by frequency dithering. The scheme can be generalized to any conversion ratio of the charge pump architecture. 2) An analog implementation mode is provided, the error between the actual output current and the ideal output current is integrated, and the integrated voltage is converted into a clock signal through a voltage-controlled oscillator to adjust the working frequency of the charge pump. When the negative feedback is stable, the equivalent impedances of the parallel branches are matched with each other, and the parallel current sharing is realized. 3) Implementation of the numbers. The system comprises limited frequency options, and a bang-bang algorithm is utilized to ensure that the branch is switched between two adjacent frequencies near the ideal frequency in a stable state. And the average frequency approaches to the ideal working frequency when the branch impedances are matched, thereby realizing parallel current sharing. In addition, by changing the limit value of the logic counter, the inertia of the whole control system can be adjusted, and the balance of response speed and stability can be realized in different systems.

Drawings

FIG. 1 is a schematic diagram of a charge pump;

FIG. 2 is a schematic diagram of CFLY voltage at steady state;

FIG. 3 is a schematic diagram of the charge pump frequency dithering (five frequency steps);

FIG. 4 is a schematic diagram of the distribution of energy in the frequency domain when the charge pump is not jittered and jittered, wherein (a) the energy is concentrated on the switching frequency and its harmonics when the charge pump is not jittered, and (b) the energy concentrated on the switching frequency is uniformly distributed in the jittering frequency range after the charge pump is jittered;

FIG. 5 is a schematic diagram of a parallel configuration of a multi-branch charge pump;

FIG. 6 is a circuit for detecting input and output currents of a conventional charge pump charging chip;

FIG. 7 is a circuit diagram of parallel current sharing implemented by adjusting and controlling the operating frequency in a simulation manner;

FIG. 8 is a waveform diagram of parallel current sharing achieved by adjusting and controlling the operating frequency in a simulation manner;

fig. 9 is a circuit diagram and waveform diagram of a voltage controlled oscillator;

FIG. 10 is a circuit diagram and waveform diagram of a voltage controlled oscillator supporting a dithering function;

FIG. 11 is a circuit diagram of parallel current sharing implemented by digitally adjusting and controlling the operating frequency;

FIG. 12 is a clock circuit that can select a frequency by numbers to support a dithering function;

FIG. 13 is a logic control state diagram;

fig. 14 is a waveform diagram of parallel current sharing achieved by digitally adjusting and controlling the operating frequency (n is 2, four jitter frequency steps).

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings.

For the mobile phone charge pump fast charging system, for the convenience of implementation, the actual output current I _ OUTx of each chip is usually obtained indirectly by detecting the input current I _ INx of each chip (I _ OUTx is 2 × I _ INx), and the ideal output current I _ OUT _ REF of the chip is obtained indirectly by detecting the total charging current I _ OUT of the battery terminal (I _ OUT _ REF is I _ OUT/N).

As for how to adjust the "equivalent impedance" of the chip, it can be seen from the expression of equation 5 that the equivalent impedance of the charge pump is determined by three factors, i.e., the on-resistance of the power transistor, the capacitance of the CFLY capacitor, and the switching period (switching frequency). The CFLY capacitor is set from the outside of the system and is not controlled by the charge pump chip, so that the charge pump chip can utilize only two factors, namely, the on-resistance and the switching period (switching frequency) of the power tube. The scheme of the invention adjusts the equivalent impedance by changing the switching frequency.

For example, suppose that two charge pump chips are connected in parallel, wherein the external CFLY capacitance value of the charge pump chip of the first branch is smaller, and the parasitic resistance caused by the PCB routing is larger, so that the equivalent impedance of the charge pump of the first branch is larger, and thus more current flows out through the second branch during parallel operation. The working frequency of the charge pump of the two branches is adjusted through feedback, the working frequency of the first branch is slightly larger than that of the second branch, so that the equivalent impedance of the two branches is equal, and the output current of the two branches is equal, namely, the two branches are connected in parallel and flow equalized.

For the parallel connection of the charge pump chips with the frequency jittering function, the scheme can also be used for realizing the parallel current sharing. This is because sampling the average input and output current values requires filtering the switching frequency ripple of the current, so there is a delay in sampling the current; furthermore, for the stability of the negative feedback loop, it is usually necessary to make the frequency of the internal dominant pole much lower than the frequency of the sampling current, which is lower than the operating frequency, so the bandwidth of the feedback loop is much lower than the operating frequency. On the other hand, in order to achieve the best frequency-jittering effect, it is desirable that the frequency of the charge pump is changed quickly, and any adjacent working period has a different frequency, i.e. the frequency of the frequency-jittering cycle is slightly lower than the working frequency; in addition, usually, the frequency variation range of the jitter frequency is far smaller than the average operating frequency, i.e. (F _ switching _ max-F _ switching _ min) < < F _ switching.

The scheme of the invention is mainly a frequency-based current sharing scheme, is suitable for the application of a charge pump with non-fixed frequency, and supports avoiding energy concentration at a certain frequency point through frequency dithering, so that the current sharing scheme based on the duty ratio is suitable for the application of the charge pump with fixed frequency and supports the realization of small voltage current ripple by utilizing phase difference, which is different from the traditional parallel current sharing scheme based on duty ratio control. The specific difference is that if the current sharing is realized by adjusting the on-resistance of the power tube, the power tube cannot be fully turned on, which is a huge waste of resources. Most of the area of the chip is a power tube, and the purpose is to make the on-resistance of the power tube small, so that the heat generated when current flows is small. However, if the on-resistance of the power transistor is selected to realize current sharing, the power transistor is not fully turned on, and most of the chip area is wasted. And the mode of adjusting the switching period (switching frequency) is selected to realize current sharing, so that the power tube can be always kept in a fully conducting state, and waste in the aspect is not generated.

As described above, the input current of a single chip and the total output current of parallel chips can be detected by detecting common methods such as small-sized sense tube current and sense resistor voltage amplification. The present invention aims to equalize the output currents between different charge pump chips, i.e. the input current of each charge pump chip is equal to 1/2N of the total output current, where N is the number of chips connected in parallel. As shown in fig. 7, each charge pump chip integrates a loop for adjusting the frequency. This loop integrates the Error between the input current and the total output current of 1/2N, and then converts the accumulated Error Voltage VCx into a clock signal by a Voltage Controlled Oscillator (VCO), where the frequency of the clock is proportional to the accumulated Error Voltage VCx. And then the clock signal is sent to a driving circuit of the power tube, so that the power tube works according to the clock signal. The adjustment of the frequency changes the equivalent impedance, and further changes the input current of the chip, and the changed input current is fed back to the input end of the integrator to form a closed loop.

The feedback loop described above can be more intuitively understood from the perspective of the integrator output level VCx. As shown in fig. 8, if the initial input current I _ INx is less than 1/2N total output current, the integrators will cumulatively amplify their errors, resulting in a larger level of VCx. Because the clock frequency output by the VCO is proportional to the voltage of VCx, the increased voltage of VCx will increase the operating frequency, and the equivalent resistance of the charge pump branch circuit becomes smaller (see formula 5), thereby increasing the input current and completing negative feedback regulation. Since the output voltage of the integrator is finite and the gain of the error amplifier that constitutes the integrator is very high, the negative feedback stabilization allows the input voltage difference of the error amplifier to be small, i.e., the input current is equal to 1/2N of the total output current.

As mentioned previously, the output level of the integrator is proportional to the operating frequency. In practical applications, it is often necessary to limit the minimum and maximum operating frequencies of the charge pump. One simple way to achieve this is to limit the minimum and maximum levels of the error amplifier output.

Regarding the stability of the system. For each charge pump chip, if the input current detection module is fast enough, the feedback loop of a single chip has only one dominant pole, i.e., the output node of the integrator. The loop bandwidth can be set by adjusting the input transconductance of the error amplifier and the capacitance value of the VCx node. By setting the bandwidth at a fraction of the frequency of the other high frequency pole, loop stability is ensured. In addition, the overall stability problem when multiple charge pump chips are connected in parallel needs to be considered. Since the total output current is determined by all the parallel charge pump chips, the total output current is used as an input reference of each charge pump chip loop, and naturally affects each charge pump chip loop. One of the most straightforward approaches is not to feed the sensed total output current truly back to the respective error amplifier, but simply to set a fixed reference value. This cuts off the feedback loop of the total output current and naturally there is no stability problem. This is possible in most charging applications, since the actual charging is such that the total charging current closely follows the preset charging current profile over time. If the system is applied by feeding the total output current back to each error amplifier, it is usually necessary to perform low frequency filtering on the total output current, so that the change frequency of the total output current is expected to be much lower than the bandwidth of each sub-feedback loop, so that from the viewpoint of each sub-loop, the input of I _ OUT/2N can be considered as a "constant fixed value".

Fig. 9 is a circuit diagram and schematic diagram of a voltage controlled oscillator. An NMOS power tube forms a source follower, enables the Vsupply node to follow the voltage of the VC node and has driving capability. The inverter chain forms a simple ring oscillator to generate a high-frequency clock, and the high-frequency clock generates a clock signal sent to the power tube driving stage after being subjected to frequency reduction by the frequency divider. The clock frequency of the ring oscillator is approximately proportional to the Vsupply voltage, so the final clock frequency is approximately proportional to VC.

Fig. 10 adds a frequency jittering function to the voltage controlled oscillator. A voltage-voltage feedback loop is built through the op-amp to generate Vsupply, which is equal to (R1+ R2)/R2 VC. The diter <1:0> signal varies periodically as shown, thereby changing the resistance of R2, thereby causing Vsupply to produce a periodic small ripple. Since the Vsupply voltage is proportional to the oscillator frequency, the resulting clock signal produces a frequency-jittering effect. The variation frequency of Dither <1:0> is very high, namely the variation of VC voltage in the variation period of Dither <1:0> can be ignored, so the jitter frequency function does not affect the stability of the whole large loop.

If the system already contains digital information of the input current and the total output current of each chip, the frequency can be adjusted in a digital mode so as to realize parallel current sharing. As shown in fig. 11, a Digital Controlled Oscillator (DCO) selectively outputs clock signals of different frequencies according to a Digital input signal. How to select the frequency of the clock signal is obtained by the logic circuit operating with the total output current information I _ OUT _ ADC/2N of the input current information I _ INx _ ADC and 1/2N converted by the ADC.

A clock circuit supporting a dithering function, which can select a frequency by numbers, is shown in fig. 12. The core of the device is a ring oscillator formed by a delayer and an inverter, and a high-frequency clock generated by the ring oscillator is subjected to frequency reduction output after passing through a frequency divider. The frequency of the final output clock can be adjusted by adjusting the number of delays in the ring oscillator. The number of the delayers is determined by two groups of signals, one group is a frequency selection signal SEL < x:0>, and the average frequency of the final output clock is determined; the other group is a Dither selection signal Dither < y:0>, which determines the number of steps and the periodic variation rule of the Dither. The clock circuit is realized by pure numbers, and is simple and flexible.

The overall idea of logic control is simple, namely if the input current of a branch is less than the total output current of 1/2N, the frequency is increased to reduce the equivalent impedance of the charge pump branch, and further increase the input current of the branch; if the input current of a branch is larger than the total output current of 1/2N, the frequency is reduced to increase the equivalent impedance of the charge pump branch, and further reduce the input current of the branch. Taking into account that there is a certain delay from adjusting the clock frequency to the change of the input current, a counter is introduced in the logic in order to make the delay of adjusting the clock frequency larger than the delay of the change of the input current. As shown in fig. 13, the counter is cleared after each clock frequency adjustment. If the input current is greater than 1/2N total output current, the counter will subtract; conversely, if the input current is less than the total output current of 1/2N, the counter will add. When the value of the counter is accumulated to-n, the frequency gear which is nearest and is smaller than the current frequency gear is selected to be output; conversely, when the value of the counter is accumulated to n, the frequency range output which is the nearest and is larger than the current frequency range is selected, wherein n represents the "inertia" of the system, and can be flexibly set according to specific applications. The whole logic is synchronous logic, and the comparison of the current, the updating of the counter and the adjustment of the frequency all occur on the rising edge of the clock. If the system supports the frequency jittering function, the frequency jittering control is repeated according to the set periodicity, and the frequency control is independent of the frequency control.

A typical control waveform diagram is shown in fig. 14, taking the counter limit n as 2 as an example. Initially, the input current is less than the total output current of 1/2N, and the internal counter m is incremented on the rising edge of clk. When m is added to 2, SEL signal is added to 1, and the clock output with frequency higher by one gear is selected. After the frequency adjustment, the input current is still less than the total output current of 1/2N, and the process is repeated. Until the SEL signal increases to 5, at which time the input current is greater than the total output current of 1/2N, the internal counter m decrements on the rising edge of clk. When m is reduced to-2, SEL signal is reduced by 1, and the clock output with frequency less than one gear is selected. The SEL signal then switches between 4 and 5, with the input current switching between the two gears closest to 1/2N total output current, with the final average input current approximately equal to 1/2N total output current.

It is further understood that the digital control method is essentially the same as the analog control method described above. The comparison of the logic circuit to the input current and the total output current corresponds to an error amplifier in an analog control mode; the counter in the logic circuit corresponds to the capacitor connected with the output of the error amplifier in the analog mode; the digitally controlled oscillator corresponds to a voltage controlled oscillator in an analog mode. The difference is that the analog mode is continuous adjustment, the frequency can be any value, the digital mode is discrete, and the frequency is a limited number of choices; the analog mode is also continuous in time, and the digital mode is updated only at the edges of the clock.

Claims

1. A charge pump parallel current-sharing circuit based on frequency control comprises N charge pumps connected in parallel, and is characterized by further comprising N frequency adjusting modules respectively connected with the N charge pumps in sequence, wherein each frequency adjusting module comprises an error amplifier, a capacitor and a voltage-controlled oscillator, the non-inverting input end of the error amplifier is input current of a charge pump branch circuit connected with the frequency adjusting module, the inverting input end of the error amplifier is output current/2N of the charge pump parallel circuit, the output end of the error amplifier is connected with the input end of the voltage-controlled oscillator, and the connection point of the output end of the error amplifier and the input end of the voltage-controlled oscillator is grounded through the capacitor; the clock signal output by the voltage-controlled oscillator is used as a driving signal of a power tube in the corresponding charge pump branch circuit; the error amplifier is used for integrating the current of the charge pump branch circuit connected with the frequency adjusting module and the total output current of the 1/2N charge pump parallel circuit, converting the accumulated error voltage into a clock signal after passing through the voltage-controlled oscillator, and outputting the clock signal to the charge pump branch circuit connected with the frequency adjusting module, so that all power tubes in the charge pump branch circuit work according to the clock signal.

2. The parallel current sharing circuit of claim 1, wherein the voltage controlled oscillator comprises an NMOS transistor, a plurality of inverters and a frequency divider; the drain electrode of the NMOS tube is connected with a power supply, the grid electrode of the NMOS tube is connected with the output end of the error amplifier, and the source electrode of the NMOS tube is connected with the positive power supply ends of all the phase inverters; all the phase inverters are sequentially connected in series, the negative power supply ends of all the phase inverters are grounded, the input end of the first phase inverter is connected with the output end of the last phase inverter, the output end of the last phase inverter is connected with the input end of the frequency divider, and the output end of the frequency divider outputs clock signals.

3. The parallel current sharing circuit of claim 1, wherein the voltage controlled oscillator comprises an operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a first NMOS transistor, a second NMOS transistor, a plurality of inverters, and a frequency divider; the non-inverting input end of the operational amplifier is connected with the output end of the error amplifier, the directional input end of the operational amplifier is connected with the other end of the first resistor and one end of the second resistor, and the output end of the operational amplifier is connected with one end of the first resistor and the positive power supply ends of all the phase inverters; the other end of the second resistor is connected with the drain electrode of the first NMOS tube, the grid electrode of the first NMOS tube is connected with the first pulse control signal, the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, and the third resistor is connected between the drain electrode and the source electrode of the first NMOS tube; the grid electrode of the second NMOS tube is connected with a second pulse control signal, the source electrode of the second NMOS tube is grounded, and the fourth resistor is connected between the drain electrode and the source electrode of the second NMOS tube; all the phase inverters are sequentially connected in series, the negative power supply ends of all the phase inverters are grounded, the input end of the first phase inverter is connected with the output end of the last phase inverter, the output end of the last phase inverter is connected with the input end of the frequency divider, and the output end of the frequency divider outputs a clock signal; the resistance value of the first resistor is denoted as R1, the resistance value of a series circuit formed by the second resistor, the third resistor and the fourth resistor is denoted as R2, the output voltage Vsupply of the operational amplifier is (R1+ R2)/R2 × VC, and VC is the output voltage of the error amplifier, and the first pulse control signal and the second pulse signal are used for changing R2 by controlling the first NMOS transistor and the second NMOS transistor, so that the voltage output by the operational amplifier generates periodic small-amplitude ripples, and VC is not changed in the change period of the first pulse signal and the second pulse signal.

4. A charge pump parallel current-sharing circuit based on frequency control comprises N charge pumps connected in parallel, and is characterized by further comprising N frequency adjusting modules connected with the N charge pumps in sequence, wherein each frequency adjusting module comprises a logic circuit and a digital control oscillator, one input signal of the logic circuit is input current of a charge pump branch circuit connected with the frequency adjusting module after ADC (analog to digital converter) conversion, the other input signal of the logic circuit is output current of a charge pump parallel circuit of 1/2N after ADC conversion, the output end of the logic circuit is connected with the input end of the digital control oscillator, and a clock signal output by the digital control oscillator is used as a driving signal of a power tube in the corresponding charge pump branch circuit;

the specific method for generating the clock signal by the logic circuit comprises the following steps: the logic circuit comprises a ring oscillator, a frequency divider and a counter, wherein the ring oscillator is composed of a delayer, a multiplexer and an inverter, a high-frequency clock generated by the ring oscillator is subjected to frequency reduction output after passing through the frequency divider, and the frequency of a final output clock is adjusted by adjusting the number of the delayers in the ring oscillator; the output of each delayer is connected with one input of the multiplexer, that is, the multiplexer is used for selectively outputting different frequency signals, the different frequency signals are defined as a plurality of frequency steps, and then the method for controlling the multiplexer to select the frequency steps by the logic circuit is as follows: judging whether the input current is larger than 1/2N total output current, if so, subtracting the counter, otherwise, adding the counter, and when the value of the counter is accumulated to-N, selecting the frequency which is the nearest and the frequency gear is smaller than the current frequency gear for output; on the contrary, when the value of the counter is accumulated to n, the frequency output which is the nearest and the frequency gear is larger than the current frequency gear is selected, and after the frequency is adjusted, the counter is cleared.