CN212542424U - Semiconductor device with a plurality of transistors - Google Patents

Semiconductor device with a plurality of transistors Download PDF

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Publication number
CN212542424U
CN212542424U CN202021330932.XU CN202021330932U CN212542424U CN 212542424 U CN212542424 U CN 212542424U CN 202021330932 U CN202021330932 U CN 202021330932U CN 212542424 U CN212542424 U CN 212542424U
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China
Prior art keywords
metal
circuit
semiconductor device
substrate
pad
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CN202021330932.XU
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Chinese (zh)
Inventor
戴建业
韦仕贡
刘伟
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Beijing Yandong Microelectronic Technology Co ltd
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Beijing Yandong Microelectronic Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Abstract

The utility model discloses a semiconductor device, include: a substrate having opposing first and second surfaces; a circuit function layer on the first surface of the substrate, the circuit function layer including a wiring layer; the circuit layer lead points, the metal columns and the metal bonding pads are sequentially arranged in the openings along the direction from the first surface to the second surface; the metal column is electrically connected with the wiring layer through the circuit layer lead point, and the metal pad is exposed through the second surface and used for electrically connecting the metal column with an external circuit. According to the semiconductor device, the metal column in the substrate, and the circuit layer lead points and the metal bonding pads on two sides of the metal column are used for realizing the electric connection between the wiring layer and an external circuit, so that the semiconductor device can be miniaturized.

Description

Semiconductor device with a plurality of transistors
Technical Field
The utility model relates to a microelectronics technical field. And more particularly, to a semiconductor device.
Background
In the field of microelectronics, a semiconductor device is a miniature electronic device or component, which is generally manufactured by integrating components such as diodes, transistors, resistors, capacitors and the like required by a circuit with certain functions and connecting wires among the components on a small silicon wafer or other semiconductor materials through a series of semiconductor manufacturing processes such as epitaxy, oxidation, photoetching, diffusion/ion implantation, deposition, metallization and the like, then electrically connecting the components with a circuit substrate or a lead frame through welding or other modes, and finally packaging the components.
Fig. 1 and 2 show two typical device packaging forms, wherein fig. 1 adopts wire bonding (wire bonding) technology, and fig. 2 shows Flip-Chip (Flip-Chip) technology. As shown in fig. 1, the front surface (i.e., the surface on which the circuit functional layer is formed) of the chip faces upward, and the back surface is attached to the lead frame (or the circuit substrate); the front surface of the chip is provided with a plurality of PADs (PADs), and the PADs are electrically connected with the PADs on the lead frame (or the circuit substrate) through metal bonding wires. As shown in fig. 2, the chip is faced down and faces the lead frame (or circuit substrate), and PADs on the chip are electrically connected to PADs on the lead frame (or circuit substrate) through metal posts or the like.
In both of the two packaging forms, a wiring layer and a bonding pad are required to be arranged on the front surface of the chip, and then the chip is electrically connected with a lead frame (or a circuit substrate) through a metal bonding wire or a metal column, so that the conduction between a circuit function layer and an external circuit is realized, and the semiconductor device has corresponding functions. However, with the package shown in fig. 1, the chip and the lead frame (or the circuit substrate) are electrically connected by the metal bonding wire, which requires additional area of the lead frame (or the circuit substrate), and this structure is not only disadvantageous to the miniaturization of the semiconductor device, but also increases the reliability risk of the circuit. In the package shown in fig. 2, the chip and the lead frame (or the circuit board) are electrically connected by the metal posts, which increases the thickness of the semiconductor device and is also not favorable for miniaturization of the semiconductor device.
In view of the above, there is a need to provide a novel semiconductor device, which does not increase the size of the semiconductor device substantially on the premise of ensuring the realization of the application function of the semiconductor device, so as to meet the development requirement of miniaturization of the device at present.
SUMMERY OF THE UTILITY MODEL
In order to solve the above problem, the utility model provides a semiconductor device can be favorable to realizing the miniaturization of device.
To achieve the above object, the present invention provides a semiconductor device, including: a substrate having opposing first and second surfaces; a circuit function layer on the first surface of the substrate, the circuit function layer including a wiring layer; the circuit layer lead points, the metal columns and the metal bonding pads are sequentially arranged in the openings along the direction from the first surface to the second surface; the metal column is electrically connected with the wiring layer through the circuit layer lead point, and the metal pad is exposed through the second surface and used for electrically connecting the metal column with an external circuit.
Further, the semiconductor device further includes a lead frame, the second surface of the substrate is attached to the lead frame, and the metal pad electrically connects the metal pillar to an external circuit through the lead frame.
Furthermore, the semiconductor device further comprises a circuit substrate, the second surface of the substrate is attached to the circuit substrate, and the metal pad electrically connects the metal column with an external circuit through the circuit substrate.
Further, the metal pad is an aluminum pad, a titanium pad or a tungsten pad.
Further, the orthographic projection of the lead points of the circuit layer on the first surface covers the orthographic projection of the metal columns on the first surface.
Further, the orthographic projection area of the lead points of the circuit layer on the first surface is larger than that of the metal columns on the first surface.
Furthermore, the circuit layer lead points are aluminum pads, titanium pads or tungsten pads.
Further, the metal pillar is a silver-containing pillar.
Further, the thickness of the metal pad is not less than 10 μm; the thickness of the lead points of the circuit layer is 0.8-10 μm; the height of the metal pillars is 50 μm to 300 μm.
The utility model has the advantages as follows:
the utility model provides a semiconductor device, through set up the opening in the substrate, and set up the metal cylinder in the opening, and set up circuit layer lead wire point and metal pad in metal cylinder both sides, make the wiring layer in the circuit function layer loop through circuit layer lead wire point, metal cylinder and metal pad and be connected with external circuit electricity, and need not be with the help of traditional metal bonding wire, also need not to occupy the area of lead frame or circuit substrate; and because the metal column is buried in the substrate deeply, the thickness of the semiconductor device is not increased basically. Therefore, the utility model provides a semiconductor device has less size, satisfies the miniaturized development trend and the requirement of current semiconductor device.
Drawings
The following detailed description of the embodiments of the present invention is provided with reference to the accompanying drawings:
FIG. 1 illustrates a schematic diagram of a semiconductor device currently packaged using wire bonding techniques;
FIG. 2 illustrates a schematic diagram of a current flip chip technology for packaging a semiconductor device;
fig. 3 illustrates a top view of a semiconductor device according to an embodiment of the present application;
fig. 4 shows a longitudinal cross-sectional view of a semiconductor device according to an embodiment of the present application;
fig. 5 to 9 are longitudinal sectional views of main steps of forming a semiconductor device in an embodiment of the present application, respectively.
Description of reference numerals:
201-a wiring layer; 203-a substrate;
203' -wafer; 205-metal pads;
207-metal cylinder; 209-circuit layer lead points;
211-a lead frame; 213-opening.
Detailed Description
In order to explain the present invention more clearly, the present invention will be further described with reference to the preferred embodiments and the accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not to be taken as limiting the scope of the invention.
The structure of the semiconductor device and the manufacturing process thereof in the embodiment of the present application are described in detail below with reference to fig. 3 to 9.
In the top view of the semiconductor device shown in fig. 3, an outermost circled solid frame is used to indicate a substrate 203 of the semiconductor device, and a solid frame inside the outermost circled solid frame indicates a wiring layer 201 in a circuit function layer; a plurality of dashed boxes overlapping the wiring layer 201 represent a plurality of openings 213 formed in the substrate 203, and the regions within the dashed boxes represent circuit layer lead points 209 in the openings 213.
With reference to fig. 3 and 4, a semiconductor device provided by the embodiment of the present application includes a substrate 203 and a circuit function layer. Wherein the substrate 203 has a first surface and a second surface opposite to each other, the circuit function layer is located on the front surface of the substrate 203 (the first surface of the substrate 203 is commonly referred to as "front surface" in the industry, and the second surface is "back surface"), and the circuit function layer includes the wiring layer 201. A plurality of openings 213 are formed in the substrate 203, and the openings 213 are arranged in the direction of the thickness of the substrate 203. In the opening 213 are sequentially disposed a metal pad 205, a metal pillar 207, and a circuit layer lead dot 209. Wherein the metal pad 205 is exposed through the back side of the substrate 203 to facilitate electrical connection with an external circuit; the metal pillar 207 is electrically connected to an external circuit through the metal pad 205; the circuit layer lead points 209 face the circuit function layer, and the circuit layer lead points 209 are electrically connected with the wiring layer 201, so that the metal posts 207 are electrically connected with the wiring layer 201 through the circuit layer lead points 209. With the above configuration, the lead layer 201 is electrically connected to an external circuit through the circuit layer lead dots 209, the metal posts 207, and the metal pads 205 in the openings 213 in this order.
According to the semiconductor device of the embodiment of the present application, the electrical connection between the lead layer 201 and the external circuit is realized by forming the deeply buried metal pillar 207 and the metal pad 205 and the circuit layer lead point 209 at both sides thereof in the substrate 203. With the above structure, it is no longer necessary to connect with the external circuit by the conventional metal bonding wire, and the lead frame 211 (or the circuit substrate) is not occupied. And compared with the traditional Flip-Chip technology, the thickness of the semiconductor device is not increased basically, so that the miniaturization of the semiconductor device is realized.
In addition, the problem of reliability risk caused by metal bonding wires in the traditional wire bonding technology is avoided just because the metal bonding wires are not needed. The electrical connection between the wiring layer 201 and an external circuit is realized by means of the deeply buried metal pillar 207, and the stability of the transmission of the I/O signal of the semiconductor device can be improved, so that the reliability of the product is improved.
It should be noted that the shape and number of the openings 213 are not particularly limited in this embodiment, and those skilled in the art can reasonably determine the number and shape of the openings 213 and the layout in the substrate 203 according to the actual size of the semiconductor device, the functional requirements of the circuit function layers, and the like. Accordingly, the size of the metal pillar 207 can be selected according to specific situations, and the radial shape, size and axial length (i.e. height) of the metal pillar are not particularly limited in this embodiment, as long as the metal pillar can be sufficiently contacted with the metal pad 205 and the circuit layer lead point 209 on both sides thereof to form a good electrical connection.
The dimensions of the metal pad 205, the metal pillar 207 and the circuit layer lead point 209 are not particularly limited in this embodiment. The height of the metal pillars 207 may be determined reasonably according to the material and thickness of the substrate 203, and may be, for example, 50 μm to 300 μm. The size of the circuit layer lead point 209 can refer to the conventional size of a PAD (PAD), for example, the thickness of the circuit layer lead point 209 can be 0.8-10 μm, preferably 0.8-4 μm. In one embodiment, the circuit layer lead PADs 209 are aluminum PADs having an average thickness of about 2 μm. The thickness of the metal pad 205 may be controlled to be generally 10 μm or more. It should be understood by those skilled in the art that the present application is not limited thereto, and the dimensions of the metal pad 205, the metal pillar 207 and the circuit layer lead point 209 may be adjusted appropriately according to the performance requirements of the semiconductor device, and the like, and the size of the opening 213 may be adjusted adaptively.
Preferably, the orthographic projection of the circuit layer lead dots 209 on the front surface of the substrate 203 covers the orthographic projection of the metal posts 207 on the front surface of the substrate 203, that is, the orthographic projection area of the circuit layer lead dots 209 on the front surface of the substrate 203 is not smaller than the orthographic projection area of the metal posts 207 on the front surface of the substrate 203, so that the circuit layer lead dots 209 are ensured to have a size large enough to be in sufficient contact with the metal posts 207, and good and sufficient electrical connection can be formed between the wiring layer 201 and the metal posts 207. More preferably, the area of the circuitry layer lead pads 209 that is orthographically projected on the front side of the substrate 203 is larger than the area of the metal posts 207 that is orthographically projected on the front side of the substrate 203.
According to an embodiment of the present application, the metal pads 205 are used to make electrical connections between the metal pillars 207 and external circuitry. In this embodiment, a specific material of the metal pad 205 is not particularly limited, and a metal or an alloy material used in a pad in the art, such as aluminum, titanium, or tungsten, may be used, and accordingly, the metal pad 205 may be an aluminum pad, a titanium pad, or a tungsten pad.
According to the embodiment of the present application, the circuit layer lead pads 209 are used to electrically connect with the circuit wiring layer 201 and the metal posts 207, respectively, and finally realize the corresponding functions of the circuit function layer, so that the circuit layer lead pads 209 also actually correspond to the bonding pads. Thus, circuit layer lead pads 209 may be any conductive material, such as aluminum, titanium, tungsten, etc., that is capable of electrically connecting the corresponding leads in lead layer 201 to an external circuit.
Further, the aforementioned semiconductor device may further include a lead frame 211 (simply referred to as "frame"). Specifically, the back surface of the substrate 203 is attached to the surface of the lead frame 211, and the metal PAD 205 is electrically connected to a PAD on the lead frame 211, so that the wiring layer 201 is electrically connected to an external circuit via the lead frame 211.
Alternatively, the semiconductor device may further include a circuit board (also referred to as a "circuit board") through which the wiring layer 201 is electrically connected to an external circuit. A typical Circuit substrate may be, for example, a Printed Circuit Board (PCB). The specific connection manner between the circuit board and the substrate 203 can refer to the foregoing description about the lead frame 211, and is not repeated.
In the present embodiment, specific specifications of the lead frame 211 and the circuit substrate are not particularly limited, and the lead frame 211 or the circuit substrate may be selected to be adapted according to the functional requirements and the size of the semiconductor device.
In order to further clearly embody the structural features and advantages of the semiconductor device according to the present application, an exemplary fabrication process of the semiconductor device according to the present application is described below with reference to fig. 5 to 9.
As shown in fig. 5, in step S1, before the functional circuit layer is formed on the wafer 203 ', a plurality of openings 213 are formed on one surface (also referred to as "front surface") of the wafer 203'.
The type and specification of the wafer 203' are not particularly limited in this embodiment, and suitable semiconductor materials and suitable dimensions may be selected according to factors such as actual performance requirements and processing level of the semiconductor device.
In this embodiment, the forming manner of the opening 213 is not particularly limited, and conventional techniques in the art, such as laser, mechanical grooving, or chemical etching, may be adopted, but the method is not limited thereto, and an appropriate technique may be specifically selected according to the material, thickness, and other factors of the wafer 203'. In addition, the depth of the opening 213 should be equivalent to the sum of the axial length of the metal pillar 207 as a lead post, the thickness of the circuit layer lead point 209, and the thickness of the metal pad 205.
Those skilled in the art will appreciate that the location of the opening 213 corresponds to the location where the metal pad 205 is to be formed on the wafer 203' as a chip I/O pin.
Referring next to fig. 6, in step S2, metal pads 205, metal posts 207, and circuit layer lead pads 209 are sequentially formed in the openings 213.
The specific forming process of the metal pad 205, the metal pillar 207 and the circuit layer lead point 209 is not particularly limited in this embodiment, and an appropriate process may be adopted according to the performance requirement of the device. Metal may be deposited, such as by metal sputtering, deposition, or electroplating, to form a deep buried metal pad 205 within opening 213.
For the metal cylinder 207, a full or semi-sintered glue may be applied into the opening 213, resulting in the metal cylinder 207. Currently, the fully sintered or semi-sintered adhesive commonly used in the microelectronics field contains silver metal, so the finally formed metal pillar 207 is a silver-containing pillar. Of course, other matching processes may also be used to fabricate the metal pillar 207, so as to obtain a copper pillar or a metal pillar or an alloy pillar made of other materials.
As mentioned above, the circuit layer lead pads 209 may actually be regarded as bonding pads, and the specific formation process thereof may adopt a bonding pad formation process in the art, such as a formation process of the reference metal bonding pad 205, including but not limited to metal sputtering, deposition, and the like. The circuit layer pads 209 may also be made of materials commonly used in current bonding pads, including but not limited to aluminum, titanium, and tungsten.
After the metal pads 205, the metal posts 207, and the circuit layer lead pads 209 are formed, referring to fig. 7, in step S3, a circuit function layer including the wiring layer 201 is formed on the surface of the wafer 203' where the openings 213 are formed. The specific preparation process of the circuit functional layer in this embodiment is not particularly limited, and epitaxy, oxidation, photolithography, ion implantation, deposition, and the like may be performed according to the functional requirements of the semiconductor device by conventional means in the art, which is not described in detail.
As shown in fig. 8, according to the embodiment of the present application, in step S4, the surface (i.e., the back surface) of the wafer 203' where the wiring layer 201 is not formed is thinned to expose the metal pads 205, and then dicing (colloquially referred to as "dicing") is performed to obtain unit chips (die). The thinning can specifically adopt a grinding process. It will be appreciated that the polishing parameters should take into account the total thickness of the metal pads 205, metal posts 207, and circuit layer lead pads 209, as well as the thickness of the wafer 203' to sufficiently expose the metal pads 205 to facilitate electrical connection to external circuitry; the back side of the polished wafer 203' serves as the PAD side of the unit chip.
As shown in fig. 9, the step of fabricating the semiconductor device according to the embodiment of the present application may further include step S5: the unit chips are mounted onto the lead frame 211 through the exposed metal pads 205. Specifically, the solder paste may be printed on the PAD Surface of the lead frame 211 by using a steel mesh printing, and then the unit chip is Mounted on the PAD Surface of the lead frame 211 by using a Surface Mount Technology (SMT), so that the metal PAD 205 can be connected to an external circuit through the lead frame 211.
Alternatively, the unit chip may be mounted on the PAD surface of the circuit board so that the metal PAD 205 can be electrically connected to an external circuit through the circuit board. For the specific process, reference may be made to the foregoing content related to the lead frame 211, and details are not repeated.
The above embodiment only schematically shows one forming manner of the semiconductor device, and actually other process routes may be taken, for example, as for the circuit layer lead pads 209, the RDL wiring technology may be referred to, and the wiring layer 201 is formed on the surface (front side) of the wafer 203', and the wiring layer 201 is electrically connected to the metal pillars 207 through the circuit layer lead pads 209.
For another example, for the metal pad 205, a blind via may be formed on the front surface of the wafer 203' as a first opening, and then the metal pillar 207 and the circuit layer lead point 209 are sequentially formed in the first opening; then, a circuit function layer is manufactured on the front side of the wafer 203 ', and the back side of the wafer 203' is ground without exposing the metal column 207; then, a second opening is formed on the back side of the ground wafer 203', the second opening is controlled to correspond to the first opening, so that the second opening and the first opening together form an opening 213 penetrating through the substrate 203, and finally, a metal pad 205 is formed in the second opening.
Therefore, the semiconductor device provided by the embodiment has a simple preparation process, and compared with the traditional Flip-Chip technology, the semiconductor device has relatively low requirement on the precision of equipment, so that the process difficulty is low.
Obviously, the above embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it is obvious for those skilled in the art to make other variations or changes based on the above descriptions, and all the embodiments cannot be exhausted here, and all the obvious variations or changes that belong to the technical solutions of the present invention are still in the protection scope of the present invention.

Claims (9)

1. A semiconductor device, comprising:
a substrate having opposing first and second surfaces;
a circuit functional layer on the first surface of the substrate, the circuit functional layer including a wiring layer;
the plurality of openings are positioned in the substrate, and circuit layer lead points, metal columns and metal bonding pads are sequentially arranged in the openings along the direction from the first surface to the second surface;
the metal column is electrically connected with the wiring layer through a circuit layer lead point, and the metal pad is exposed through the second surface and used for electrically connecting the metal column with an external circuit.
2. The semiconductor device of claim 1, further comprising a lead frame, wherein the second surface of the substrate is attached to the lead frame, and wherein the metal pad electrically connects the metal post to an external circuit through the lead frame.
3. The semiconductor device of claim 1, further comprising a circuit substrate, wherein the second surface of the substrate is attached to the circuit substrate, and wherein the metal pad electrically connects the metal post to an external circuit through the circuit substrate.
4. The semiconductor device according to any one of claims 1 to 3, wherein the metal pad is an aluminum pad, a titanium pad, or a tungsten pad.
5. The semiconductor device of claim 1, wherein an orthographic projection of the circuit layer lead points on the first surface covers an orthographic projection of the metal posts on the first surface.
6. The semiconductor device of claim 5, wherein an orthographic area of the circuit layer feedthroughs on the first surface is greater than an orthographic area of the metal posts on the first surface.
7. The semiconductor device according to any one of claims 1 to 3, wherein the circuit layer terminal points are aluminum pads, titanium pads, or tungsten pads.
8. The semiconductor device according to any one of claims 1 to 3, wherein the metal pillar is a silver-containing pillar.
9. A semiconductor device according to any one of claims 1 to 3, wherein the thickness of the metal pad is not less than 10 μm; the thickness of the circuit layer lead points is 0.8-10 μm; the height of the metal pillar is 50 μm to 300 μm.
CN202021330932.XU 2020-07-08 2020-07-08 Semiconductor device with a plurality of transistors Active CN212542424U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202021330932.XU CN212542424U (en) 2020-07-08 2020-07-08 Semiconductor device with a plurality of transistors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202021330932.XU CN212542424U (en) 2020-07-08 2020-07-08 Semiconductor device with a plurality of transistors

Publications (1)

Publication Number Publication Date
CN212542424U true CN212542424U (en) 2021-02-12

Family

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Country Status (1)

Country Link
CN (1) CN212542424U (en)

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