CN212412050U

CN212412050U - Metal oxide array substrate

Info

Publication number: CN212412050U
Application number: CN202021500812.XU
Authority: CN
Inventors: 刘翔
Original assignee: Chengdu CEC Panda Display Technology Co Ltd
Current assignee: Chengdu BOE Display Technology Co Ltd
Priority date: 2020-07-27
Filing date: 2020-07-27
Publication date: 2021-01-26
Anticipated expiration: 2030-07-27

Abstract

The utility model provides a metal oxide array substrate, which comprises a main pixel electrode, an auxiliary pixel electrode, a first drain electrode, a second drain electrode and a grid scanning line, wherein the main pixel electrode and the auxiliary pixel electrode are arranged side by side; the grid scanning line is positioned in a gap between the main pixel electrode and the auxiliary pixel electrode, the first drain electrode is positioned between the main pixel electrode and the grid scanning line, the second drain electrode is positioned between the auxiliary pixel electrode and the grid scanning line, the first drain electrode and the second drain electrode are symmetrical about a first straight line, and the first straight line is superposed with the central line of the grid scanning line. The utility model provides a metal oxide array substrate, the total sum of the area of the overlap region of grid scanning line and first drain electrode, second drain electrode remains unchanged for grid-drain electrode parasitic capacitance's size can remain unchanged, has avoided because the picture that parasitic capacitance Cgd's change and arouse shows inequality and scintillation problem.

Description

Metal oxide array substrate

Technical Field

The utility model relates to a liquid crystal display technology field especially relates to a metal oxide array substrate.

Background

The liquid crystal display includes a plurality of display modes such as a Twisted Nematic (TN) mode, an Electronically Controlled Birefringence (ECB) mode, an in-plane switching mode (IPS), and a Vertical Alignment (VA), in which the VA mode is a common display mode having advantages such as high contrast, wide viewing angle, and rubbing-free alignment.

At present, a VA pixel design of 3T _8domain (8-domain 3 transistor) is generally adopted, so that the rotation angles of liquid crystal molecules of 4 domains of a main region and 4 domains of a secondary region in the same sub-pixel are different, thereby improving color shift. A conventional thin film transistor includes a gate electrode, a source electrode, and a drain electrode. Generally, the gate extends to the gate scan line to receive the scan signal, and is defined by the first metal layer together with the gate scan line. The source and drain electrodes are separated by the channel and defined by the second metal layer together with the data line.

However, when the first metal layer and the second metal layer are offset relatively in the manufacturing process, the gate-source parasitic capacitance and the gate-drain parasitic capacitance are changed, and thus, the defects of the display panel, such as image flicker and image sticking, are caused.

SUMMERY OF THE UTILITY MODEL

To address the above-mentioned drawbacks in the prior art, the present invention provides a metal oxide array substrate, which includes a main pixel electrode and a sub-pixel electrode disposed side by side, a first drain electrode electrically connected to the main pixel electrode, a second drain electrode electrically connected to the sub-pixel electrode, and a gate scan line; the gate scan line is located in a gap between the main pixel electrode and the sub-pixel electrode, the first drain electrode is located between the main pixel electrode and the gate scan line, the second drain electrode is located between the sub-pixel electrode and the gate scan line, and the first drain electrode and the second drain electrode are symmetrical with respect to a first straight line, which coincides with a center line of the gate scan line.

In one possible implementation manner, the first drain electrode and the second drain electrode share the same first active region and the first source electrode, the first source electrode is electrically connected with the data line and is parallel to the gate scanning line, and a center line of the first source electrode coincides with the first straight line.

In one possible implementation manner, the length of the first active region in a direction perpendicular to the gate scan line is greater than the width of the gate scan line.

In one possible implementation manner, in a direction perpendicular to the gate scan line, a length of an overlapping region of the first drain and the gate scan line is equal to a length of the first drain, and a length of an overlapping region of the second drain and the gate scan line is equal to a length of the second drain.

In one possible implementation manner, in a direction perpendicular to the gate scan line, a length of an overlapping region of the first drain and the first active region is equal to a length of the first active region, and a length of an overlapping region of the second drain and the first active region is equal to a length of the first active region.

In one possible implementation manner, the semiconductor device further includes a second source electrode and a third drain electrode which are arranged in parallel, and a second active region located between the second source electrode and the third drain electrode;

the second source electrode is electrically connected with the first drain electrode, and the third drain electrode is electrically connected with a capacitor;

the second active region is parallel to the grid scanning line and is overlapped with the grid scanning line;

the second source electrode and the third drain electrode are symmetrical with respect to a second straight line parallel to a center line of the data line.

In one possible implementation manner, the width of the second active region is smaller than the width of the gate scan line.

In one possible implementation manner, the first drain electrode and the second source electrode are arranged on the same layer.

In one possible implementation, the first drain electrode and the second source electrode are formed as a unitary structure.

In one possible implementation manner, the third drain and the second source are perpendicular to the gate scan line and both end portions of the third drain and the second source extend beyond the gate scan line.

The utility model provides a metal oxide array substrate, through setting up first drain electrode and second drain electrode, and through first drain electrode and second drain electrode central line symmetry about the grid scanning line, make, when skew takes place for first metal level and second metal level, grid scanning line and first drain electrode, the total sum of the overlapping region's of second drain electrode area remains unchanged, make grid-drain electrode parasitic capacitance's size can remain unchanged, avoided because the picture that parasitic capacitance Cgd's change arouses shows uneven and scintillation problem, make the inside shared capacitance evenly distributed of metal oxide array substrate, improve whole liquid crystal display panel's picture display quality.

In addition to the technical problems, technical features constituting technical aspects, and advantageous effects brought by the technical features of the technical aspects described above, other technical problems, technical features included in technical aspects, and advantageous effects brought by the technical features that can be solved by the embodiments of the present invention will be described in further detail in the detailed description.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.

Fig. 1 is a schematic plan view of a part of a pixel unit in a conventional array substrate;

fig. 2 is a schematic plan view of a portion of a first metal layer of a pixel region of a metal oxide array substrate according to an exemplary embodiment;

FIG. 3 is a schematic plan view of FIG. 2 with semiconductor layers added;

FIG. 4 is a schematic plan view of FIG. 3 with the addition of a second metal layer;

FIG. 5 is a schematic plan view of FIG. 4 with an additional pixel electrode layer;

fig. 6 is a circuit diagram of a pixel region of a metal oxide array substrate according to an exemplary embodiment.

Description of reference numerals:

21. a gate scan line; 211. a first portion; 212. a second portion; 22. a first electrode plate;

31. a first active region; 32. a second active region;

41. a data line; 42. a first drain electrode; 43. a second drain electrode; 44. a first source electrode; 45. a third drain electrode; 46. a second source electrode; 47. a second electrode plate;

5. a contact hole;

61. a main pixel electrode; 62. a sub-pixel electrode;

101. a gate electrode; 102. a source electrode; 103. a drain electrode; 104. scanning a line; 105. a data line; 106. a pixel electrode; 107. a semiconductor active layer.

With the above figures, certain embodiments of the present invention have been shown and described in more detail below. The drawings and the description are not intended to limit the scope of the inventive concept in any way, but rather to illustrate the inventive concept by those skilled in the art with reference to specific embodiments.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention.

Fig. 1 is a schematic plan view of a part of a pixel unit in a conventional array substrate, and as shown in fig. 1, a thin film transistor includes a gate 101, a source 102 and a drain 103. The gate 101 extends to the scan line 104 to receive a scan signal, and is defined by the first metal layer together with the scan line 104. The source and drain

electrodes

102 and 103 are separated by a channel and defined by a second metal layer together with the data line 105. The source 102 extends to the data line 105 to receive a data signal; the drain electrode 103 is connected to the pixel electrode 106 through a contact hole. Between the first metal layer and the second metal layer there is a semiconductor active layer 107. The region of overlap between the gate 101 and the source 102 has a gate 101-source 102 parasitic capacitance Cgs, and the region of overlap between the gate 101 and the drain 103 has a gate 101-drain 103 parasitic capacitance Cgd. When the first metal layer and the second metal layer are shifted relative to each other (as shown by the dotted line in fig. 1, the second metal layer is shifted leftward relative to the first metal layer) during the manufacturing process, the areas of the overlapping regions of the gate 101 and the source 102 and the gate 101 and the drain 103 are changed, so that the gate 101-source 102 parasitic capacitance Cgs and the gate 101-drain 103 parasitic capacitance Cgd are changed. This change may indirectly affect the voltage on the pixel electrode 106. Because the tft has parasitic capacitance, at the moment of ending the scanning, the voltage actually applied to the pixel electrode 106 is pulled down, and the voltage difference Δ Vp pulled down is: Δ Vp ═ Vgl-Vgh) × Cgd/(Cgd + Cst + Clc); here, Vgl and Vgh respectively represent voltages at the gate electrode 101 when the thin film transistor is turned on and off, and Cgd, Cst, and Clc respectively represent gate electrode 101 to drain electrode 103 parasitic capacitances of the thin film transistor, a storage capacitance of the pixel, and a liquid crystal capacitance.

As can be seen from the above equation, different Cgd results in different pixel electrode 106 voltages. The conventional Cgd mainly depends on the structural design of the thin film transistor and the pair accuracy of the gate 101 metal and the source and drain 103 metal of the array substrate. Due to limitations of objective conditions such as a manufacturing process, the accuracy of the pair is distributed within the array substrate to a certain degree, and thus the Cgd of each pixel unit within the array substrate varies. This difference causes uneven distribution of Δ Vp in each pixel electrode 106 in the panel, and further causes defects such as flicker and afterimage to be displayed on the screen of the panel.

Therefore, a plurality of drains may be disposed, so that when the gate electrode and the source electrode and the drain electrode are relatively shifted due to the process deviation of the pair, the total area of the overlapping regions of the gate electrode and the plurality of drain electrodes is kept unchanged, and the total area of the overlapping regions of the semiconductor active layer and the plurality of drain electrodes is kept unchanged, so that the parasitic capacitance between the gate electrode and the drain electrode of the thin film transistor can be kept unchanged, thereby avoiding the display unevenness caused by the variation of Cgs, not affecting the aperture ratio and the brightness of the liquid crystal display device, achieving the uniformity of the display screen, and improving the yield of the product.

The following describes a metal oxide array substrate provided by the present invention with reference to the accompanying drawings. First, the present application is designed based on the case where the pixel region has an eight-domain structure. The eight-domain structure means that one pixel region is divided into two sub-pixel regions, and the two sub-pixel regions have different shades.

First, a layer structure of the metal oxide array substrate will be described. It should be noted that the metal oxide array substrate of the present application can be used in, but not limited to, liquid crystal, OLED, Mini-LED, Macro-LED display technologies.

Fig. 2 is a schematic plan view of a portion of the first metal layer in the pixel region of a metal oxide array substrate according to an exemplary embodiment, as shown in fig. 2, the metal oxide array substrate includes a substrate and gate scan lines 21. The substrate base plate is positioned at the bottom of the metal oxide array base plate. The gate scan lines 21 are deposited on the substrate, and a plurality of gate scan lines 21 may be disposed on the same layer to form a first metal layer.

As shown in fig. 3, a semiconductor layer is stacked over the first metal layer in order to form a channel between the gate electrode and the drain electrode, which will be described later. Wherein the semiconductor layer comprises a first active region 31.

As shown in fig. 4, a data line 41 is disposed above the gate scan line 21. In the metal oxide array substrate, a plurality of data lines 41 may be disposed at intervals, and the data lines 41 and the gate scan lines 21 may be spatially staggered in a horizontal direction and a vertical direction so as to form a plurality of pixel regions. One pixel region is divided into upper and lower two sub-pixel regions, that is, one pixel region is divided into upper and lower two sub-pixel regions by a common gate scan line 21 located between the two sub-pixel regions. The upper sub-pixel region is referred to as a sub-region, and the lower sub-pixel region is referred to as a main region.

In addition, both ends of the first active region 31 may be covered with a first drain electrode 42 and a second drain electrode 43, and a predetermined distance is provided between the first drain electrode 42 and the second drain electrode 43. Of course, the first active region 31 is also covered with two sources, and there may be one source. When there are two sources, the two sources correspond to the first drain electrode 42 and the second drain electrode 43 respectively; when one source is provided, as shown in fig. 4, the first drain electrode 42 and the second drain electrode 43 share one source, so as to reduce the area of the source and increase the aperture ratio of the metal oxide array substrate. Hereinafter, description will be made by taking fig. 4 as an example, and a source common to the first drain electrode 42 and the second drain electrode 43 will be referred to as a first source electrode 44.

It should be noted that. The first drain electrode 42, the second drain electrode 43, the first source electrode 44 and the data line 41 may be disposed in the same layer to form a second metal layer.

As shown in fig. 5, the first drain electrode 42 includes a first end and a second end, the first end of the first drain electrode 42 covers the first active region 31, the second end of the first drain electrode 42 extends toward the main region, and a main pixel electrode 61 is disposed above the second end of the first drain electrode 42; the second drain electrode 43 includes a first end and a second end, the first end of the second drain electrode 43 covers the first active region 31, the second end of the second drain electrode 43 extends toward the sub-region, and a sub-pixel electrode 62 is disposed above the second end of the second drain electrode 43.

It should be noted that an insulating layer is further laid on the first metal layer, and a protective layer is further laid above the second metal layer, which are not important points in the present invention because they are prior art, and therefore, detailed description is not given here.

The following is a description of the specific structure of each layer.

First, assuming that a direction indicated by an arrow a is a longitudinal direction of the gate scanning line 21 and a direction indicated by an arrow B is a width direction of the gate scanning line 21, the main pixel electrode 61 and the sub-pixel electrode 62 are exemplarily located on both sides of the gate scanning line 21 in the width direction, and the data line 41 is provided along the longitudinal direction of the gate scanning line 21.

As shown in fig. 2, the gate scan line 21 may include a first portion 211 and a second portion 212, the second portion 212 may have a width greater than that of the first portion 211, the first portion 211 may be disposed on two sides of the second portion 212, and the first active region 31 is disposed on the second portion 212. It is understood that the first drain electrode 42 and the second drain electrode 43 are disposed opposite to each other on the first active region 31, and therefore, in order to ensure the overlapping area between the first drain electrode 42 and the second drain electrode 43 and the gate scan line 21 and the first active region 31, the gate scan line 21 is widened as a whole. Compared with the mode of widening the grid scanning lines 21 as a whole, the mode of widening the local grid scanning lines 21 increases the aperture opening ratio of the metal oxide array substrate.

Optionally, the second portion 212 may be provided with a PS in order to increase the transmittance. It is understood that, in order to maintain the Gap (Cell Gap, box thickness) between the metal oxide array substrate and the color filter substrate, a Spacer (Spacer) with a certain thickness is added between the two substrate substrates before the two substrate substrates are paired into a box to maintain the box thickness. The Spacer may be a Post Spacer (PS for short). The liquid crystal display panel adopts the PS in the process, and the PS can be arranged on the color film substrate base plate through the composition process, so that the position of the PS can be accurately controlled.

As shown in fig. 3, in order to increase an overlapping area between the first active region 31 and the first and

second drain electrodes

42 and 43, the first active region 31 may be disposed parallel to the data line 41. That is, both ends of the first active region 31 extend toward the main pixel electrode 61 and the sub-pixel electrode 62, respectively.

Alternatively, for uniformity of the metal oxide array substrate for better imaging effect, the first active regions 31 may be symmetrically disposed with respect to the axis of the gate scan line 21.

Alternatively, the length of the first active region 31 may be equal to the width of the gate scan line 21; both ends of the first active region 31 in the length direction may also extend out of both sides of the gate scan line 21 in the width direction, i.e. the length of the first active region 31 in the direction perpendicular to the gate scan line 21 is greater than the width of the gate scan line 21. In order to ensure an overlapping area between the first drain electrode 42, the second drain electrode 43 and the first source electrode 44 when the first metal layer moves relative to the second metal layer.

As shown in fig. 4, the first active region 31 is disposed symmetrically with respect to the axis of the gate scan line 21, a portion of the first drain electrode 42 overlapping the first active region 31 and a portion of the second drain electrode 43 overlapping the first active region 31 are disposed symmetrically, and the axis of symmetry is the axis of the gate scan line 21.

It is understood that when the second metal layer is shifted up and down with respect to the first metal layer, that is, when the second metal layer is shifted with respect to the first metal layer in the width direction of the gate scan line 21, if the overlapping area of the first drain electrode 42 and the gate scan line 21 becomes smaller, the overlapping area of the second drain electrode 43 and the gate scan line 21 increases accordingly; similarly, if the overlapping area of the second drain electrode 43 and the gate scan line 21 is decreased, the overlapping area of the first drain electrode 42 and the gate scan line 21 is increased accordingly, so that the total overlapping area of the first drain electrode 42, the second drain electrode 43 and the gate scan line 21 is kept unchanged, and the problems of uneven display and flicker caused by the variation of the parasitic capacitance Cgs are avoided.

In addition, the distance between the first drain electrode 42 and the main pixel electrode 61 and the distance between the second drain electrode 43 and the sub-pixel electrode 62 may be shortened.

As shown in fig. 4, in the axial direction of the gate scan line 21, that is, in the length direction of the gate scan line 21, the length of the overlapping region of the first drain electrode 42 and the gate scan line 21 is equal to the length of the first drain electrode 42.

It can be understood that when the second metal layer is shifted left and right relative to the first metal layer, that is, when the second metal layer is shifted along the length direction of the gate scan line 21 relative to the first metal layer, because the two sides of the first drain electrode 42 are the gate scan line 21, the width of the overlap region is kept unchanged, and the length of the overlap region is the length of the first drain electrode 42, the overlap area between the first drain electrode 42 and the gate scan layer is kept unchanged within the allowable error of manufacture; similarly, it can be inferred that the overlapping area between the first drain electrode 42 and the gate scan layer is always kept constant when the second metal layer is shifted left and right with respect to the first metal layer.

With continued reference to fig. 4, in the axial direction of the gate scan line 21, i.e., in the length direction of the gate scan line 21, the length of the overlapping region of the first drain electrode 42 and the first active region 31 is equal to the length of the first drain electrode 42, or the length of the overlapping region of the first drain electrode 42 and the first active region 31 is equal to the length of the first active region 31.

Exemplarily, when the length of the overlapping region of the first drain electrode 42 and the first active region 31 is equal to the length of the first drain electrode 42 (the second drain electrode 43), that is, the first active region 31 is located at two sides of the first drain electrode 42 (the second drain electrode 43), it can be concluded, with reference to the above, that the overlapping area between the first drain electrode 42 (the second drain electrode 43) and the first active region 31 always remains unchanged when the second metal layer is shifted to the left and right with respect to the first metal layer.

For another example, as shown in fig. 4, when the length of the overlapping region of the first drain electrode 42 (the second drain electrode 43) and the first active region 31 is equal to the length of the first active region 31, that is, the first drain electrode 42 (the second drain electrode 43) is located at two sides of the first active region 31, and the length of the overlapping region is the length of the first active region 31, the width of the overlapping region remains unchanged, so the overlapping area between the first drain electrode 42 (the second drain electrode 43) and the gate scan layer remains unchanged.

In summary, the present application provides a metal oxide array substrate, when a first metal layer and a second metal layer are shifted, the sum of the areas of the overlapping regions of a gate and a first drain 42, a second drain 43 remains unchanged, and the sum of the areas of the overlapping regions of a first active region 31 and a first drain 42, a second drain 43 remains unchanged, so that the size of the gate-drain parasitic capacitance can remain unchanged, the problems of uneven display and flicker caused by the change of the parasitic capacitance Cgd are avoided, the shared capacitance inside the metal oxide array substrate is uniformly distributed, and the picture display quality of the entire liquid crystal display panel is improved.

Alternatively, as shown in fig. 4 and 5, the first source electrode 44 may be disposed along the length direction of the gate scan line 21, the first source electrode 44 includes a first end and a second end, the first end of the first source electrode 44 is connected to the data line 41, and the second end of the first source electrode 44 is disposed on the first active region 31 and between the first end of the first drain electrode 42 and the first end of the second drain electrode 43.

It is understood that a first channel is formed between the first drain electrode 42 and the first source electrode 44, and a second channel is formed between the second drain electrode 43 and the first source electrode 44, such that the first drain electrode 42 and the second drain electrode 43 share the first source electrode 44. A first liquid crystal capacitance is formed between the main pixel electrode 61 and the common electrode on the rainbow substrate. A second liquid crystal capacitance is formed between the sub-pixel electrode 62 and the common electrode on the rainbow substrate.

In addition, since the first source 44 is located between the first drain 42 and the second drain 43, after the first metal layer is vertically shifted with respect to the second metal layer, that is, shifted in the width direction of the gate scan line 21, the overlapping area between the first source 44 and the gate scan line 21 and the first active region 31 is not changed, and the sharing capacitance between the first source 44 and the gate is not changed.

Fig. 6 is a circuit schematic diagram of a pixel region of a metal oxide array substrate according to an exemplary embodiment, and as shown in fig. 6, two thin film transistors, namely, a first thin film transistor TFT1 and a second thin film transistor TFT2, are disposed on one Gate scan line Gate. The first thin film transistor TFT1 and the second thin film transistor TFT2 are connected in parallel to a data line Date, and the data line Date respectively provides a target voltage for the first liquid crystal capacitor Clc-1 and the second liquid crystal capacitor Clc-2 through first source electrodes of the first thin film transistor TFT1 and the second thin film transistor TFT 2;

the first thin film transistor TFT1 and the second thin film transistor TFT2 are equivalent to switches, the Gate scan line Gate receives a timing pulse signal, and the on/off of the branch where the first liquid crystal capacitor Clc-1 and the second liquid crystal capacitor Clc-2 are located is controlled by controlling the on/off of the first thin film transistor TFT1 and the second thin film transistor TFT2, so that the pixel region can be controlled to display an image.

Illustratively, when the gate scan line 21 receives an on signal, the first thin film transistor TFT1 and the second thin film transistor TFT2 are turned on, and the first liquid crystal capacitor Clc-1 and the second liquid crystal capacitor Clc-2 are charged to store charges. When the gate scan line 21 receives the power-off signal, the first thin film transistor TFT1 and the second thin film transistor TFT2 are in an off state, and the charges on the first liquid crystal capacitor Clc-1 and the second liquid crystal capacitor Clc-2 are kept unchanged.

Alternatively, as shown in fig. 4 and 5, the projection of the first source electrode 44 is entirely located on the gate scan line 21. It can be understood that the gate scan line 21 is opaque, and the first source electrode 44, the first drain electrode 42 and the second drain electrode 43 are also opaque, so that the opaque first source electrode 44 is entirely stacked on the gate scan line 21, so as to increase the light transmittance of the metal oxide array substrate, and further increase the aperture ratio of the metal oxide array substrate.

Optionally, a second end of the first source 44 is disposed to extend beyond the first active region 31. It can be understood that, when the second metal layer is shifted left and right relative to the first metal layer, that is, when the second metal layer is shifted along the length direction of the gate scan line 21 relative to the first metal layer, the length of the overlapping region between the first source 44 and the first active region 31 is the length of the first active region 31, and the width of the overlapping region is not changed, so that the overlapping area between the first source 44 and the first active region 31 is not changed, and the sharing capacitance between the first active region 31 and the gate is not changed.

It is noted that the present application is an eight-domain structure, and the larger the number of display domains, the better the viewing angle characteristics. However, at the boundary between adjacent display domains, the liquid crystal molecules are driven by a voltage to be in a horizontal state, but the liquid crystal molecules in the adjacent display domains are not in the same rotational direction, and thus an intermediate state (generally 0 ° or 90 °) between the two rotational directions of the display domains occurs at the boundary. Under the condition that the VA display mode is matched with the linear polarizer, the transmittance of the liquid crystal molecules is highest when the liquid crystal molecules are rotated by 45 ° or 135 ° in the horizontal state, and is lowest when the liquid crystal molecules are rotated by 0 ° or 90 ° (i.e., when the liquid crystal molecules are horizontally or vertically aligned with the polarization direction of the polarizer), so that the transmittance at the boundary between adjacent domains is very low, and dark fringes are formed.

In view of this, as shown in fig. 6, a third thin film transistor TFT3 connected to the sharing capacitor C1 may be disposed on the gate scan line 21, and the third thin film transistor TFT3 is connected to the second thin film transistor TFT2 and can be turned on when the first thin film transistor TFT1 and the second thin film transistor TFT2 are turned off to reduce the voltage of the sub-region, so that a certain voltage difference exists between the voltages of the main region and the sub-region, and the liquid crystal molecules in the main region and the sub-region are twisted at different angles, which is beneficial to improving the color shift phenomenon at a large viewing angle.

Exemplarily, as shown in fig. 4 and fig. 6, the metal oxide array substrate further includes a second active region 32 disposed on the gate scan line 21, two ends of the second active region 32 are respectively covered with a second source 46 and a third drain 45, the second source 46 is connected to the second drain 43 or the shared capacitor, and the third drain 45 is connected to the shared capacitor or the second drain 43.

The second drain electrode 43 may be connected to the third drain electrode 45, and the second drain electrode 43 may be connected to the second source electrode 46. Fig. 4 and 5 illustrate the second drain electrode 43 and the third drain electrode 45 connected as an example. In fig. 4, the second source 46 is connected to a sharing capacitor, which may be formed by the first electrode plate 22 and the second electrode plate 47. The first electrode plate 22 may be formed in the same layer as the gate scan line 21, that is, the first electrode plate 22 is formed in the first metal layer. The third drain electrode 45, the second source electrode 46, and the second electrode plate 47 may be formed on the second metal layer. The sharing capacitor is located in the sub-region and below the sub-pixel electrode 62.

It is to be understood that, as shown in fig. 6, when the gate scan line 21 receives an on signal, the first thin film transistor TFT1, the second thin film transistor TFT2 are in an on state, and the third thin film transistor TFT3 is in an off state, the first liquid crystal capacitor Clc-1 and the second liquid crystal capacitor Clc-2 are charged to store charges. When the gate scan line 21 receives a power-off signal, the first thin film transistor TFT1 and the second thin film transistor TFT2 are in an off state, and the third thin film transistor TFT3 is in an on state, the charge of the first liquid crystal capacitor Clc-1 remains unchanged, and the charge of the second liquid crystal capacitor Clc-2 moves to the sharing capacitor C1, so that a certain voltage difference exists between the voltages of the first liquid crystal capacitor Clc-1 and the second liquid crystal capacitor Clc-2, thereby rotating the liquid crystals in the main region and the sub-region differently, and improving the color shift of the large viewing angle.

Alternatively, as shown in fig. 4 and fig. 5, the second active region 32 may be disposed along the length direction of the gate scan line 21, and the projection of the second active region 32 is entirely located on the gate scan line 21, that is, optionally, the width of the second active region 32 is smaller than the width of the gate scan line 21, so as to increase the aperture ratio of the metal oxide array substrate. Alternatively, the second active region 32 may be located at the above-mentioned second portion 212 of the gate scan line 21 in order to make reasonable use of the gate scan line 21.

When the first metal layer and the second metal layer are shifted in the left-right direction, that is, when the first metal layer and the second metal layer are shifted in the longitudinal direction of the gate scanning line 21, the second source electrode 46 and the third drain electrode 45 always overlap the gate scanning line 21 and the second active region 32.

Alternatively, the second active regions 32 may be symmetrically disposed, and the symmetry axis of the second active regions 32 is along the width direction of the gate scan line 21, and the third drain electrode 45 and the second source electrode 46 are respectively arranged at two sides of the symmetry axis of the second active regions 32, so as to achieve uniformity of the metal oxide array substrate.

Alternatively, both ends of the third drain electrode 45 and the second source electrode 46 extend out of both sides of the gate scanning line 21 in the width direction, that is, the third drain electrode 45 and the second source electrode 46 are perpendicular to the gate scanning line 21 and both ends of the third drain electrode 45 and the second source electrode 46 extend beyond the gate scanning line 21. It is understood that when the first metal layer and the second metal layer are shifted up and down, that is, shifted in the width direction of the gate scan line 21, the second source electrode 46 and the third drain electrode 45 always overlap with the gate scan line 21 and the second active region 32.

One possible fabrication process for the metal oxide array substrate is described below.

The method comprises the following steps: as shown in fig. 2, a gate metal film is deposited on a substrate base plate by sputtering or thermal evaporation. The gate metal film may be made of Cr, W, Cu, Ti, Ta, Mo, etc. or alloy, and the gate metal layer made of multiple layers of metal may also meet the requirement.

After a photolithography process, a gate scan line 21 and a first electrode plate 22 sharing a capacitor are formed, as shown in fig. 2, the gate scan line 21 is divided into a first portion 211 and a second portion 212. A first thin film transistor TFT1 for controlling the main region and the sub region and a first thin film transistor TFT2 may be designed above the second portion 212, and a third thin film transistor TFT3 for discharging may be disposed at the first portion 211.

Step two: as shown in FIG. 3, a thickness of

The insulating layer 3 may be made of an oxide, a nitride, or an oxynitride, and SiH4, N2O is used as a reaction gas corresponding to formation of silicon oxide in a PECVD method; the reaction gas corresponding to the formation of nitride or oxynitride in the PECVD process is SiH4, NH3, N2, or SiH2Cl2, NH3, N2;

then, the film is deposited thereon by sputtering or thermal evaporation to a thickness of about

The semiconductor layer may include a first active region 31 and a second active region 32. The semiconductor layer may be made of amorphous IGZO, HIZO, IZO, a-InZnO, ZnO F, In2O3 Sn, In2O3 Mo, Cd2SnO4, ZnO Al, TiO2 Nb, Cd-Sn-O or other metal oxides.

Step three: as shown in fig. 4, the substrate of step two is sequentially deposited by sputtering or thermal evaporation to a thickness of

The source drain metal film of (2). The source and drain metal film can be selected from Cr, W, Cu, Ti, Ta, Mo and other metals or alloys, and a gate metal layer consisting of multiple layers of metals can also meet the requirement.

The data line 41, the first drain electrode 42, the second drain electrode 43, the first source electrode 44, the third drain electrode 45, the second source electrode 46, and the second electrode plate of the sharing capacitor are formed by a common photolithography process. The second electrode plate overlaps the first electrode plate 22 to form a shared capacitor.

Step four: as shown in fig. 5, a thickness of

The metal oxide protective layer of (2) can be a single-layer silicon oxide or a composite structure of silicon nitride and silicon oxide, or a three-layer structure of silicon nitride/silicon oxynitride/silicon oxide, and the reaction gases corresponding to the silicon oxide, silicon oxynitride and silicon nitride can be N2O and SiH 4; N2O, SiH4, NH3, N2; SiH4, NH3, N2 or SiH2Cl2, NH3, N2.

Forming a contact via hole of the first drain electrode 42 and a contact via hole of the second drain electrode 43 through a common photolithography process, so that the first drain electrode 42 is connected to the main pixel electrode 61, and the second drain electrode 43 is connected to the sub-pixel electrode 62; the contact via of the third drain electrode 45 is identical to the second drain electrode 43.

Step five: as shown in fig. 5, the substrate of step four is continuously deposited by sputtering or thermal evaporation to a thickness of about

The transparent conductive layer of (2) may be ITO or IZO. The transparent main pixel electrode 61 and the sub-pixel electrode 62 are formed by one common photolithography process. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention. The embodiments described below and the features of the embodiments can be combined with each other without conflict.

The terms "upper" and "lower" are used to describe relative positions of the structures in the drawings, and are not used to limit the scope of the present invention, and the relative relationship between the structures may be changed or adjusted without substantial technical changes.

In the present application, unless expressly stated or limited otherwise, the first feature may be directly on or directly under the second feature or indirectly via intermediate members. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

Furthermore, in the present disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral part; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention.

Claims

1. The metal oxide array substrate is characterized by comprising a main pixel electrode, a sub-pixel electrode, a first drain electrode, a second drain electrode and a grid scanning line, wherein the main pixel electrode and the sub-pixel electrode are arranged side by side;

the gate scan line is located in a gap between the main pixel electrode and the sub-pixel electrode, the first drain electrode is located between the main pixel electrode and the gate scan line, the second drain electrode is located between the sub-pixel electrode and the gate scan line, and the first drain electrode and the second drain electrode are symmetrical with respect to a first straight line, which coincides with a center line of the gate scan line.

2. The metal oxide array substrate of claim 1, wherein the first and second drain electrodes share a first active region and a first source electrode, the first source electrode is electrically connected to a data line and is parallel to the gate scan line, and a center line of the first source electrode coincides with the first straight line.

3. The metal oxide array substrate of claim 2, wherein the length of the first active region in a direction perpendicular to the gate scan line is greater than the width of the gate scan line.

4. The metal oxide array substrate of claim 2, wherein in the direction of the gate scan line, a length of an overlapping region of the first drain and the gate scan line is equal to a length of the first drain, and a length of an overlapping region of the second drain and the gate scan line is equal to a length of the second drain.

5. The metal oxide array substrate of claim 2, wherein in the direction of the gate scan line, the length of the overlapping region of the first drain and the first active region is equal to the length of the first active region, and the length of the overlapping region of the second drain and the first active region is equal to the length of the first active region.

6. The metal oxide array substrate of any one of claims 2-5, further comprising a second source electrode and a third drain electrode arranged in parallel, and a second active region located between the second source electrode and the third drain electrode;

7. The metal oxide array substrate of claim 6, wherein the width of the second active region is less than the width of the gate scan line.

8. The metal oxide array substrate of claim 6, wherein the first drain and the second source are disposed in the same layer.

9. The metal oxide array substrate of claim 8, wherein the first drain electrode and the second source electrode are formed as a unitary structure.

10. The metal oxide array substrate of claim 6, wherein the third drain electrode and the second source electrode are perpendicular to the gate scan line and both end portions of the third drain electrode and the second source electrode extend beyond the gate scan line.