CN212380424U

CN212380424U - Flash memory chip module

Info

Publication number: CN212380424U
Application number: CN202020970460.8U
Authority: CN
Inventors: 单伟君; 沈晔晖; 单智阳; 廖少武; 金伟; 王立辉; 李清; 俞军
Original assignee: Shanghai Fudan Microelectronics Group Co Ltd
Current assignee: Shanghai Fudan Microelectronics Group Co Ltd
Priority date: 2020-06-01
Filing date: 2020-06-01
Publication date: 2021-01-19
Anticipated expiration: 2030-06-01

Abstract

A flash memory chip module, comprising: a package carrier including a number of external shared pins; the flash memory chip positioned on the packaging carrier comprises a plurality of first sharing pins and a plurality of first internal pins, and the first sharing pins are interconnected with the external sharing pins; the response protection monotonic counter chip positioned on the packaging carrier comprises a plurality of second internal pins, and the second internal pins are interconnected with the first internal pins. Therefore, the design complexity and the packaging difficulty of the flash memory chip module are reduced, the yield of the flash memory chip module is increased, and the power consumption of the flash memory chip module is reduced.

Description

Flash memory chip module

Technical Field

The utility model relates to a chip technology field especially relates to a flash memory chip module.

Background

The Response Protection Monotonic Counter (RPMC) is a Counter with a Monotonic counting function, that is, after the data recorded in the response Protection Monotonic Counter is responded, the response Protection Monotonic Counter only monotonically increases or monotonically decreases with the change of the count value.

In order to protect a FLASH memory (FLASH) chip and increase the confidentiality and integrity of data transmission of the FLASH memory chip, a response protection monotonic counter chip is generally used in combination with the FLASH memory chip to form a FLASH memory chip module. Therefore, a protection mechanism can be generated on the flash memory chip by using a method of one-way counting by the one-way counter and combining data verification to resist external attacks on the flash memory chip, such as Replay Attack (Replay Attack) or Probe Attack (Probe Attack).

However, the flash memory chip module has high design complexity, high packaging difficulty, low yield, and high power consumption.

Disclosure of Invention

The utility model provides a technical problem provide a flash memory chip module to reduce the design complexity, the encapsulation degree of difficulty of flash memory chip module, increase the yield of flash memory chip module, and reduce the consumption of flash memory chip module.

In order to solve the above technical problem, the technical scheme of the utility model provide a flash memory chip module, include: the device comprises a packaging carrier and a control module, wherein the packaging carrier comprises a plurality of external sharing pins which are used for acquiring a first external instruction; the flash memory chip is positioned on the packaging carrier and comprises a plurality of first sharing pins and a plurality of first internal pins, the first sharing pins are interconnected with the external sharing pins, the first sharing pins are used for inputting the first external instruction into the flash memory chip, and the first internal pins are used for outputting a first instruction; the response protection monotonic counter chip is positioned on the packaging carrier and comprises a plurality of second internal pins, the second internal pins are interconnected with the first internal pins, and the second internal pins are used for inputting the first instruction into the response protection monotonic counter chip and transmitting first information from the response protection monotonic counter chip to the first internal pins.

Optionally, the flash memory chip further includes: and the first receiving and judging module is used for judging the first external instruction and outputting the first instruction, or outputting the second instruction, or outputting the first instruction and the second instruction.

Optionally, the flash memory chip further includes: and the first control module is used for controlling the flash memory chip to execute the second instruction and outputting second information.

Optionally, the flash memory chip further includes: the first output judgment module is used for judging the first information and outputting the first information, the second information or the first information and the second information to the first sending module, or closing the first sending module.

Optionally, the first shared pin is interconnected with the first sending module, and the first shared pin is further configured to transmit the first information, the second information, or the first information and the second information to the external shared pin.

Optionally, the flash memory chip further includes: the first output judgment module is used for judging the first information and outputting the first information, the second information, the third information, the first information and the second information or the first information and the third information to the first sending module, and the third information is encrypted data or random error data.

Optionally, the first sharing pin is interconnected with the first sending module, and the first sharing pin is further configured to transmit the first information, the second information, the third information, the first information and the second information, or the first information and the third information to the external sharing pin.

Optionally, the package carrier further includes a plurality of external independent pins, and the external independent pins are used for receiving a second external instruction; the flash memory chip further includes: the first independent pins are used for inputting the second external instruction into a flash memory chip and transmitting fourth information from the flash memory chip to the external independent pins, and the fourth information is data obtained after the flash memory chip processes the second external instruction.

Optionally, the external independent pin is further configured to receive a third external instruction; the answer protection monotonic counter chip further comprises: the second independent pins are used for inputting the third external instruction into a response protection monotonic counter chip and transmitting fifth information from the response protection monotonic counter chip to the external independent pins, and the fifth information is data obtained after the response protection monotonic counter chip processes the third external instruction.

Optionally, the answer protection monotonic counter chip further includes a second control module, where the second control module is configured to control the answer protection monotonic counter chip to execute the first instruction, and output first information to the second internal pin.

Optionally, in a direction perpendicular to the surface of the package carrier, the flash memory chip and the response protection monotonic counter chip are arranged in an overlapping manner.

Optionally, the flash memory chip and the response protection monotonic counter chip are arranged along the direction of the surface of the package carrier.

The technical scheme of the utility model a flash memory chip module is still provided, include: the device comprises a packaging carrier and a control module, wherein the packaging carrier comprises a plurality of external sharing pins which are used for acquiring a first external instruction; the response protection monotonic counter chip is positioned on the packaging carrier and comprises a plurality of second shared pins and a plurality of second internal pins, the second shared pins are interconnected with the external shared pins, the second shared pins are used for inputting the first external instruction into the response protection monotonic counter chip, and the second internal pins are used for outputting a second instruction; the flash memory chip is positioned on the packaging carrier and comprises a plurality of first internal pins, the first internal pins are interconnected with the second internal pins, and the first internal pins are used for inputting the second instruction into the flash memory chip and transmitting second information from the flash memory chip to the second internal pins.

Optionally, the answer protection monotonic counter chip further includes: and the second receiving and judging module is used for judging the first external instruction and outputting the first instruction, or outputting a second instruction, or outputting the first instruction and the second instruction.

Optionally, the answer protection monotonic counter chip further includes: and the second control module is used for controlling the response protection monotonic counter chip to execute the first instruction and outputting first information.

Optionally, the answer protection monotonic counter chip further includes: the second output judgment module is used for judging the first information and outputting the first information, the second information or the first information and the second information to the second sending module, or closing the second sending module.

Optionally, the second sharing pin is interconnected with the second sending module, and the second sharing pin is further configured to transmit the first information, the second information, or the first information and the second information to the external sharing pin.

Optionally, the answer protection monotonic counter chip further includes: the second output judgment module is used for judging the first information and outputting the first information, the second information, the third information, the first information and the second information or the first information and the third information to the second sending module, and the third information is encrypted data or random error data.

Optionally, the second sharing pin is interconnected with the second sending module, and the second sharing pin is further configured to transmit the first information, the second information, the third information, the first information and the second information, or the first information and the third information to the external sharing pin.

Optionally, the package carrier further includes a plurality of external independent pins, and the external independent pins are further configured to receive a third external instruction; the answer protection monotonic counter chip further comprises: the second independent pins are used for inputting the third external instruction into a response protection monotonic counter chip and transmitting fifth information from the response protection monotonic counter chip to the external independent pins, and the fifth information is data obtained after the response protection monotonic counter chip processes the third external instruction.

Optionally, the external independent pin is configured to receive a second external instruction; the flash memory chip further includes: the first independent pins are used for inputting the second external instruction into a flash memory chip and transmitting fourth information from the flash memory chip to the external independent pins, and the fourth information is data obtained after the flash memory chip processes the second external instruction.

Optionally, the flash memory chip further includes a first control module, where the first control module is configured to control the flash memory chip to execute the second instruction and output second information to the first internal pin.

Compared with the prior art, the technical scheme of the invention has the following beneficial effects:

in the flash memory chip module provided by the technical scheme of the invention, the first shared pin is used for inputting the first external instruction into the flash memory chip, the first internal pin is used for outputting the first instruction, the second internal pin is used for inputting the first instruction into the response protection monotonic counter chip and transmitting the first information from the response protection monotonic counter chip to the first internal pin, so that on the first aspect, chips which are directly interconnected with the external shared pin and generate data transmission are reduced. Because the number of chips which are directly connected with external shared pins and generate data transmission is reduced, the number of the shared pins for responding and protecting the monotonic counter chip is reduced, and therefore the wiring design complexity of the flash memory chip module is simplified, the packaging difficulty is reduced, and the yield of the flash memory chip module is increased; and the load of the control instruction which needs to be driven by the external shared pin is reduced, so that the design requirement of the driving capability of the external shared pin is reduced, and the power consumption of the flash memory chip module is reduced. In the second aspect, the control instruction which is from the outside and points to the answer protection monotonic counter chip can be input into the answer protection monotonic counter chip through the flash memory chip, and the condition that the answer protection monotonic counter chip executes the instruction can be obtained through the flash memory chip, that is, the flash memory chip is controlled to be matched with the answer protection monotonic counter chip for use. Because the control flash memory chip and the response protection monotonic counter chip are matched for use through the flash memory chip, the judgment and monitoring required by the response protection monotonic counter chip are simplified and reduced, on one hand, the design complexity of a control logic circuit of the response protection monotonic counter chip is reduced, the power consumption of a flash memory chip module is reduced, on the other hand, the number of internal pins for data transmission between the flash memory chip and the response protection monotonic counter chip can be reduced, namely, the number of the first internal pins and the second internal pins is reduced, the wiring design complexity of the flash memory chip module is simplified, the packaging difficulty is reduced, and the yield of the flash memory chip module is increased.

Furthermore, the packaging carrier also comprises a plurality of external independent pins, and the external independent pins are used for receiving a second external instruction; the flash memory chip further includes: the flash memory chip comprises a plurality of first independent pins and a plurality of second independent pins, wherein the first independent pins are connected with the external independent pins, so that the flexibility of a path for the flash memory chip to receive an independent instruction pointing to the flash memory chip and the data acquired by the flash memory chip after the flash memory chip independently executes the instruction to be transmitted to the outside is increased through the external independent pins and the first independent pins.

In the flash memory chip module provided by the technical scheme of the invention, the second shared pin is used for inputting the first external instruction into the response protection monotonic counter chip, the second internal pin is used for outputting the second instruction, and the first internal pin is used for inputting the second instruction into the flash memory chip and transmitting the second information from the flash memory chip to the second internal pin, so that, on the first hand, chips which are directly interconnected with the external shared pin and generate data transmission are reduced. Because the number of chips which are directly connected with external shared pins and generate data transmission is reduced, the number of the shared pins of the flash memory chip is reduced, and therefore the wiring design complexity of the flash memory chip module is simplified, the packaging difficulty is reduced, and the yield of the flash memory chip module is increased; and the load of the control instruction which needs to be driven by the external shared pin is reduced, so that the design requirement of the driving capability of the external shared pin is reduced, and the power consumption of the flash memory chip module is reduced. In the second aspect, the monotonic counter chip can be protected by answering, a control instruction which is from the outside and points to the flash memory chip can be input into the flash memory chip, and the condition that the flash memory chip executes the instruction can be obtained by the monotonic counter chip which is protected by answering, that is, the monotonic counter chip is protected by answering, so that the flash memory chip and the monotonic counter chip which is protected by answering can be matched for use. Because the monotonic counter chip is protected by the response, the monotonic counter chip and the flash memory chip are controlled to be matched for use, so that the judgment and monitoring required by the flash memory chip are simplified and reduced, on one hand, the design complexity of a control logic circuit of the flash memory chip is reduced, the power consumption of a flash memory chip module is reduced, on the other hand, the number of internal pins for data transmission between the flash memory chip and the monotonic counter chip can be reduced, namely, the number of the first internal pins and the second internal pins is reduced, and the wiring design complexity of the flash memory chip module is simplified, the packaging difficulty is reduced, and the yield of the flash memory chip module is increased; meanwhile, the method is beneficial to reducing the contact frequency of the flash memory chip and an external instruction and reducing the risk that the flash memory chip is attacked when the external instruction is analyzed, thereby increasing the data security of the flash memory chip and improving the confidentiality and the integrity of data transmission of the flash memory chip module.

Further, the package carrier further comprises a plurality of external independent pins, and the external independent pins are further used for receiving a third external instruction; the answer protection monotonic counter chip further comprises: the response protection monotonic counter chip receives an instruction which points to the response protection monotonic counter chip independently and the flexibility of a path for transmitting data acquired after the response protection monotonic counter chip executes the instruction independently to the outside are increased through the external independent pin and the second independent pin.

Compared with the prior art, the technical scheme of the utility model following beneficial effect has:

the utility model discloses in the flash memory chip module that technical scheme provided, because first sharing pin be used for with first outside instruction input flash memory chip, first inside pin is used for exporting first instruction, and, the inside pin of second be used for with first instruction input answer protection monotonic counter chip to with first information from answering protection monotonic counter chip to first inside pin transmission, consequently, the first aspect, reduced directly with outside sharing pin interconnection, produce data transmission's chip. Because the number of chips which are directly connected with external shared pins and generate data transmission is reduced, the number of the shared pins for responding and protecting the monotonic counter chip is reduced, and therefore the wiring design complexity of the flash memory chip module is simplified, the packaging difficulty is reduced, and the yield of the flash memory chip module is increased; and the load of the control instruction which needs to be driven by the external shared pin is reduced, so that the design requirement of the driving capability of the external shared pin is reduced, and the power consumption of the flash memory chip module is reduced. In the second aspect, the control instruction which is from the outside and points to the answer protection monotonic counter chip can be input into the answer protection monotonic counter chip through the flash memory chip, and the condition that the answer protection monotonic counter chip executes the instruction can be obtained through the flash memory chip, that is, the flash memory chip is controlled to be matched with the answer protection monotonic counter chip for use. Because the control flash memory chip and the response protection monotonic counter chip are matched for use through the flash memory chip, the judgment and monitoring required by the response protection monotonic counter chip are simplified and reduced, on one hand, the design complexity of a control logic circuit of the response protection monotonic counter chip is reduced, the power consumption of a flash memory chip module is reduced, on the other hand, the number of internal pins for data transmission between the flash memory chip and the response protection monotonic counter chip can be reduced, namely, the number of the first internal pins and the second internal pins is reduced, the wiring design complexity of the flash memory chip module is simplified, the packaging difficulty is reduced, and the yield of the flash memory chip module is increased.

The utility model discloses in the flash memory chip module that technical scheme provided, because the second shared pin be used for with the monotonic counter chip of protection is answered in the input of first outside instruction, the inside pin of second is used for exporting the second instruction, and, first inside pin be used for with the input of second instruction the flash memory chip to with the second information from the flash memory chip to the inside pin transmission of second, consequently, the first aspect, reduced directly with outside shared pin interconnect, produce data transmission's chip. Because the number of chips which are directly connected with external shared pins and generate data transmission is reduced, the number of the shared pins of the flash memory chip is reduced, and therefore the wiring design complexity of the flash memory chip module is simplified, the packaging difficulty is reduced, and the yield of the flash memory chip module is increased; and the load of the control instruction which needs to be driven by the external shared pin is reduced, so that the design requirement of the driving capability of the external shared pin is reduced, and the power consumption of the flash memory chip module is reduced. In the second aspect, the monotonic counter chip can be protected by answering, a control instruction which is from the outside and points to the flash memory chip can be input into the flash memory chip, and the condition that the flash memory chip executes the instruction can be obtained by the monotonic counter chip which is protected by answering, that is, the monotonic counter chip is protected by answering, so that the flash memory chip and the monotonic counter chip which is protected by answering can be matched for use. Because the monotonic counter chip is protected by the response, the monotonic counter chip and the flash memory chip are controlled to be matched for use, so that the judgment and monitoring required by the flash memory chip are simplified and reduced, on one hand, the design complexity of a control logic circuit of the flash memory chip is reduced, the power consumption of a flash memory chip module is reduced, on the other hand, the number of internal pins for data transmission between the flash memory chip and the monotonic counter chip can be reduced, namely, the number of the first internal pins and the second internal pins is reduced, and the wiring design complexity of the flash memory chip module is simplified, the packaging difficulty is reduced, and the yield of the flash memory chip module is increased; meanwhile, the method is beneficial to reducing the contact frequency of the flash memory chip and an external instruction and reducing the risk that the flash memory chip is attacked when the external instruction is analyzed, thereby increasing the data security of the flash memory chip and improving the confidentiality and the integrity of data transmission of the flash memory chip module.

Drawings

FIG. 1 is a schematic diagram of a flash memory chip module;

fig. 2 is a schematic diagram of the logical connection of a flash memory chip module according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a packaging principle of a flash memory chip module according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a logical connection of a flash memory chip module according to another embodiment of the present invention;

fig. 5 is a schematic structural diagram of a packaging principle of a flash memory chip module according to another embodiment of the present invention.

Detailed Description

As described in the background art, the flash memory chip module has high design complexity, high packaging difficulty, low yield, and high power consumption. The analysis will now be described with reference to specific examples.

FIG. 1 is a schematic diagram of a flash memory chip module.

Referring to fig. 1, the flash memory chip module includes: a flash chip 110, wherein the flash chip 110 includes a plurality of flash chip shared IO pins (e.g., IO _ x _1, IO _ x _2, … …, IO _ x _ n in fig. 1), a plurality of flash chip internal IO pins (e.g., IO _ a _1, IO _ a _2, … …, IO _ a _ n in fig. 1), and a flash chip controller (not shown); an answer protection monotonic counter chip 120, the answer protection monotonic counter chip 120 comprising: an IO pin (such as IO _ y _1, IO _ y _2, … …, IO _ y _ n in fig. 1) shared by a plurality of answer protection monotonic counter chips, an IO pin (such as IO _ b _1, IO _ b _2, … …, IO _ b _ n in fig. 1) inside a plurality of answer protection monotonic counter chips, and an answer protection monotonic counter chip controller (not shown); several external shared IO pins (e.g. IO _1, IO _2, … …, IO _ n in FIG. 1).

The flash memory chip 110 and the response protection monotonic counter chip 120 are independent from each other.

The flash memory chip controller is used for receiving an external instruction, judging whether the flash memory chip needs to execute the external instruction or not, and controlling the flash memory chip to execute the external instruction when the flash memory chip needs to execute the external instruction.

The response protection monotonic counter chip controller is used for receiving an external instruction, judging whether the response protection monotonic counter chip needs to execute the external instruction or not, and controlling the response protection monotonic counter chip to execute the external instruction when judging that the response protection monotonic counter chip needs to execute the external instruction.

And the corresponding sharing IO pin of the flash memory chip and the sharing IO pin of the response protection monotonic counter chip are connected with the same external sharing IO pin by adopting a metal lead, so that an external instruction is simultaneously transmitted to the flash memory chip controller and the response protection monotonic counter chip controller through the external sharing IO pin, the sharing IO pin of the flash memory chip and the sharing IO pin of the response protection monotonic counter chip.

For example, a flash memory chip shared IO pin IO _ x _1, a response protection monotonic counter chip shared IO pin IO _ y _1 and an external shared IO pin IO _1 are interconnected; the method comprises the steps that a flash memory chip shared IO pin IO _ x _2 and a response protection monotonic counter chip shared IO pin IO _ y _2 are connected with an external shared IO pin IO _ 2; and interconnecting the shared IO pin IO _ x _ n of the flash memory chip, the shared IO pin IO _ y _ n of the response protection monotonic counter chip and the external shared IO pin IO _ n, and the like.

And the IO pins in the corresponding flash memory chip and the IO pins in the response protection monotonic counter chip are interconnected by adopting metal leads. Therefore, through the IO pin in the flash memory chip and the IO pin in the response protection monotonic counter chip which are interconnected in pairs, the current state of the flash memory chip and the current state of the response protection monotonic counter chip can be obtained or the execution state of an external instruction can be obtained.

For example, an internal IO pin IO _ a _1 of the flash memory chip is interconnected with an internal IO pin IO _ b _1 of the response protection monotonic counter chip; interconnecting an IO pin IO _ a _2 in the flash memory chip with an IO pin IO _ b _2 in the response protection monotonic counter chip; and interconnecting an IO pin IO _ a _ n in the flash memory chip with an IO pin IO _ b _ n in the response protection monotonic counter chip, and the like.

In the flash memory chip module, the flash memory chip and the response protection monotonic counter chip are independent chips, so that the flash memory chip and the response protection monotonic counter chip can be used in a matched mode to protect the flash memory chip, the area of a single chip is reduced, the packaging area is reduced, the design complexity of the flash memory chip module is simplified, and the design flexibility of the flash memory chip module is improved.

However, in the above embodiment, on one hand, in order to use the flash memory chip and the response protection monotonic counter chip in a matched manner, the flash memory chip needs to have a flash memory chip sharing IO pin, and the response protection monotonic counter chip needs to have a response protection monotonic counter chip sharing IO pin, so that the flash memory chip controller and the response protection monotonic counter chip controller can respectively obtain external instructions, and therefore, the number of the sharing IO pins of the flash memory chip module is large, thereby increasing the wiring complexity when the flash memory chip module is packaged, increasing the difficulty in packaging the flash memory chip module, and reducing the yield of the flash memory chip module. On the other hand, the external shared IO pin needs to drive the flash memory chip and respond to the load of the control instruction of the two parts of the protection monotonic counter chip at the same time, so the design driving capability requirement of the external shared IO pin is high, and the power consumption of the flash memory chip module is high. In addition, the flash memory chip controller and the response protection monotonic counter chip controller respectively judge and execute external instructions for respective chips, so that the power consumption of the flash memory chip module is large. On the basis, in order to enable the flash memory chip and the response protection monotonic counter chip to be matched for use, both the flash memory chip controller and the response protection monotonic counter chip controller need to acquire the current state of the other party or the execution state of an external instruction, so that the design of a control logic circuit of the flash memory chip and the response protection monotonic counter chip is more complicated, and meanwhile, the number of IO pins inside the flash memory chip and the number of IO pins inside the response protection monotonic counter chip are more, so that the design complexity of the flash memory chip module is not facilitated to be simplified, meanwhile, the wiring complexity in the process of packaging the flash memory chip module is further increased, the difficulty in packaging the flash memory chip module is improved, and the yield of the flash memory chip module is reduced.

In summary, in the above embodiments, the flash memory chip module has a high design complexity, a high packaging difficulty, a low yield, and a high power consumption.

For solving the technical problem, the embodiment of the utility model provides a flash memory chip module includes a plurality of first sharing pins through flash memory chip in the flash memory chip module, perhaps deposits the monotonic counter chip of answer protection in the chip module and includes a plurality of second sharing pins, and, the flash memory chip includes a plurality of first inside pins, the monotonic counter chip of answer protection includes a plurality of second inside pins, the second inside pin with first inside pin interconnection to reduce the design complexity of flash memory chip module, the encapsulation degree of difficulty, increase the yield of flash memory chip module, and reduce the consumption of flash memory chip module.

In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings.

Fig. 2 is a schematic diagram of the logic connection of the flash memory chip module according to an embodiment of the present invention, and fig. 3 is a schematic diagram of the packaging principle structure of the flash memory chip module according to an embodiment of the present invention.

Referring to fig. 2 and 3, the flash memory chip module includes: a package carrier 200, where the package carrier 200 includes a plurality of external shared pins (e.g. IO _ W _1, IO _ W _2, … …, IO _ W _ n in fig. 2), and the external shared pins are used for obtaining a first external instruction.

With continued reference to fig. 2 and 3, the flash memory chip module further includes: a flash memory chip 210 located on the package carrier 200, and a reply-protection monotonic counter chip 220 located on the package carrier 200.

The flash memory chip 210 includes: a number of first shared pins (e.g., IO _ a _1, IO _ a _2, … …, IO _ a _ n in fig. 2).

The first shared pin is interconnected with the external shared pin, and the first shared pin is used for inputting the first external command into the flash memory chip 210.

In the present embodiment, the respective first shared pin and the external shared pin are interconnected using a metal wire 231.

For example, the first shared pin IO _ a _1 is interconnected with the external shared pin IO _ W _ 1; interconnecting a first shared pin IO _ A _2 and an external shared pin IO _ W _ 2; the first shared pin IO _ a _ n is interconnected with the external shared pin IO _ W _ n, etc.

Thus, the first external command can be obtained by the first shared pin, and the first external command is input to the flash memory chip 210 through the first shared pin.

In this embodiment, the flash memory chip 210 further includes: a first receiving and determining module 211, where the first receiving and determining module 211 is configured to determine the first external instruction and output the first instruction, or output a second instruction, or output the first instruction and the second instruction.

It should be noted that the first external instruction includes: at least one of an instruction pointing to the flash memory chip 210 and an instruction pointing to the answer protection monotonic counter chip 220, where the first instruction is an instruction formed according to the instruction pointing to the answer protection monotonic counter chip 220, and the second instruction is an instruction formed according to the instruction pointing to the flash memory chip 210.

Specifically, after the first external command is input to the flash memory chip 210 through the first shared pin, the first receiving and determining module 211 determines that the first external command is: when the first external instruction only includes an instruction pointing to the answer protection monotonic counter chip 220, the first receiving judgment module 211 outputs the first instruction; when the first external command only includes a command pointing to the flash memory chip 210, the first receiving and determining module 211 outputs the second command; when the first external instruction includes an instruction pointing to the flash memory chip 210 and an instruction pointing to the response protection monotonic counter chip 220, the first receiving and determining module 211 outputs the first instruction and the second instruction.

In this embodiment, the flash memory chip 210 further includes: a first control module 212, where the first control module 212 is configured to control the flash chip 210 to execute the second instruction and output second information.

It should be noted that the second information is data obtained after the flash chip 210 executes the second instruction.

Specifically, in this embodiment, when the first external instruction includes an instruction pointing to the flash chip 210, the first control module 212 acquires a second instruction through the first receiving and determining module 211, and controls the flash chip 210 to execute the second instruction and output second information.

The flash memory chip 210 further includes: a plurality of first internal pins (e.g. IO _ C _1, IO _ C _2, … …, IO _ C _ n in fig. 2) for outputting the first instruction.

Specifically, in this embodiment, after the first internal pin obtains the first instruction from the first receiving and determining module 211, the first internal pin outputs the first instruction to the response protection monotonic counter chip 220.

The answer protection monotonic counter chip 220 includes: a plurality of second internal pins (for example, IO _ D _1, IO _ D _2, … …, IO _ D _ n in fig. 2), the second internal pins being interconnected with the first internal pins, and the second internal pins being configured to input the first instruction into the response protection monotonic counter chip 220, and transmit the first information from the response protection monotonic counter chip 220 to the first internal pins.

Since the second internal pin is interconnected with the first internal pin, the second internal pin can acquire the first instruction and transmit first information to the first internal pin, that is, the first instruction is input into the response protection monotonic counter chip 220 through the second internal pin, and the first information is transmitted to the first internal pin from the response protection monotonic counter chip 220.

It should be noted that the first information is data obtained by the response protection monotonic counter chip 220 executing the first instruction, and the data may include an execution state of the response protection monotonic counter chip 220, data that needs to be transmitted to the outside and is obtained after the response protection monotonic counter chip 220 executes the first instruction, and the like.

Since the first shared pin is used to input the first external instruction into the flash memory chip 210, the first internal pin is used to output the first instruction, and the second internal pin is used to input the first instruction into the answer protection monotonic counter chip 220, and transmit the first information from the answer protection monotonic counter chip 220 to the first internal pin, in the first aspect, chips directly interconnected with the external shared pin and generating data transmission are reduced. Because the number of chips which are directly connected with external shared pins and generate data transmission is reduced, the number of shared pins for answering and protecting the monotonic counter chip 220 is reduced, and therefore the wiring design complexity of the flash memory chip module is simplified, the packaging difficulty is reduced, and the yield of the flash memory chip module is increased; and the load of the control instruction which needs to be driven by the external shared pin is reduced, so that the design requirement of the driving capability of the external shared pin is reduced, and the power consumption of the flash memory chip module is reduced.

In the second aspect, the flash memory chip 210 can input a control instruction, which is from the outside and is directed to the answer protection monotonic counter chip 220, into the answer protection monotonic counter chip 220, and the flash memory chip 210 can acquire the condition that the answer protection monotonic counter chip 220 executes the instruction, that is, the flash memory chip 210 can control the flash memory chip 210 and the answer protection monotonic counter chip 220 to be used cooperatively. Because the control of the flash memory chip 210 and the cooperation of the response protection monotonic counter chip 220 are realized through the flash memory chip 210, the judgment and the monitoring which are needed by the response protection monotonic counter chip 220 are facilitated to be simplified and reduced. Therefore, on the one hand, it is beneficial to reduce the complexity of the design of the control logic circuit of the response protection monotonic counter chip 220 and reduce the power consumption of the flash memory chip module, and on the other hand, it is also capable of reducing the number of the internal pins for data transmission between the flash memory chip 210 and the response protection monotonic counter chip 220, that is, the number of the first internal pins and the second internal pins, so as to facilitate the simplification of the complexity of the wiring design of the flash memory chip module, the reduction of the packaging difficulty, and the increase of the yield of the flash memory chip module.

In the present embodiment, metal leads 232 are employed to interconnect the respective first and second internal leads.

For example, a first internal pin IO _ C _1 and a second internal pin IO _ D _1 are interconnected; interconnecting the first internal pin IO _ C _2 and the second internal pin IO _ D _ 2; the first internal pin IO _ C _ n is interconnected with the second internal pin IO _ D _ n, etc.

In other embodiments, the flash memory chip 210 and the answer guard monotonic counter chip 220 are bonded to enable interconnection of the first internal lead and the second internal lead.

In this embodiment, the answer protection monotonic counter chip 220 further includes a second control module 221, where the second control module 221 is configured to control the answer protection monotonic counter chip 220 to execute the first instruction, and output the first information to the second internal pin.

Specifically, in this embodiment, when the first external instruction includes an instruction pointing to the answer protection monotonic counter chip 220, the second control module 221 acquires the first instruction through the second internal pin, controls the answer protection monotonic counter chip 220 to execute the first instruction, and outputs the first information to the second internal pin.

In this embodiment, the flash memory chip 210 further includes: a first output judging module 213 and a first sending module 214, where the first output judging module 213 is configured to judge the first information, and output the first information, the second information, or the first information and the second information to the first sending module 214, or turn off the first sending module 214.

In this embodiment, the first shared pin is interconnected with the first sending module 214, and the first shared pin is further used for transmitting the first information, the second information, or the first information and the second information to the external shared pin.

Specifically, in this embodiment, after acquiring the first information, the first output judgment module 213 judges the first information: to determine whether the first information includes information that needs to be transmitted to the outside, and when the first information includes information that needs to be transmitted to the outside, output the first information to the first transmitting module 214. And, it is determined whether the flash memory chip 210 is attacked, i.e., whether the current state of the flash memory chip 210 is safe. When the current state of the flash memory chip 210 is safe, outputting second information to the first sending module 214; when the current state of the flash memory chip 210 is not unsafe, the first transmitting module 214 is turned off. After the first sending module 241 obtains the first information, the second information, or the first information and the second information, the first information, the second information, or the first information and the second information are transmitted to the outside through the first sharing pin and the external sharing pin.

Therefore, on one hand, the state of the flash memory chip module can be obtained, and on the other hand, a protection mechanism can be generated for the flash memory chip 210 to resist external attack on the flash memory chip 210, so that the confidentiality and integrity of data transmission of the flash memory chip 210 are improved.

In other embodiments, the first output determining module is configured to determine the first information, and output the first information, the second information, the third information, the first information and the second information, or the first information and the third information to the first sending module, where the third information is encrypted data or random error data. The first sharing pin is interconnected with the first sending module, and the first sharing pin is further used for transmitting the first information, the second information, the third information, the first information and the second information, or the first information and the third information to the external sharing pin.

Specifically, in another embodiment, after acquiring the first information, the first output determination module determines that the first information: to determine whether the first information includes information that needs to be transmitted to the outside, and when the first information includes information that needs to be transmitted to the outside, output the first information to the first sending module. And, it is determined whether the flash memory chip is under attack, i.e., whether the current state of the flash memory chip is safe. When the current state of the flash memory chip is safe, outputting second information to the first sending module; and when the current state of the flash memory chip is not unsafe, outputting third information to the first sending module. And the first sending module acquires the first information, the second information, the third information, the first information and the second information, or the first information and the third information, and then transmits the first information, the second information, the third information, the first information and the second information, or the first information and the third information to the outside through the first sharing pin and the external sharing pin.

The third information is encrypted data, which means that the third information is data obtained by encrypting the second information. The third information is random error data, which means that the third information is random error data which is acquired by error infection and has misleading attackers.

In this embodiment, the package carrier 200 further includes a plurality of external independent pins (e.g. IO _ V _1, IO _ V _2, … …, IO _ V _ n in fig. 2) for receiving a second external instruction.

It should be noted that the second external instruction is a control instruction pointing to the flash memory chip 210, and the control instruction is an instruction executed by the flash memory chip 210 independently to implement the function of the flash memory chip 210.

In this embodiment, the flash memory chip 210 further includes: a number of first independent pins (e.g., IO _ E _1, IO _ E _2, … …, IO _ E _ n in fig. 2) interconnected with the external independent pins.

In the present embodiment, the respective first and external individual pins are interconnected using metal wires 233.

For example, a first independent pin IO _ E _1 is interconnected with an external independent pin IO _ V _ 1; interconnecting the first independent pin IO _ E _2 with an external independent pin IO _ V _ 2; the first independent pin IO _ E _ n is interconnected with the external independent pin IO _ V _ n, etc.

The first independent pin is used for inputting the second external instruction into the flash memory chip 210, and for transmitting fourth information from the flash memory chip to the external independent pin, where the fourth information is data obtained after the flash memory chip processes the second external instruction.

Specifically, in this embodiment, the external independent pin receives a second external instruction, and the first independent pin obtains the second external instruction from the external independent pin and inputs the second external instruction into the flash memory chip 210; after the flash chip 210 executes the second external instruction, fourth information is obtained, and the first independent pin transmits the fourth information to the external independent pin.

Therefore, an external instruction executed by the flash memory chip 210 in cooperation with the response protection monotonic counter chip 220 is not required, and the external instruction can be input to the flash memory chip 210 through the external shared pin and the first shared pin, and can also be input to the flash memory chip through the external independent pin and the first independent pin. Moreover, after the flash chip 210 executes the external command to obtain data, the data can be output to the outside through the external shared pin and the first shared pin, and also can be output to the outside through the external independent pin and the first independent pin. Furthermore, on one hand, flexibility of a path through which the flash memory chip 210 receives an instruction directed to the flash memory chip 210 independently is increased, and on the other hand, flexibility of a path through which data acquired after the flash memory chip 210 executes the instruction independently is transmitted to the outside is increased.

In other embodiments, the flash memory chip does not include the first independent pin.

In other embodiments, the package carrier does not include external stand-alone pins.

In other embodiments, the external stand-alone pin is further configured to receive a third external command. The answer protection monotonic counter chip further comprises: a number of second independent pins, the second independent pins and the external independent pins being interconnected. The second independent pin is used for inputting the third external instruction into a response protection monotonic counter chip and transmitting fifth information from the response protection monotonic counter chip to the external independent pin, and the fifth information is data obtained after the response protection monotonic counter chip processes the third external instruction.

In other embodiments, the second independent pin and the external independent pin are interconnected using metal wires.

It should be noted that the third external instruction is a control instruction pointing to the response protection monotonic counter chip, and the control instruction is an instruction that is independently executed by the response protection monotonic counter chip and implements a function of the response protection monotonic counter chip.

Specifically, in other embodiments, the external independent pin receives a third external instruction, and the second independent pin obtains the third external instruction from the external independent pin and inputs the third external instruction into the flash memory chip; and after the flash memory chip executes the third external instruction, fifth information is acquired, and the second independent pin transmits the fifth information to the external independent pin.

Therefore, an external instruction executed by the flash memory chip and the response protection monotonic counter chip in a matching manner is not needed, the response protection monotonic counter chip can be input after being input to the flash memory chip through the external shared pin and the first shared pin, and can also be directly input to the response protection monotonic counter chip through the external independent pin and the second independent pin. And after the response protection monotonic counter chip executes the external instruction to acquire data, the data can be output to the outside through the second internal pin, the first shared pin and the external shared pin, and the data can be directly output to the outside through the external independent pin and the second independent pin. Furthermore, on the one hand, the flexibility of the path through which the response protection monotonic counter chip receives instructions directed to the response protection monotonic counter chip independently is increased, and on the other hand, the flexibility of the path through which data acquired after the response protection monotonic counter chip executes the instructions independently is transmitted to the outside is increased.

In yet another embodiment, the answer protection monotonic counter chip does not include a second independent pin.

In this embodiment, the flash memory chip 210 and the response protection monotonic counter chip 220 are arranged in an overlapping manner in a direction perpendicular to the surface of the package carrier 200.

Thus, the area occupied by the flash memory chip module is saved.

In this embodiment, when the area of the flash memory chip 210 is smaller than the area of the answer protection monotonic counter chip 220, the flash memory chip 210 is located on the answer protection monotonic counter chip 220; when the area of the flash memory chip 210 is larger than the area of the answering protection monotonic counter chip 220, the answering protection monotonic counter chip 220 is located on the flash memory chip 210.

It should be noted that fig. 3 only schematically shows: when the area of the flash memory chip 210 is larger than the area of the answering protection monotonic counter chip 220, the answering protection monotonic counter chip 220 is located on the flash memory chip 210.

In other embodiments, when the area of the flash memory chip is larger than the area of the answer protection monotonic counter chip, the flash memory chip is located on the answer protection monotonic counter chip; and when the area of the flash memory chip is smaller than that of the answer protection monotonic counter chip, the answer protection monotonic counter chip is positioned on the flash memory chip.

In a further embodiment, the flash memory chip and the answer protection monotonic counter chip are arranged in an overlapping manner in a direction perpendicular to the surface of the package carrier.

Correspondingly, the embodiment of the utility model provides a packaging method who encapsulates above-mentioned flash memory chip module.

Referring to fig. 3, the method for packaging the flash memory chip module includes: providing a package carrier 200, wherein the package carrier 200 includes a plurality of external shared pins (e.g., IO _ a _1, IO _ a _2, … …, IO _ a _ n in fig. 3); providing a flash chip 210, wherein the flash chip 210 includes a plurality of first shared pins (e.g., IO _ a _1, IO _ a _2, … …, IO _ a _ n in fig. 3) and a plurality of first internal pins (e.g., IO _ C _1, IO _ C _2, … …, IO _ C _ n in fig. 3); providing an answer protection monotonic counter chip 220, wherein the answer protection monotonic counter chip 220 comprises a plurality of second internal pins (e.g., IO _ D _1, IO _ D _2, … …, IO _ D _ n in fig. 3); placing said flash memory chip 210 and said answer protection monotonic counter chip 220 on said package carrier 200; interconnecting the first internal pin and the second internal pin; interconnecting the first shared pin with the external shared pin; after the first shared pin and the external shared pin are interconnected, and after the first internal pin and the second internal pin are interconnected, the flash memory chip 210, the response protection monotonic counter chip 220, and the package carrier 200 are plastically packaged.

In this embodiment, the method of interconnecting the first internal pin and the second internal pin includes: the first and second internal leads are interconnected with metal leads 232.

In this embodiment, the method of interconnecting the first shared pin and the external shared pin includes: the first shared pin is interconnected with the external shared pin with a metal wire 231.

In other embodiments, a method of interconnecting the first internal pin and the second internal pin includes: bonding the flash memory chip and the answer protection monotonic counter chip before placing the flash memory chip and the answer protection monotonic counter chip on the packaging carrier.

In this embodiment, the package carrier 200 further includes a plurality of external independent pins (e.g., IO _ V _1, IO _ V _2, … …, IO _ V _ n in fig. 3), the flash chip 210 further includes a plurality of first independent pins (e.g., IO _ E _1, IO _ E _2, … …, IO _ E _ n in fig. 3), and the packaging method further includes: before the plastic package is performed, the first independent pin and the external independent pin are interconnected by a metal lead 233.

In other embodiments, the answer protection monotonic counter chip further comprises: a plurality of second independent pins. The packaging method further comprises the following steps: and before the plastic package, the second independent pin is interconnected with the external independent pin by adopting a metal lead.

FIG. 4 is a schematic diagram of a logical connection of a flash memory chip module according to another embodiment of the present invention; fig. 5 is a schematic structural diagram of a packaging principle of a flash memory chip module according to another embodiment of the present invention.

Referring to fig. 4 and 5, the flash memory chip module includes: a package carrier 300, the package carrier 300 comprising a plurality of external shared pins (e.g. IO _ Q _1, IO _ Q _2, … …, IO _ Q _ n in fig. 4), the external shared pins being used for obtaining the first external instruction.

With continued reference to fig. 4 and 5, the flash memory chip module further includes: a flash memory chip 310 located on the package carrier 300, and a reply-protection monotonic counter chip 320 located on the package carrier 300.

The answer protection monotonic counter chip 320 includes: several second shared pins (e.g. IO _ B _1, IO _ B _2, … …, IO _ B _ n in fig. 4).

The second shared pin is interconnected with the external shared pin, and the second shared pin is used for inputting the first external instruction into the response protection monotonic counter chip 320.

In the present embodiment, metal leads 331 are employed to interconnect the respective second shared pins and the external shared pin.

For example, the second shared pin IO _ B _1 is interconnected with the external shared pin IO _ Q _ 1; interconnecting the second shared pin IO _ B _2 with the external shared pin IO _ Q _ 2; the second shared pin IO _ B _ n is interconnected with the external shared pin IO _ Q _ n, etc.

Therefore, the second shared pin can obtain the first external instruction, and the first external instruction input response protection monotonic counter chip 320 is realized through the second shared pin.

In this embodiment, the answer protection monotonic counter chip 320 further includes: a second receiving and determining module 321, where the second receiving and determining module 321 is configured to determine the first external instruction and output the first instruction, or output a second instruction, or output the first instruction and the second instruction.

It should be noted that the first external instruction includes: at least one of an instruction pointing to the flash memory chip 310 and an instruction pointing to the answer protection monotonic counter chip 320, where the first instruction is an instruction formed according to the instruction pointing to the answer protection monotonic counter chip 320, and the second instruction is an instruction formed according to the instruction pointing to the flash memory chip 310.

Specifically, after the first external command is input to the response protection monotonic counter chip 320 through the second shared pin, the second receiving and determining module 321 determines that the first external command is: when the first external instruction only includes an instruction pointing to the answer protection monotonic counter chip 320, the second receiving and determining module 321 outputs the first instruction; when the first external command only includes a command directed to the flash memory chip 310, the second receiving and determining module 321 outputs the second command; when the first external instruction includes an instruction pointing to the flash memory chip 310 and an instruction pointing to the response protection monotonic counter chip 320, the second receiving and determining module 321 outputs the first instruction and the second instruction.

In this embodiment, the answering protection monotonic counter chip 320 further includes: a second control module 322, where the second control module 322 is configured to control the response protection monotonic counter chip 320 to execute the first instruction and output first information.

It should be noted that the first information is data obtained by the response-protected monotonic counter chip 320 executing the first instruction, and the data may include an execution state of the response-protected monotonic counter chip 320, data that needs to be transmitted to the outside and is obtained after the response-protected monotonic counter chip 320 executes the first instruction, and the like.

Specifically, in this embodiment, when the first external instruction includes an instruction pointing to the answer protection monotonic counter chip 320, the second control module 322 obtains the first instruction through the second receiving and determining module 321, and controls the answer protection monotonic counter chip 320 to execute the first instruction and output the first information.

The answer protection monotonic counter chip 320 further comprises: and a plurality of second internal pins (for example, IO _ P _1, IO _ P _2, … …, IO _ P _ n in fig. 4) for outputting the second instruction.

Specifically, in this embodiment, after the second internal pin obtains the second instruction from the second receiving and determining module 321, the second internal pin outputs the second instruction to the flash memory chip 310.

The flash memory chip 310 further includes: a plurality of first internal pins (for example, IO _ R _1, IO _ R _2, … …, IO _ R _ n in fig. 4), the first internal pins being interconnected with the second internal pins, and the first internal pins being configured to input the second instruction into the flash memory chip 310 and transmit second information from the flash memory chip 310 to the second internal pins.

Since the first internal pin and the second internal pin are interconnected, the first internal pin can acquire the second instruction and transmit second information to the second internal pin, that is, the second instruction is input into the flash memory chip 310 through the first internal pin and the second information is transmitted from the flash memory chip 310 to the second internal pin.

It should be noted that the second information is data obtained after the flash chip 310 executes the second instruction.

Since the second shared pin is used to input the first external instruction into the response protection monotonic counter chip 320, the second internal pin is used to output the second instruction, and the first internal pin is used to input the second instruction into the flash memory chip 310 and transmit the second information from the flash memory chip 310 to the second internal pin, in the first aspect, chips directly interconnected with the external shared pin and generating data transmission are reduced. Because the number of chips which are directly connected with external shared pins and generate data transmission is reduced, the number of the shared pins of the flash memory chip 310 is reduced, and therefore the wiring design complexity of the flash memory chip module is simplified, the packaging difficulty is reduced, and the yield of the flash memory chip module is increased; and the load of the control instruction which needs to be driven by the external shared pin is reduced, so that the design requirement of the driving capability of the external shared pin is reduced, and the power consumption of the flash memory chip module is reduced.

In the second aspect, the control instruction from the outside and directed to the flash memory chip 310 can be input to the flash memory chip 310 by responding to the protection monotonic counter chip 320, and the situation that the flash memory chip 310 executes the instruction can be obtained by responding to the protection monotonic counter chip 320, that is, the control flash memory chip 310 and the response protection monotonic counter chip 320 can be cooperatively used by responding to the protection monotonic counter chip 320. Because the monotonic counter chip 320 is protected by the response, the monotonic counter chip 320 and the flash memory chip 310 are controlled to be matched for use, so that the judgment and monitoring of the flash memory chip 310 are facilitated to be simplified and reduced, on one hand, the design complexity of a control logic circuit of the flash memory chip 310 is facilitated to be reduced, the power consumption of a flash memory chip module is reduced, on the other hand, the number of internal pins for data transmission between the flash memory chip 310 and the monotonic counter chip 320 is facilitated to be reduced, namely, the number of the first internal pins and the number of the second internal pins are facilitated to be beneficial to the simplification of the wiring design complexity of the flash memory chip module, the reduction of the packaging difficulty and the increase of the yield of the flash memory chip module; meanwhile, the number of contact times between the flash memory chip 310 and an external instruction is reduced, and the risk that the flash memory chip 310 is attacked when the external instruction is analyzed is reduced, so that the data security of the flash memory chip 310 is improved, and the confidentiality and the integrity of data transmission of a flash memory chip module are improved.

In this embodiment, metal leads 332 are employed to interconnect the respective first and second internal leads.

For example, a first internal pin IO _ R _1 and a second internal pin IO _ P _1 are interconnected; interconnecting the first internal pin IO _ R _2 and the second internal pin IO _ P _ 2; the first internal pin IO _ R _ n is interconnected with the second internal pin IO _ P _ n, etc.

In other embodiments, the flash chip 310 and the answer protection monotonic counter chip 320 are bonded to enable interconnection of the first internal lead and the second internal lead.

In this embodiment, the flash chip 310 further includes a first control module 311, and the first control module 311 is configured to control the flash chip 310 to execute the second instruction and output the second information to the first internal pin.

Specifically, in this embodiment, when the first external instruction includes an instruction pointing to the flash chip 310, the first control module 311 acquires a second instruction through the first internal pin, controls the flash chip 310 to execute the second instruction, and outputs the second information to the first internal pin.

In this embodiment, the answer protection monotonic counter chip 320 further includes: a second output determining module 323 and a second sending module 324, where the second output determining module 323 is configured to determine the first information, and output the first information, the second information, or the first information and the second information to the second sending module 324, or close the second sending module 324.

In this embodiment, the second sharing pin is interconnected with the second sending module 324, and the second sharing pin is further configured to transmit the first information, the second information, or the first information and the second information to the external sharing pin.

Specifically, in this embodiment, after acquiring the first information, the second output determining module 323 determines the first information: to determine whether the first information includes information that needs to be transmitted to the outside, and when the first information includes information that needs to be transmitted to the outside, output the first information to the second sending module 324. And, it is determined whether the flash memory chip 310 is attacked, i.e., whether the current state of the flash memory chip 310 is safe. When the current state of the flash chip 310 is safe, outputting second information to the second sending module 324; when the current state of the flash chip 310 is not unsafe, the second transmitting module 324 is turned off. After the second sending module 324 obtains the first information, the second information, or the first information and the second information, the first information, the second information, or the first information and the second information are transmitted to the outside through the second sharing pin and the external sharing pin.

Therefore, on one hand, the state of the flash memory chip module can be obtained, and on the other hand, a protection mechanism can be generated for the flash memory chip 310 to resist external attacks on the flash memory chip 310, so that the confidentiality and integrity of data transmission of the flash memory chip 310 are improved.

In other embodiments, the second output determining module is configured to determine the first information, and output the first information, the second information, third information, the first information and the second information, or the first information and the third information to the second sending module, where the third information is encrypted data or random error data. The second sharing pin is interconnected with the second sending module, and the second sharing pin is further used for transmitting the first information, the second information, the third information, the first information and the second information, or the first information and the third information to the external sharing pin.

Specifically, in another embodiment, after acquiring the first information, the second output determination module determines that the first information: and when the first information comprises the information which needs to be transmitted to the outside, outputting the first information to the second sending module. And, it is determined whether the flash memory chip is under attack, i.e., whether the current state of the flash memory chip is safe. When the current state of the flash memory chip is safe, outputting second information to the second sending module; and when the current state of the flash memory chip is not unsafe, outputting third information to the second sending module. And the second sending module is used for transmitting the first information, the second information, the third information, the first information and the second information, or the first information and the third information to the outside through the second sharing pin and the external sharing pin after acquiring the first information, the second information, the third information, the first information and the second information, or the first information and the third information. The third information is encrypted data, which means that the third information is data obtained by encrypting the second information. The third information is random error data, which means that the third information is random error data which is acquired by error infection and has misleading attackers.

In this embodiment, the package carrier 300 further includes a plurality of external independent pins (e.g., IO _ K _1, IO _ K _2, … …, IO _ K _ n in fig. 4), and the external independent pins are further configured to receive a third external instruction.

It should be noted that the third external instruction is a control instruction pointing to the answering protection monotonic counter chip 320, and the control instruction is an instruction that is independently executed by the answering protection monotonic counter chip 320 and implements the function of the answering protection monotonic counter chip 320.

In this embodiment, the answer protection monotonic counter chip 320 further includes: a plurality of second independent pins (e.g., IO _ F _1, IO _ F _2, … …, IO _ F _ n in fig. 4) interconnected with the external independent pins.

In the present embodiment, the metal wire 333 is used to interconnect the corresponding second independent pin and the external independent pin.

For example, the second independent pin IO _ F _1 is interconnected with the external independent pin IO _ K _ 1; interconnecting a second independent pin IO _ F _2 and an external independent pin IO _ K _ 2; the second independent pin IO _ F _ n is interconnected with the external independent pin IO _ K _ n, etc.

The second independent pin is configured to input the third external instruction into the response protection monotonic counter chip 320, and transmit fifth information from the response protection monotonic counter chip 320 to the external independent pin, where the fifth information is data obtained after the response protection monotonic counter chip 320 processes the third external instruction.

Specifically, in this embodiment, the external independent pin receives a third external instruction, the second independent pin obtains the third external instruction from the external independent pin, and inputs the third external instruction into the response protection monotonic counter chip 320; after the response protection monotonic counter chip 320 executes the third external instruction, fifth information is obtained, and the second independent pin transmits the fifth information to the external independent pin.

Therefore, an external instruction executed by the flash memory chip 310 in cooperation with the answer protection monotonic counter chip 320 is not required, and the external instruction can be input to the answer protection monotonic counter chip 320 through the external shared pin and the second shared pin, and can also be input to the answer protection monotonic counter chip 320 through the external independent pin and the second independent pin. Moreover, after the answer protection monotonic counter chip 320 executes the external instruction to obtain data, the data can be output to the outside not only through the external shared pin and the second shared pin, but also through the external independent pin and the second independent pin. Furthermore, on the one hand, flexibility of a path through which the response protection monotonic counter chip 320 receives an instruction directed to the response protection monotonic counter chip 320 independently is increased, and on the other hand, flexibility of a path through which data acquired after the response protection monotonic counter chip 320 executes the instruction independently is transmitted to the outside is increased.

In other embodiments, the answer protection monotonic counter chip does not include a second independent pin.

In other embodiments, the external stand-alone pin is configured to receive a second external instruction. The flash memory chip further includes: the first independent pins are used for inputting the second external instruction into a flash memory chip and transmitting fourth information from the flash memory chip to the external independent pins, and the fourth information is data obtained after the flash memory chip processes the second external instruction.

In other embodiments, the first independent pin and the external independent pin are interconnected using metal wires.

It should be noted that the second external instruction is a control instruction pointing to the flash memory chip, and the control instruction is an instruction executed independently by the flash memory chip to implement a function of the flash memory chip.

Specifically, in other embodiments, the external independent pin receives a second external instruction, and the first independent pin obtains the second external instruction from the external independent pin and inputs the second external instruction into the flash memory chip; and after the flash memory chip executes the second external instruction, fourth information is acquired, and the first independent pin transmits the fourth information to the external independent pin.

Therefore, an external instruction executed by the flash memory chip and the response protection monotonic counter chip in a matched mode is not needed, the external instruction can be input into the flash memory chip after being input into the response protection monotonic counter chip through the external sharing pin and the second sharing pin, and the external instruction can also be directly input into the flash memory chip through the external independent pin and the first independent pin. And after the flash memory chip executes the external instruction to acquire data, the data can be output to the outside through the first internal pin, the second shared pin and the external shared pin, and the data can be directly output to the outside through the external independent pin and the first independent pin. Furthermore, on the one hand, the flexibility of a path for the flash memory chip to receive an instruction independently pointing to the flash memory chip is increased, and on the other hand, the flexibility of a path for data acquired after the flash memory chip independently executes the instruction to be transmitted to the outside is increased.

In yet another embodiment, the flash memory chip does not include the first independent pin.

In this embodiment, the flash memory chip 310 and the response protection monotonic counter chip 320 are arranged in an overlapping manner in a direction perpendicular to the surface of the package carrier 300.

Thus, the area occupied by the flash memory chip module is saved.

In this embodiment, when the area of the flash memory chip 310 is smaller than the area of the answer protection monotonic counter chip 320, the flash memory chip 310 is located on the answer protection monotonic counter chip 320; when the area of the flash memory chip 310 is larger than the area of the answering protection monotonic counter chip 320, the answering protection monotonic counter chip 320 is located on the flash memory chip 310.

Fig. 5 is a schematic illustration of: a case where the flash memory chip 310 is located on the answer protection monotonic counter chip 320 when the area of the answer protection monotonic counter chip 320 is larger than the area of the flash memory chip 310.

Correspondingly, another embodiment of the present invention provides a method for packaging the flash memory chip module.

Referring to fig. 5, the method for packaging the flash memory chip module includes: providing a package carrier 300, wherein the package carrier 300 comprises a plurality of external shared pins (e.g. IO _ Q _1, IO _ Q _2, … …, IO _ Q _ n in fig. 5); providing a flash chip 310, wherein the flash chip 310 includes a plurality of first internal pins (e.g., IO _ R _1, IO _ R _2, … …, IO _ R _ n in fig. 5); providing an answer protection monotonic counter chip 320, the answer protection monotonic counter chip 320 comprising a number of second shared pins (e.g., IO _ B _1, IO _ B _2, … …, IO _ B _ n in fig. 5) and a number of second internal pins (e.g., IO _ P _1, IO _ P _2, … …, IO _ P _ n in fig. 5); placing said flash memory chip 310 and said answer protection monotonic counter chip 320 on said package carrier 300; interconnecting the first internal pin and the second internal pin; interconnecting the second shared pin with the external shared pin; after the second shared pin and the external shared pin are interconnected, and after the first internal pin and the second internal pin are interconnected, the flash memory chip 310, the response protection monotonic counter chip 320, and the package carrier 300 are plastically packaged.

In this embodiment, the method of interconnecting the first internal pin and the second internal pin includes: the first and second internal pins are interconnected with metal leads 332.

In this embodiment, the method of interconnecting the second shared pin and the external shared pin includes: the second shared pin is interconnected with the external shared pin with a metal lead 331.

In this embodiment, the package carrier 300 further includes a plurality of external independent pins (e.g., IO _ K _1, IO _ K _2, … …, IO _ K _ n in fig. 5), the answer protection monotonic counter chip 320 further includes a plurality of second independent pins (e.g., IO _ F _1, IO _ F _2, … …, IO _ F _ n in fig. 5), and the packaging method further includes: before the plastic package is performed, the second independent pin and the external independent pin are interconnected by using a metal lead 333.

In other embodiments, the flash memory chip further includes: a plurality of first independent pins. The packaging method further comprises the following steps: and before the plastic package, the first independent pin and the external independent pin are interconnected by adopting a metal lead.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present invention, and the scope of the present invention is defined by the appended claims.

Claims

1. A flash memory chip module, comprising:

the device comprises a packaging carrier and a control module, wherein the packaging carrier comprises a plurality of external sharing pins which are used for acquiring a first external instruction;

the flash memory chip is positioned on the packaging carrier and comprises a plurality of first sharing pins and a plurality of first internal pins, the first sharing pins are interconnected with the external sharing pins, the first sharing pins are used for inputting the first external instruction into the flash memory chip, and the first internal pins are used for outputting a first instruction;

the response protection monotonic counter chip is positioned on the packaging carrier and comprises a plurality of second internal pins, the second internal pins are interconnected with the first internal pins, and the second internal pins are used for inputting the first instruction into the response protection monotonic counter chip and transmitting first information from the response protection monotonic counter chip to the first internal pins.

2. The flash memory chip module of claim 1, wherein the flash memory chip further comprises: and the first receiving and judging module is used for judging the first external instruction and outputting the first instruction, or outputting the second instruction, or outputting the first instruction and the second instruction.

3. The flash memory chip module of claim 2, wherein the flash memory chip further comprises: and the first control module is used for controlling the flash memory chip to execute the second instruction and outputting second information.

4. The flash memory chip module of claim 3, wherein the flash memory chip further comprises: the first output judgment module is used for judging the first information and outputting the first information, the second information or the first information and the second information to the first sending module, or closing the first sending module.

5. The flash chip module of claim 4, wherein the first shared pin is interconnected with the first sending module, the first shared pin further for transmitting the first information, the second information, or both the first information and the second information to the external shared pin.

6. The flash memory chip module of claim 3, wherein the flash memory chip further comprises: the first output judgment module is used for judging the first information and outputting the first information, the second information, the third information, the first information and the second information or the first information and the third information to the first sending module, and the third information is encrypted data or random error data.

7. The flash chip module of claim 6, wherein the first shared pin is interconnected with the first sending module, the first shared pin further for transmitting the first information, the second information, the third information, the first information and the second information, or the first information and the third information to the external shared pin.

8. The flash memory chip module of claim 1 wherein the package carrier further comprises a number of external stand-alone pins for receiving a second external command; the flash memory chip further includes: the first independent pins are used for inputting the second external instruction into a flash memory chip and transmitting fourth information from the flash memory chip to the external independent pins, and the fourth information is data obtained after the flash memory chip processes the second external instruction.

9. The flash memory chip module of claim 8 wherein the external stand-alone pin is further configured to receive a third external command; the answer protection monotonic counter chip further comprises: the second independent pins are used for inputting the third external instruction into a response protection monotonic counter chip and transmitting fifth information from the response protection monotonic counter chip to the external independent pins, and the fifth information is data obtained after the response protection monotonic counter chip processes the third external instruction.

10. The flash memory chip module of any of claims 1 to 9, wherein the reply-protection monotonic counter chip further comprises a second control module configured to control the reply-protection monotonic counter chip to execute the first instruction and output first information to the second internal pin.

11. The flash memory chip module of any of claims 1 to 9, wherein said flash memory chip is arranged in overlapping relation with said answer-protection monotonic counter chip in a direction perpendicular to a surface of said package carrier.

12. The flash memory chip module of any of claims 1 to 9, wherein said flash memory chip and said reply-protect monotonic counter chip are arranged along a direction of said package carrier surface.

13. A flash memory chip module, comprising:

the response protection monotonic counter chip is positioned on the packaging carrier and comprises a plurality of second shared pins and a plurality of second internal pins, the second shared pins are interconnected with the external shared pins, the second shared pins are used for inputting the first external instruction into the response protection monotonic counter chip, and the second internal pins are used for outputting a second instruction;

the flash memory chip is positioned on the packaging carrier and comprises a plurality of first internal pins, the first internal pins are interconnected with the second internal pins, and the first internal pins are used for inputting the second instruction into the flash memory chip and transmitting second information from the flash memory chip to the second internal pins.

14. The flash chip module of claim 13, wherein the reply protection monotonic counter chip further comprises: and the second receiving and judging module is used for judging the first external instruction and outputting a first instruction, or outputting a second instruction, or outputting the first instruction and the second instruction.

15. The flash chip module of claim 14 wherein the reply protection monotonic counter chip further comprises: and the second control module is used for controlling the response protection monotonic counter chip to execute the first instruction and outputting first information.

16. The flash chip module of claim 15 wherein the reply protection monotonic counter chip further comprises: the second output judgment module is used for judging the first information and outputting the first information, the second information or the first information and the second information to the second sending module, or closing the second sending module.

17. The flash chip module of claim 16, wherein the second shared pin is interconnected with the second transmit module, the second shared pin further for transmitting the first information, the second information, or the first and second information to the external shared pin.

18. The flash chip module of claim 15 wherein the reply protection monotonic counter chip further comprises: the second output judgment module is used for judging the first information and outputting the first information, the second information, the third information, the first information and the second information or the first information and the third information to the second sending module, and the third information is encrypted data or random error data.

19. The flash chip module of claim 18, wherein the second shared pin is interconnected with the second transmit module, the second shared pin further for transmitting the first information, the second information, the third information, the first information and the second information, or the first information and the third information to the external shared pin.

20. The flash memory chip module of claim 13 wherein the package carrier further comprises a plurality of external stand-alone pins, the external stand-alone pins further configured to receive a third external command; the answer protection monotonic counter chip further comprises: the second independent pins are used for inputting the third external instruction into a response protection monotonic counter chip and transmitting fifth information from the response protection monotonic counter chip to the external independent pins, and the fifth information is data obtained after the response protection monotonic counter chip processes the third external instruction.

21. The flash memory chip module of claim 20, wherein the external stand-alone pin is configured to receive a second external command; the flash memory chip further includes: the first independent pins are used for inputting the second external instruction into a flash memory chip and transmitting fourth information from the flash memory chip to the external independent pins, and the fourth information is data obtained after the flash memory chip processes the second external instruction.

22. The flash memory chip module of any one of claims 13 to 21, wherein the flash memory chip further comprises a first control module, the first control module being configured to control the flash memory chip to execute the second instruction and output second information to the first internal pin.

23. The flash memory chip module of any of claims 13 to 21, wherein said flash memory chip is arranged in overlapping relation with said answer-protection monotonic counter chip in a direction perpendicular to a surface of said package carrier.

24. The flash memory chip module of any of claims 13 to 21, wherein said flash memory chip and said reply-protect monotonic counter chip are arranged along a direction of said package carrier surface.