CN108664428B

CN108664428B - Communication method based on FPGA (field programmable Gate array), FPGA controller and USB (Universal Serial bus) adapter

Info

Publication number: CN108664428B
Application number: CN201711367607.3A
Authority: CN
Inventors: 蔡臻昱; 彭晓林; 吴乾科
Original assignee: Shenzhen Siglent Technologies Co Ltd
Current assignee: Shenzhen Siglent Technologies Co Ltd
Priority date: 2017-12-18
Filing date: 2017-12-18
Publication date: 2020-05-05
Anticipated expiration: 2037-12-18
Also published as: CN108664428A

Abstract

Provided are a communication method based on an FPGA, an FPGA controller and a USB adapter. The communication method comprises the steps of acquiring, analyzing, judging and sending load data, packaging and returning reply data, and can independently realize the communication process of the drive layer USB. The FPGA controller adapted to the communication method comprises an FIFO module, a data transceiver module and a state machine module, the phenomenon of data backlog can not occur in the communication process of various data by adopting the FIFO module, the data transceiver module strengthens the transmission capability of the data, and the state machine module is adopted to realize the process of coordinating and processing the data between the FIFO module and the data transceiver module. The USB adapter comprises the USB controller and the FPGA controller, the USB adapter is used for realizing another communication mode between the USB master device and the USB slave device, the whole circuit structure of the adapter is simplified, and the use cost of the adapter is reduced.

Description

Communication method based on FPGA (field programmable Gate array), FPGA controller and USB (Universal Serial bus) adapter

Technical Field

The invention relates to the technical field of communication, in particular to a communication method based on an FPGA, an FPGA controller and a USB adapter.

Background

USB (Universal Serial Bus) is a Universal Serial Bus protocol, which has the advantages of high data transmission efficiency and convenient use, and the USB standard interface has become one of the most widely used interfaces in the existing computer devices. The communication protocols of USB2.0 and USB3.0 have gained public acceptance and are widely used in the field of electronics.

Since information interaction between devices communicating by using a USB communication protocol is usually completed by using a mode of initiating by a master device and responding by a slave device, related USB devices are generally classified into master/slave devices, wherein the USB master device refers to devices such as a host computer, a PC, and a server having a USB communication function, and the USB slave device refers to devices such as a USB disk, a mouse, and a printer having a USB communication function. In order to realize the communication function between the USB master device and the USB slave device, the communication response speed between the master device and the slave device needs to be matched, and in order to achieve the synchronization performance of receiving and sending communication data between the master device and the slave device, a communication adapter is often used to coordinate the communication process between the USB master device and the USB slave device, and the existing communication adapter usually uses a communication chip to centrally process a bottom layer protocol and a driver layer protocol of USB communication. Since such communication chips need to be competent for large data, fast response working requirements, excessive requirements on their performance make the peripheral circuits of such communication chips complex and make communication adaptation application costly.

Disclosure of Invention

The invention mainly solves the technical problem of how to realize the USB communication function between a master device and a slave device by means of the FPGA. In order to solve the above problems, the present invention provides a solution based on FPGA, that is, a communication method based on FPGA, an FPGA controller, and a USB adapter.

A communication method based on an FPGA controller comprises the following steps: the FPGA acquires load data through an FIFO module of the FPGA, wherein the load data comprises a protocol header and read-write data, and the protocol header comprises a write command or an inquiry command; the FPGA analyzes the load data through a data receiving and transmitting module of the FPGA; the FPGA judges the command type of the protocol header through a state machine thereof, if the command is a write command, the FPGA sends corresponding read-write data to the external communication equipment through a data receiving and sending module thereof, and if the command is an inquiry command, the FPGA sends the corresponding read-write data to the external communication equipment through the data receiving and sending module thereof and receives reply data returned by the external communication equipment.

The communication method provided by the embodiment adopts the USB co-processing mechanism, and adopts the FPGA to independently complete the USB communication process of the drive layer, so that the operation command and the reading, analyzing and sending processes of the related communication data are tightly combined, the phenomenon that the bottom layer USB communication process and the drive layer USB communication process are mutually influenced is effectively avoided, and the processing speed of the data load from the USB master device to the USB slave device is increased.

An FPGA controller for communication, comprising: FIFO module, data transceiver module and state machine module. The FIFO module is used for signal connection with USB main equipment and is used for caching load data; the data transceiver module is used for being in communication connection with the USB slave device and is used for analyzing the load data and sending read-write data in the load data; the state machine module is used for controlling the communication process of the FIFO module and the data transceiver module. When the external communication device returns reply data to the data transceiver module, the data transceiver module is used for receiving and packaging the reply data.

The FPGA controller provided in the above embodiment adopts the FIFO module to buffer the load data in a form of data temporary storage, so that data backlog and even a communication stagnation phenomenon do not occur in a communication process. In addition, the FPGA controller adopts a data transceiver module to independently process the analysis or encapsulation work of data, thereby being beneficial to processing the load data at the same time with the FIFO module. In addition, the state machine module does not undertake the data processing work and is only used for coordinating the data communication process, so that the FIFO module and the data transceiver module can fully utilize the functions of the FIFO module and the data transceiver module in the data processing process, the communication rate is increased, and the bandwidth is increased.

A USB adapter for communication, comprising: USB controller and FPGA controller. The USB controller is used for being in communication connection with the USB main device and the FPGA controller and used for executing bottom layer USB protocol communication, and the FPGA controller is used for executing driving layer USB protocol communication.

The USB adapter provided in the above embodiment divides the USB data communication process into two stages, which are driver layer USB communication and protocol layer USB communication, on one hand, coordinates the communication response speed between the USB master device and the USB slave device, and on the other hand, improves the hardware operating speed, thereby ensuring the data communication effect between the USB master device and the USB slave device. Moreover, the FPGA controller has high integration level and low application cost, thereby being beneficial to simplifying the whole circuit structure of the USB adapter and reducing the use cost of the USB adapter.

Drawings

FIG. 1 is a schematic diagram of an FPGA controller according to an embodiment;

FIG. 2 is a schematic diagram of the structure of payload data;

FIG. 3 is a schematic flowchart of a FPGA-based communication method according to a second embodiment;

fig. 4 is a schematic diagram of the working principle of the three FPGA state machine modules according to the embodiment.

Detailed Description

The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.

Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.

The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).

The USB protocol generally includes an underlying protocol and a driver layer protocol, where the underlying USB protocol includes processing mechanisms such as identification, authentication, and verification of a data packet (referred to as USB communication data, i.e., payload data), and the driver layer USB protocol includes processing mechanisms such as parsing, encapsulation, and transmission of the data packet.

The load data refers to a data packet capable of realizing USB communication, the data packet often includes a USB protocol and read-write data corresponding to the USB protocol, the USB protocol is a main basis for determining a format and a type of the read-write data, and the read-write data corresponding to the USB protocol is a main basis for determining communication contents.

The FPGA, as a programmable logic device, has high integration level and abundant logic resources, is very convenient to develop, and has unique advantages in digital signal processing or hardware algorithm realization due to high FPGA processing speed. If the process of processing the USB protocol is realized on the FPGA, more FPGA on-chip resources are occupied, and the hardware acceleration effect of the FPGA in processing the digital signals is not facilitated. Therefore, the FPGA-based communication method is adopted to independently process the USB protocol of the driving layer, so that the digital signal processing performance of the FPGA can be fully exerted.

Embodiment one, an FPGA controller for communication, as shown in fig. 1.

In this embodiment, the USB controller 101 and the FPGA controller 102 are sequentially connected between the USB master device D1 and the USB slave device D2, wherein the USB controller 101 and the USB master device D1 are connected in a USB communication manner, the FPGA controller 102 and the USB slave device D2 are connected in a USB communication or IO communication manner, and the USB controller 101 and the FPGA controller 102 are connected in a bus.

In this embodiment, the USB controller 101 and the FPGA controller 102 constitute a USB adapter, the former is used for processing a bottom layer USB protocol, and the latter is used for processing a driver layer USB protocol, and the two are in communication connection and cooperate with each other, so that a hardware acceleration effect during USB communication is greatly enhanced.

In this embodiment, the USB controller 101 has a functional component for processing the underlying USB protocol, and the functional component can implement the functions of identifying, authenticating, and verifying the communication data, so as to reasonably determine the transmission form of the communication data, for example, complete the communication work by using the communication standard such as the USB2.0 protocol or the USB3.0 protocol.

In the present embodiment, the FPGA controller 102 includes a FIFO module 1021, a data transceiving module 1023, and a state machine module 1022. The FIFO module 1021 is signally connected to the USB host (the FIFO module 1021 is bussed to the USB controller 101), and is used to buffer payload data. The data transceiver module 1023 is communicatively connected to the USB slave device D2, the data transceiver module 1023 is used for parsing payload data and sending read-write data related to a protocol header, and an IO control module is arranged in the data transceiver module 1023 for transceiving data. The state machine module 1022 is connected to the FIFO module 1011 via a FIFO interface, and is connected to the data transceiver module 1023 via a state machine interface, and the state machine module 1022 controls the communication process between the FIFO module 1021 and the data transceiver module 1023.

In this embodiment, the payload data is often in the form of a data packet, in which some data with a specific meaning is present. Referring to fig. 2, payload data A1 includes a protocol header a11 and read/write data a12, and the protocol header a11 includes two types of operation commands, write command a111 or query command a112 (the protocol header for a payload data has only one type of operation command). The write command a111 is used to guide the data write process to the USB slave device, and therefore, the read-write data a12 corresponding to the write command is write content. The query command a112 is used to guide the return process of the reply result to the USB slave device, so that the read-write data a12 corresponding to the query command a112 is a query question, and the reply result corresponding to the query question is reply data.

Embodiment two, a communication method based on FPGA, as shown in fig. 3.

At the beginning of communication, the USB master device D1 sends payload data to the USB controller 101, and the USB controller 101 checks the received payload data, where the checking includes packet flag bit identification, bottom layer USB protocol authentication, and packet integrity check, and then the USB controller 101 sends the checked payload data to the FIFO module 1021. Thereafter, the FPGA controller 102 will receive the payload data and process the data.

In this embodiment, the communication method provided is a partial communication mechanism between USB master and slave devices, and mainly implements a processing function of a driver layer USB protocol, and will be described in detail with reference to fig. 1, where the communication method includes the following steps:

201, the FIFO module 1021 retrieves payload data.

In the initial stage of communication between the USB master device D1 and the USB slave device D2, the USB master device D1 actively sends payload data to the USB slave device D2, and in order to increase the response speed of the USB slave device D2 to the payload data, the FPGA controller 102 acquires the payload data to perform drive layer processing on the payload data, and the process of acquiring the payload data is performed by the state machine module 1022 in the FPGA controller 102 controlling the FIFO module 1021.

202, the data transceiver module 1023 parses the payload data to obtain a protocol header and read/write data.

The state machine module 1022 reads the payload data in the FIFO module 1021 and sends the payload data to the data transceiving module 1023, and the state machine module 1022 controls the data transceiving module 1023 to parse the payload data and obtain the protocol header and read-write data from the payload data. The protocol header includes an operation command, either a write command or a query command. The read-write data corresponding to the write command is the write content, and the read-write data corresponding to the inquiry command is the inquiry problem.

203, the state machine module 1022 determines whether the protocol header includes a write command.

And identifying the identification characters of the protocol header to obtain the operation command type corresponding to the data load, wherein the operation command is a write command or a query command.

204, if the protocol header includes a write command, the data transceiver module 1023 sends the read/write data to the external communication device.

The state machine module 1022 controls the data transceiving module 1023 to transmit read-write data (i.e., write content) to the external communication device, which is the USB slave device D2.

After step 204 is complete, the system again proceeds to steps 201 through 204.

205, if the protocol header does not include a write command, the data transceiver module 1023 sends the read/write data to the external communication device.

The state machine module 1022 controls the data transceiving module 1023 to transmit read-write data (i.e., inquiry question) to the external communication device, which is the USB slave device D2. The USB slave device not only receives the read-write data, but also returns corresponding reply data according to the query question. After step 205 is complete, the system proceeds to step 206.

In this embodiment, since only two command types of the write command and the query command are included in the payload data, the case where the protocol header does not include the write command is regarded as the case where the protocol header includes the query command.

206, the data transceiver module 1023 receives and encapsulates the reply data.

The data transceiving module 1023 receives the reply data from the USB slave D2, and combines the reply data as read-write data with the protocol header corresponding to the inquiry command, thereby forming new payload data, thereby completing the encapsulation operation of the reply data.

207, the FIFO 1021 buffers the encapsulated reply data.

The state machine 1022 writes the payload data (i.e., the encapsulated reply data) described in step 206 to the FIFO module 1021 to buffer the payload data. The purpose of this step is to quickly transfer the reply data and complete the encapsulation of subsequent reply data.

208, the FIFO 1021 sends the encapsulated reply data.

The state machine 1022 controls the FIFO module 1021 to send the buffered payload data to the USB controller 101, and the USB controller checks the payload data and sends it to the USB host device D1, thereby completing the return of the reply data.

In another embodiment, during the process of completing the return work of a reply data, steps 205 to 208 are executed a plurality of times, that is, the USB master device D1 sends a plurality of sets of payload data with query command to the USB slave device D2 in a short time, and at this time, the FPGA controller 102 has the function of processing a plurality of sets of payload data simultaneously. In this case, the data transceiver module 1023 receives multiple sets of payload data continuously, analyzes the payload data, latches the protocol headers of the payload data in order of priority, and sends the read/write data to the USB slave device D2. Since the USB slave device D2 has different times for processing the read-write data or different priority orders for returning the reply data, the return order of the reply data does not follow the transmission order of the read-write data. At this time, the data transceiver module 1023 actively recognizes the priority flag of the returned reply data, and obtains the protocol header matching the priority flag from the latch unit according to the priority flag, thereby performing the operation of step 206 on the reply data.

In the third embodiment, the state machine module runs a flow chart, as shown in fig. 4.

Since the state machine module 1022 is a control component in the FPGA controller 102, the present embodiment will use the active control process of the state machine module 1022 as a main line to describe in detail the processing process of the load data by the FPGA controller, which includes four processing steps, respectively:

301, the state machine module 1022 enters an "idle" state.

The state is an initial state of the state machine module 1022, and the state machine module 1022 identifies the data storage state in the FIFO module 1021 in either an active or passive manner.

In this state, the state machine module 1022 will control the FIFO module 1021 to enable its write operation to acquire payload data from the USB controller 101 at any time.

302, the state machine module 1022 enters a "read FIFO" state.

After the FIFO module 1021 is written with payload data from the USB controller, the state machine module 1022 determines that the FIFO module 1021 is not empty, and at this time, the state machine module 1022 enters a "read FIFO" state. In this state, the state machine module 1022 reads the payload data in the FIFO module 1021 and sends the payload data to the data transceiving module 1023.

In this step, the state machine module 1022 transmits payload data to the data transceiver module 1023, the payload data exists in the form of a data stream, so the state machine module 1022 controls the data transceiver module 1023 to parse the payload data from the data stream to obtain a protocol header and read/write data, and then the state machine module 1022 determines whether the obtained protocol header includes a write command or a query command.

If the protocol header includes a write command, the state machine module 1022 performs a write operation on the disabled FIFO module 1021 (i.e., the FIFO write operation is not enabled), and at this time, the FIFO module 1021 does not receive data any more, and the purpose of this operation is to temporarily close the data buffering function of the FIFO module 1021, preferentially process the received payload data, ensure the data processing speed, and avoid the data congestion phenomenon caused by receiving too much payload data. Then, the state machine module 1022 sends the read-write data (i.e., the write content) obtained by the analysis to the USB slave device D2 through the control data transceiver module 1023.

If a query command is included in the protocol header, the state machine module 1022 will latch the protocol header with the latch to perform an encapsulation operation on reply data from the USB slave device, and hold the write enable operation of the FIFO module 1021 to cache the reply data from the USB slave device D2. Then, the state machine module 1022 sends the read-write data (i.e. query question) obtained by parsing to the USB slave device D2 through the control data transceiver module 1023.

When the state machine module 1022 recognizes that the FIFO module 1021 is empty and has completely transmitted payload data to the data transceiver module 1023, indicating that the processing is completed or is about to be completed, the state machine module 1022 will enter the next state. Conversely, when the state machine module 1022 recognizes that the FIFO module 1021 is not empty or does not completely transmit payload data to the data transceiver module 1023, indicating that the payload data has not been processed, the state machine module 1022 will continue to enter the "read FIFO" state.

303, the state machine module 1022 enters a "wait" state.

The state machine module 1022 enters the "wait" state because the FIFO module 1021 is empty and has all sent payload data. In this state, the state machine module 1022 determines the write operation state of the FIFO module 1021, and if the write operation fails, indicating that the USB slave D2 does not reply with data, the state machine module 1022 enters the "idle" state in step 301. If the write operation of the FIFO 1021 is enabled, indicating that the USB slave device D2 has reply data, the state machine module 1022 will wait for the reply data of the USB slave device D2, and the state machine module 1022 will enter the next state when the reply data is received by the data transceiving module 1023 or the reply times out.

304, the state machine module 1022 enters a "write FIFO" state.

In this state, the state machine module 1022 controls the data transceiver module 1023 to receive reply data returned from the device D2 by USB (the reply data is null in case of reply timeout), and to combine the reply data with the latched protocol header (the protocol header has been processed, which is adapted to the protocol form of the reply data) and encapsulate it as new payload data. Then, the state machine module 1022 writes the encapsulated payload data into the FIFO module 1021, and writes the payload data into the FIFO module 1021, which facilitates to quickly release the resources of the data transceiver module 1023. Thereafter, the state machine module 1022 will control the FIFO module 1021 to send the new payload data to the USB controller 101.

When the state machine module 1022 recognizes that the FIFO module is empty and has all sent payload data to the USB controller 101, the state machine module 1022 will enter the "idle" state in step 301. Conversely, when the state machine module 1022 recognizes that the FIFO module is not empty or does not completely send payload data to the USB controller 101, the state machine module 1022 will continue to enter the "write FIFO" state.

In this embodiment, after receiving the payload data from the FIFO module 1021, the USB controller 101 performs a verification process on the payload data, and then sends the verified payload data to the USB host device D1.

The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.

Claims

1. A communication method based on FPGA is characterized by comprising the following steps:

the FPGA acquires load data through an FIFO module of the FPGA, wherein the load data comprises a protocol header and read-write data, and the protocol header comprises a write command or an inquiry command;

the FPGA analyzes the load data through a data receiving and transmitting module of the FPGA;

the FPGA judges the command type of the protocol header through a state machine thereof, if the command is a write command, the FPGA sends corresponding read-write data to external communication equipment through a data transceiver module thereof, and if the command is an inquiry command, the FPGA sends the corresponding read-write data to the external communication equipment through the data transceiver module thereof and receives reply data returned by the external communication equipment;

when the protocol header comprises a query command, the read-write data is a query question, and the FPGA transmits reply data returned by the external communication device back, including: the FPGA packages the reply data through a data transceiver module of the FPGA, a state machine of the FPGA writes the packaged reply data into the FIFO module, and the FPGA sends the packaged reply data through the FIFO module; the data transceiver module actively identifies the priority mark of the returned reply data, acquires the corresponding protocol header according to the priority mark, and combines the reply data serving as read-write data with the protocol header corresponding to the query command to form new payload data.

2. An FPGA controller for communication is characterized by comprising an FIFO module, a data transceiver module and a state machine module;

the FIFO module is used for signal connection with USB main equipment and is used for caching load data; the payload data comprises a protocol header and read-write data, and the protocol header comprises a write command or an inquiry command;

the data transceiver module is used for being in communication connection with the USB slave device and is used for analyzing the load data and sending read-write data in the load data;

the state machine module is used for controlling the communication process of the FIFO module and the data transceiver module, and comprises: the state machine module reads load data in the FIFO module and sends the load data to the data transceiver module, judges the command type of the protocol head analyzed by the data transceiver module, controls the data transceiver module to send corresponding read-write data to external communication equipment if the command is a write command, and controls the data transceiver module to send corresponding read-write data to the external communication equipment and receive reply data returned by the external communication equipment if the command is an inquiry command; when the data transceiver module receives the reply data, the state machine module controls the data transceiver module to encapsulate the reply data, controls the encapsulated reply data to be written into the FIFO module, and controls the FIFO module to transmit the encapsulated reply data; the data transceiver module actively identifies the priority mark of the returned reply data, acquires the corresponding protocol header according to the priority mark, and combines the reply data serving as read-write data with the protocol header corresponding to the query command to form new payload data.

3. A USB adapter for communication, comprising a USB controller and an FPGA controller as claimed in claim 2;

the USB controller is used for being in communication connection with a USB main device and the FPGA controller and is used for operating a bottom USB protocol;

the FPGA controller is used for executing a driving layer USB protocol.