CN212340075U - Array speed measuring target test data storage device - Google Patents
Array speed measuring target test data storage device Download PDFInfo
- Publication number
- CN212340075U CN212340075U CN202020495431.0U CN202020495431U CN212340075U CN 212340075 U CN212340075 U CN 212340075U CN 202020495431 U CN202020495431 U CN 202020495431U CN 212340075 U CN212340075 U CN 212340075U
- Authority
- CN
- China
- Prior art keywords
- circuit
- input
- data storage
- storage device
- array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
The utility model provides an array speed measuring target test data storage device, which comprises a plurality of signal input interfaces, a signal conditioning circuit, a controller and a data memory; the plurality of signal input interfaces comprise a front target signal input interface and a rear target signal input interface; the input end of the signal conditioning circuit is connected with the output end of each signal input interface, and the output end of the signal conditioning circuit is connected with an I/O port of the controller, and the signal conditioning circuit comprises a filter circuit and a shaping circuit; the controller comprises a timing digital circuit, the input end of the timing digital circuit is connected with the I/O port, and the output end of the timing digital circuit is connected with the memory through an input data bus; wherein the clocked digital circuit includes a plurality of counter modules. Compared with the prior art, the utility model discloses convenient quick arrangement installation has simplified the test installation. Meanwhile, the fragment dynamic parameters of multiple channels can be measured.
Description
Technical Field
The utility model relates to an ammunition power test technical field especially relates to a test data storage device such as broken piece speed and angle of departure are measured to array target.
Background
In the test process of the explosion field, the parameters of the fragments are mainly measured by the speed, the dispersion angle and the like of the fragments.
At present, a large-area on-off target or a distributed steel plate target is mainly used for testing to obtain related parameters. However, the conventional test method has the following problems:
(1) the existing speed measurement product only aims at single-channel or double-channel speed measurement signal conditioning, when a plurality of targets exist, a plurality of devices need to be equipped at present, and a measured object is single.
(2) Aiming at the array targets, signal conditioning of a single target is not needed, and signals of a plurality of targets need to be synchronously processed and stored and uploaded to an upper computer. But the existing speed measuring device has no data processing and storing device.
Disclosure of Invention
An object of the utility model is to provide an array target test data storage device that tests speed to the measurand object that appears is single in solving the fragmentation test procedure, and the test procedure is loaded down with trivial details, test data is not accurate enough, the inconvenient scheduling problem of data processing.
The utility model provides an array speed measuring target test data storage device, which comprises a plurality of signal input interfaces, a signal conditioning circuit, a controller and a data memory; the plurality of signal input interfaces comprise a front target signal input interface and a rear target signal input interface; the input end of the signal conditioning circuit is connected with the output end of each signal input interface, and the output end of the signal conditioning circuit is connected with an I/O port of the controller, and the signal conditioning circuit comprises a filter circuit and a shaping circuit; the controller comprises a timing digital circuit, the input end of the timing digital circuit is connected with the I/O port, and the output end of the timing digital circuit is connected with the memory through an input data bus; wherein the clocked digital circuit includes a plurality of counter modules.
According to other embodiments, the signal conditioning circuit includes an operational amplifier U1 and a comparator U2 connected in series.
Further, the non-inverting input terminal of the operational amplifier U1 is connected to the signal input interface through the resistors R1 and R3 connected in series, and is grounded through the capacitor C6; the inverting input end is grounded through a resistor R2 and is connected with the output end of the operational amplifier U1 through a resistor R4; the resistor R1 and the resistor R3 are connected with the output end of the operational amplifier U1 through a capacitor C7; the output terminal of the operational amplifier U1 is connected to the negative input terminal of the comparator U2 through a resistor R5.
Further, the positive input terminal of the comparator U2 is connected to the parameter value input terminal through a resistor R7, and is connected to the output terminal of the comparator U2 through a resistor R6 and a diode D1 connected in series.
According to other embodiments, the signal conditioning circuit further comprises a high-speed optical coupler conversion circuit connected to the output of the comparator U2.
Optionally, the operational amplifier U1 is implemented as an OP07 integrated circuit. The comparator U2 is an LM339 integrated circuit.
Optionally, the controller comprises an FPGA and peripheral circuits thereof; the memory adopts an FRAM chip of an SPI interface.
Optionally, the memory is a dual-port RAM, an input end of the memory is connected with the timing digital circuit through an input data bus, and an output end of the memory is connected with the communication module and the display module through an output data bus.
According to other embodiments, the communication module is communicatively coupled to the host computer.
Optionally, the communication module includes at least one of an RS485 module and an ethernet communication module.
Based on above-mentioned technical scheme, compare with prior art, the utility model discloses convenient quick arrangement installation has simplified the test installation. Meanwhile, the fragment dynamic parameters of multiple channels can be measured.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments of the invention, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are described herein, serve to provide a further understanding of the invention and constitute a part of this specification, and the exemplary embodiments and descriptions thereof are provided for explaining the invention without unduly limiting it. In the drawings:
fig. 1 is a schematic structural diagram of an array speed target test data storage device according to an embodiment of the present invention;
fig. 2 is an input signal conditioning circuit according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
Unless specifically stated otherwise, the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present invention. Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description.
The utility model is used for in the test process in the explosion field, to the parameter measurement of fragment, for example light curtain system of testing speed, further for example laser light curtain system of testing speed, X-ray light curtain system of testing speed etc. mainly include preceding target light curtain and back target light curtain, preceding target light curtain and back target light curtain set gradually in emitter the place ahead along on shot or fragment transmitting direction's the route, and distance between the two is confirmed.
Fig. 1 is according to the utility model discloses an array tests speed target test data storage device schematic structure, this array tests speed target test data storage device can be used to above-mentioned light curtain system of testing speed for example.
As shown in fig. 1, the array tachometer target test data storage device includes a plurality of signal input interfaces, a signal conditioning circuit, a controller and a data storage.
The signal input interface is used for inputting array speed measuring target test signals and comprises a front target signal input interface and a rear target signal input interface.
The input end of the signal conditioning circuit is connected with the output end of the input interface, the output end of the signal conditioning circuit is connected with the I/O port of the controller, and the signal conditioning circuit comprises a filter circuit and a shaping circuit and is used for conditioning an input signal into a standard controller input signal.
As shown in fig. 2, according to the embodiment of the present invention, the signal conditioning circuit includes an operational amplifier U1 and a comparator U2,
the non-inverting input terminal of the operational amplifier U1 is connected to the signal input interface through series-connected resistors R1 and R3, and is grounded through a capacitor C6. The inverting input terminal is connected to ground through a resistor R2 and to the output terminal of the operational amplifier U1 through a resistor R4. The resistor R1 and the resistor R3 are connected with the output end of the operational amplifier U1 through a capacitor C7.
The operational amplifier U1 is powered by a positive and negative 15V power supply, the positive power supply end is grounded through parallel capacitors C4 and C5, and the negative power supply end is grounded through parallel capacitors C2 and C3.
The output terminal of the operational amplifier U1 is connected to the negative input terminal of the comparator U2 through a resistor R5. The positive input end of the comparator U2 is connected with the parameter value input end through a resistor R7, and is connected with the output end of the comparator U2 through a resistor R6 and a diode D1 which are connected in series.
The comparator U2 is powered by 15V power supply, and its output terminal is connected with power supply terminal and ground terminal through a resistor R8 and a resistor R9 respectively.
Optionally, the signal conditioning circuit further comprises a high-speed optical coupler conversion circuit connected to the output end of the comparator U2.
The operational amplifier U1 may be implemented as an OP07 integrated circuit. The comparator U2 may be implemented as an LM339 integrated circuit.
The test signal input by the signal input interface is converted into a standard controller input signal after passing through the signal conditioning circuit, and is input into the controller through the I/O port.
The controller comprises a timing digital circuit, the input end of the timing digital circuit is connected with the I/O port, and the output end of the timing digital circuit is connected with the memory through an input data bus. The timing digital circuit comprises a plurality of counter modules, wherein the counter modules take the input front target signal as a starting signal and take the rear target signal as a termination signal, count is carried out by processing the counter modules in parallel, the time of a fragment passing interval is calculated, and the time data and the target coordinate data are stored in a memory.
Alternatively, the controller may employ, for example, an FPGA and its peripheral circuits. Those skilled in the art will readily appreciate that the method of using an FPGA to implement the above time data calculation and target coordinate data storage is within the routine skill of the art.
According to the utility model discloses an embodiment, the memory adopts two port RAM, and its input passes through the input data bus and is connected with timing digital circuit, and the output passes through the output data bus and is connected with communication module, display module.
Optionally, the memory is a FRAM chip of the SPI interface.
The communication module communicates with the upper computer, so that the test data are sent to the upper computer, and the upper computer performs related data processing. The communication module can be an RS485 module, an Ethernet communication module and the like.
The display module is used for displaying the test data on the display screen.
When the array speed measuring target is tested, the array target frames are arranged, the output interfaces of the front target frame and the rear target frame are in butt joint with the front input interface and the rear input interface of the device, the device is powered on, relevant working parameters are set, the device waits for a test, and data storage is carried out.
After the test is finished, the array speed measuring target test data storage device is recovered, and the data stored in the data storage circuit is sent to the upper computer through the communication module by utilizing the communication interface. The upper computer, such as a PC computer, uses existing data processing software to complete the processing and analysis of the test data.
The utility model discloses a plurality of signal input interfaces adopt the area of a plurality of targets of star type structure to intercept information, then handle through signal conditioning circuit and timing digital circuit, can make the time precision of measuring the fragmentation through appointed interval reach 10 ns.
Meanwhile, for a multi-channel speed measuring target, signal conditioning, data processing and data storage of each channel can be synchronously processed, and further multi-channel fragment speed and fly-away angle parameter measurement is achieved.
The above embodiments are only used to illustrate the technical solution of the present invention and not to limit it; although the present invention has been described in detail with reference to preferred embodiments, it should be understood by those skilled in the art that: the invention can be modified or equivalent substituted for some technical features; without departing from the spirit of the present invention, it should be understood that the scope of the claims is intended to cover all such modifications and variations.
Claims (8)
1. A test data storage device for an array speed measurement target comprises a plurality of signal input interfaces, a signal conditioning circuit, a controller and a data memory; the system is characterized in that the plurality of signal input interfaces comprise a front target signal input interface and a rear target signal input interface; the input end of the signal conditioning circuit is connected with the output end of each signal input interface, and the output end of the signal conditioning circuit is connected with an I/O port of the controller, and the signal conditioning circuit comprises a filter circuit and a shaping circuit; the controller comprises a timing digital circuit, the input end of the timing digital circuit is connected with the I/O port, and the output end of the timing digital circuit is connected with the memory through an input data bus; wherein the clocked digital circuit includes a plurality of counter modules.
2. The array tachotarget test data storage device of claim 1, wherein the signal conditioning circuit comprises an operational amplifier U1 and a comparator U2 connected in series.
3. The array tacho target test data storage device of claim 2, wherein the non-inverting input of the operational amplifier U1 is connected to the signal input interface through series connected resistors R1, R3 and to ground through capacitor C6; the inverting input end is grounded through a resistor R2 and is connected with the output end of the operational amplifier U1 through a resistor R4; the resistor R1 and the resistor R3 are connected with the output end of the operational amplifier U1 through a capacitor C7; the output terminal of the operational amplifier U1 is connected to the negative input terminal of the comparator U2 through a resistor R5.
4. The array tachometer target test data storage device of claim 2, wherein the positive input of the comparator U2 is connected to the parameter value input through a resistor R7 and to the output of the comparator U2 through a resistor R6 and a diode D1 connected in series.
5. The array tachometer target test data storage device of any of claims 2 to 4, wherein the signal conditioning circuit further comprises a high speed optical coupler conversion circuit connected to the output of the comparator U2.
6. The array tacho target test data storage device of any one of claims 2 to 4, wherein the operational amplifier U1 is an OP07 integrated circuit; the comparator U2 is an LM339 integrated circuit.
7. The array tacho target test data storage device of claim 1, wherein the controller comprises an FPGA and its peripheral circuitry; the memory adopts an FRAM chip of an SPI interface.
8. The array tacho target test data storage device of claim 1, wherein the memory is a dual port RAM, the input port of the RAM is connected to the timing digital circuit via an input data bus, and the output port of the RAM is connected to the communication module and the display module via an output data bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020495431.0U CN212340075U (en) | 2020-04-08 | 2020-04-08 | Array speed measuring target test data storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020495431.0U CN212340075U (en) | 2020-04-08 | 2020-04-08 | Array speed measuring target test data storage device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212340075U true CN212340075U (en) | 2021-01-12 |
Family
ID=74070214
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020495431.0U Active CN212340075U (en) | 2020-04-08 | 2020-04-08 | Array speed measuring target test data storage device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN212340075U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114739242A (en) * | 2022-03-29 | 2022-07-12 | 北京理工大学 | Submillimeter-level heavy metal particle group front edge speed testing system and method |
-
2020
- 2020-04-08 CN CN202020495431.0U patent/CN212340075U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114739242A (en) * | 2022-03-29 | 2022-07-12 | 北京理工大学 | Submillimeter-level heavy metal particle group front edge speed testing system and method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105911562B (en) | A kind of three-dimensional scanning type many reference amounts laser radar system for environmental monitoring | |
| CN102636270B (en) | Optical measurement instrument and method for atmospheric coherent length | |
| CN212340075U (en) | Array speed measuring target test data storage device | |
| CN1945356B (en) | Multifunctional atmospheric laser radar | |
| CN104296607B (en) | Laser fuze closes feedback test device and test system and method for testing | |
| CN109100159A (en) | A kind of vehicle data monitoring and performance analysis system | |
| CN110231311B (en) | Portable optical fiber turbidity detection device | |
| CN105157834A (en) | Spectral data acquisition system based on CCD and photomultiplier | |
| CN207181570U (en) | A kind of electronic surveying integrated system | |
| CN210270582U (en) | Multichannel synchronous trigger device, tunnel area array camera and tunnel system of patrolling and examining | |
| CN204964452U (en) | Wireless crack depth automated inspection appearance | |
| CN206930588U (en) | A kind of photosynthetical system II delayed fluorescence instrument with multiple pulses arousal function | |
| CN102620861A (en) | Scaling temperature measuring device in distributed optical fiber temperature sensor | |
| CN110989557B (en) | Long-range guided missile test system based on PXI bus | |
| CN202734971U (en) | Optical measuring instrument for measuring atmospheric coherent length | |
| CN109029537A (en) | A kind of pointer-type sync bit indicator test device and its application method | |
| CN201000326Y (en) | Device for measuring laser beam | |
| CN102590151A (en) | Wireless transmission mode-based laser measuring method of smoke transmission rate | |
| CN107991649A (en) | Visible ray indoor positioning device | |
| CN107064679A (en) | New Electric Quality Monitoring and monitoring method | |
| CN107202993A (en) | The big visual field laser three-dimensional imaging system of cascade acousto-optic sampled based on Full wave shape | |
| CN203178032U (en) | Auxiliary reading device of measurement-based force measurement device | |
| CN208537140U (en) | A kind of measurement far-field spot device | |
| CN205537728U (en) | Optical sensor testing device for fire explosion | |
| CN105222893A (en) | A kind of spectrum data gathering system based on high-voltage adjusting circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |