CN212322144U - Chip power supply power-on time sequence control circuit - Google Patents
Chip power supply power-on time sequence control circuit Download PDFInfo
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- CN212322144U CN212322144U CN202021132741.2U CN202021132741U CN212322144U CN 212322144 U CN212322144 U CN 212322144U CN 202021132741 U CN202021132741 U CN 202021132741U CN 212322144 U CN212322144 U CN 212322144U
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Abstract
The utility model discloses a chip power supply power-on time sequence control circuit, include: the power supply comprises a preceding stage power supply converter, an intermediate stage signal conditioning circuit and a rear stage power supply converter, wherein the output end of the preceding stage power supply converter is connected with the input end of the intermediate stage signal conditioning circuit, and the output end of the intermediate stage signal conditioning circuit is connected with the input end of the rear stage power supply converter. The utility model discloses in, through preceding stage power converter and back stage power converter's setting, preceding stage power converter and back stage power converter that contain in the circuit do not appoint certain special model or form, only require the converter possess level control enable control function can, the commonality is strong, circuit structure is simple, the logic is clear, easily adjust and satisfy various behavior according to the demand of difference, the circuit uses the component to be few, realized with low costs, the reliability is high, the effect of easy overall arrangement.
Description
Technical Field
The utility model relates to the field of electronic technology, especially, relate to a chip power supply goes up electric sequential control circuit.
Background
Many power supply chips have requirements on power supply sequences among power rails, the consequence of not following a specified power supply sequence is usually overlarge starting surge current and even irreparable damage to the chips, so reliable power supply is very important for a multi-power system.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a: in order to solve the above problems, a power-on timing control circuit for a chip power supply is provided.
In order to achieve the above purpose, the utility model adopts the following technical scheme:
a power-on sequence control circuit of a chip power supply comprises: the power supply comprises a preceding-stage power supply converter, an intermediate-stage signal conditioning circuit and a rear-stage power supply converter, wherein the output end of the preceding-stage power supply converter is connected with the input end of the intermediate-stage signal conditioning circuit, and the output end of the intermediate-stage signal conditioning circuit is connected with the input end of the rear-stage power supply converter;
the front-stage power supply converter is used for supplying power to a power supply rail needing to be electrified in advance, and the output voltage is used as an input signal of the intermediate-stage signal conditioning circuit;
the intermediate stage signal conditioning circuit is used for matching the level between an input signal and an output signal and inserting necessary transmission delay time between the input signal and the output signal;
and the rear-stage power converter is used for receiving the enabling signal output by the intermediate-stage signal conditioning circuit, and sequentially powering on and supplying power to other power rails according to the enabling signal delay time sequence.
As a further description of the above technical solution:
the front-stage power converter, the rear-stage power converter and the rear-stage power converter are a group of circuit units, a plurality of groups are arranged, and the circuit units of each group are connected in a nested manner and are of a tree-nested structure.
As a further description of the above technical solution:
the former stage power converter and the latter stage power converter form comprise a DC/DC switching regulator and an LDO linear regulator.
As a further description of the above technical solution:
the preceding stage power converter and the following stage power converter have enable control input terminals.
As a further description of the above technical solution:
the intermediate-level signal conditioning circuit comprises an input voltage stabilizing diode D1, current limiting and voltage dividing resistors R1 and R2, a pull-down triode Q1, a pull-up resistor R4, a current limiting resistor R3, a pull-up triode Q2, voltage dividing and current limiting resistors R5 and R6, a delay capacitor C1 and a discharge diode D2.
To sum up, owing to adopted above-mentioned technical scheme, the beneficial effects of the utility model are that:
the utility model discloses in, through preceding stage power converter and back stage power converter's setting, preceding stage power converter and back stage power converter that contain in the circuit do not appoint certain special model or form, only require the converter possess level control enable control function can, the commonality is strong, circuit structure is simple, the logic is clear, easily adjust and satisfy various behavior according to the demand of difference, the circuit uses the component to be few, realized with low costs, the reliability is high, the effect of easy overall arrangement.
Drawings
Fig. 1 is a schematic diagram illustrating a structure of a power-on timing control circuit of a chip power supply according to an embodiment of the present invention;
fig. 2 shows a schematic structural diagram of a power-on timing control circuit frame on a chip power supply according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.
Referring to fig. 1-2, the present invention provides a technical solution: a power-on sequence control circuit of a chip power supply comprises: the output end of the front-stage power converter is connected with the input end of the middle-stage signal conditioning circuit, and the output end of the middle-stage signal conditioning circuit is connected with the input end of the rear-stage power converter;
the front-stage power supply converter is used for supplying power to a power supply rail needing to be electrified in advance and taking the output voltage as an input signal of the intermediate-stage signal conditioning circuit;
the intermediate stage signal conditioning circuit is used for matching the level between the input signal and the output signal and inserting necessary transmission delay time between the input signal and the output signal;
the rear-stage power converter is used for receiving the enabling signal output by the intermediate-stage signal conditioning circuit, and sequentially powering on and supplying power to other power rails according to the enabling signal delay time sequence.
Specifically, as shown in fig. 1, the preceding-stage power converter, the subsequent-stage power converter, and the subsequent-stage power converter are a group of circuit units, which are collectively provided with a plurality of groups, the circuit units of each group are connected in a nested manner and have a tree-nested structure, each circuit unit is regarded as a subsequent-stage power converter of a child node, and is also regarded as a preceding-stage power converter of a parent node in a subsequent circuit unit, the connection sequence of each group of circuit units is not limited to a certain fixed mode, and the power-on sequence of the power rails and the number of the power rails are variable.
Specifically, as shown in fig. 1, the preceding power converter and the following power converter include a DC/DC switching regulator and an LDO linear regulator, and the preceding power converter and the following power converter have an enable control signal input for receiving an enable signal from the signal conditioning circuit and controlling the start and stop of the converter, and include but are not limited to DC/DC switching regulator and LDO linear regulator, so as to enhance the versatility of the preceding power converter and the following power converter in the circuit.
Specifically, as shown in fig. 1, the preceding-stage power converter and the subsequent-stage power converter have enable control input terminals, so that the preceding-stage power converter and the subsequent-stage power converter generate corresponding enable signal threshold voltages.
Specifically, as shown in fig. 1, the intermediate-stage signal conditioning circuit includes an input zener diode D1, current-limiting and voltage-dividing resistors R1 and R2, a pull-down transistor Q1, a pull-up resistor R4, a current-limiting resistor R3, a pull-up transistor Q2, voltage-dividing and current-limiting resistors R5 and R6, a delay capacitor C1, and a discharge diode D2, and the input threshold voltage can be changed by using zener diodes D1 with different zener values and adjusting the values of the voltage-dividing resistors R3 and R4, so as to adapt to the pre-stage power converters with different output voltages; the values of the delay capacitor C1 and the divider resistors R5 and R6 are adjusted, so that the time length of the signal transmission delay of the intermediate-stage signal conditioning circuit can be adjusted, and the enable input threshold voltage of the rear-stage power converter can be matched; the intermediate-stage signal conditioning circuit is realized by connecting discrete components without using a special integrated control chip, and delays and controls the work of the rear-stage power converter and realizes the signal matching circuit of the sequential power-on operation between power rails by receiving the output voltage of the front-stage power converter, and the signal conditioning circuit comprises but is not limited to the functions of signal threshold level triggering, signal delay triggering, signal level matching, resetting and the like. The conditioning circuit is built completely by using discrete basic elements and does not use any integrated circuit chip.
The working principle is as follows: when the power supply is used, the front-stage power supply converter provides power supply for a power supply channel needing to be powered preferentially, when the output voltage of the front-stage power supply meets the target requirement, the output voltage passes through a voltage stabilizing tube D1 and current limiting resistors R1 and R2 for voltage division to reach the emitter junction conducting voltage of an NPN triode Q1, the collector electrode and the emitter electrode of the triode Q1 are conducted, the voltage Uce between the collector electrode and the emitter electrode is reduced due to the reduction of the Uce of the triode Q1 and the voltage division is carried out through voltage dividing resistors R3 and R4, so that the emitter junction of the PNP triode Q2 reaches the conducting voltage, the emitter electrode and the collector electrode of the triode Q2 are conducted, the voltage Uec between the emitter electrode and the collector electrode of the triode Q2 is reduced, the divided voltages on the voltage dividing resistors R5 and R6 are increased, a delay capacitor C1 is charged through voltage dividing resistors R5 and R6, and an RC circuit time constant consisting of the voltage dividing resistors R, after a certain charging time, the voltage at two ends of the delay capacitor reaches the enabling signal threshold voltage of the rear-stage power converter, the rear-stage power converter is started to supply power to a power channel needing subsequent power-on, and by analogy, a plurality of groups of front-stage power converters and rear-stage power converters which are mutually cascaded in a tree shape work in succession, namely, the sequential power-on operation of a plurality of groups of power supplies can be realized, when the whole system is powered off, the delay capacitor C1 can discharge in time through the discharge diode D2, and the power supply system can be triggered in a normal sequence when powered on again.
The above, only be the concrete implementation of the preferred embodiment of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art is in the technical scope of the present invention, according to the technical solution of the present invention and the utility model, the concept of which is equivalent to replace or change, should be covered within the protection scope of the present invention.
Claims (5)
1. A power-on sequence control circuit of a chip power supply is characterized by comprising: the power supply comprises a preceding-stage power supply converter, an intermediate-stage signal conditioning circuit and a rear-stage power supply converter, wherein the output end of the preceding-stage power supply converter is connected with the input end of the intermediate-stage signal conditioning circuit, and the output end of the intermediate-stage signal conditioning circuit is connected with the input end of the rear-stage power supply converter;
the front-stage power supply converter is used for supplying power to a power supply rail needing to be electrified in advance, and the output voltage is used as an input signal of the intermediate-stage signal conditioning circuit;
the intermediate stage signal conditioning circuit is used for matching the level between an input signal and an output signal and inserting necessary transmission delay time between the input signal and the output signal;
and the rear-stage power converter is used for receiving the enabling signal output by the intermediate-stage signal conditioning circuit, and sequentially powering on and supplying power to other power rails according to the enabling signal delay time sequence.
2. The chip power supply power-on timing sequence control circuit according to claim 1, wherein the front stage power converter, the rear stage power converter and the rear stage power converter are a group of circuit units, and a plurality of groups are arranged, and the circuit units of each group are connected in a nested manner and are in a tree-nested structure.
3. A power-on timing control circuit for chip power supply as claimed in claim 1, wherein said pre-stage power converter and post-stage power converter form includes DC/DC switching regulator and LDO linear regulator.
4. The power-on timing control circuit of claim 1, wherein the pre-stage power converter and the post-stage power converter have enable control inputs.
5. The power-on timing control circuit of claim 1, wherein the intermediate-stage signal conditioning circuit comprises an input zener diode D1, current-limiting and voltage-dividing resistors R1 and R2, a pull-down transistor Q1, a pull-up resistor R4, a current-limiting resistor R3, a pull-up transistor Q2, voltage-dividing and current-limiting resistors R5 and R6, a delay capacitor C1, and a discharge diode D2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021132741.2U CN212322144U (en) | 2020-06-18 | 2020-06-18 | Chip power supply power-on time sequence control circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021132741.2U CN212322144U (en) | 2020-06-18 | 2020-06-18 | Chip power supply power-on time sequence control circuit |
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| CN212322144U true CN212322144U (en) | 2021-01-08 |
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| CN202021132741.2U Active CN212322144U (en) | 2020-06-18 | 2020-06-18 | Chip power supply power-on time sequence control circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023284122A1 (en) * | 2021-07-16 | 2023-01-19 | 长鑫存储技术有限公司 | Power source circuit and memory |
| CN115801042A (en) * | 2023-02-09 | 2023-03-14 | 西安集成电路设计专业孵化器有限公司 | Electric digital data transmission chip circuit |
| US11862228B2 (en) | 2021-07-16 | 2024-01-02 | Changxin Memory Technologies Inc. | Power supply circuit and memory |
-
2020
- 2020-06-18 CN CN202021132741.2U patent/CN212322144U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023284122A1 (en) * | 2021-07-16 | 2023-01-19 | 长鑫存储技术有限公司 | Power source circuit and memory |
| US11862228B2 (en) | 2021-07-16 | 2024-01-02 | Changxin Memory Technologies Inc. | Power supply circuit and memory |
| CN115801042A (en) * | 2023-02-09 | 2023-03-14 | 西安集成电路设计专业孵化器有限公司 | Electric digital data transmission chip circuit |
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