CN212302243U - Electronic load control circuit with current drawing and filling capacity - Google Patents
Electronic load control circuit with current drawing and filling capacity Download PDFInfo
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- CN212302243U CN212302243U CN202020820718.6U CN202020820718U CN212302243U CN 212302243 U CN212302243 U CN 212302243U CN 202020820718 U CN202020820718 U CN 202020820718U CN 212302243 U CN212302243 U CN 212302243U
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Abstract
The utility model discloses an possess simultaneously and draw electronic load control circuit who irritates current ability, include the voltage-controlled follower circuit and draw and irritate return circuit switching circuit, including test end, power end, earthing terminal, a plurality of switches and by the series circuit that sampling resistor, switch tube constitute, draw irritate the circuit and establish the test end through the switching of a plurality of switches and draw current loop to the earthing terminal, or the power end is through the current loop that irritates of series circuit to test end; the voltage-controlled follower circuit comprises a voltage control end, a sampling input end and an output end; the voltage control end is used for inputting external control voltage; the sampling input end is used for collecting voltage on the sampling resistor; the output end is connected with the control electrode of the switch tube and used for controlling the conduction current of the switch tube to enable the voltage on the sampling resistor to be equal to the external control voltage.
Description
Technical Field
The utility model belongs to the technical field of the circuit, specifically relate to an electronic load control circuit for realizing drawing and irritating current capability.
Background
The conventional electronic load control mode can only realize current-pulling capacity, the control principle is shown in fig. 1, and the control method is as follows: the DAC sets the output voltage Vset to turn on the switching tube Q1, samples the resistance value Rs, and sets the pull-up current I to Vset/Rs when Vrs is equal to Vset, thereby realizing the extraction of I current to the PIN port.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing an possess simultaneously and draw electronic load control circuit who irritates the current capability, realize possessing to draw/irritate the current capability to the PIN mouth to simplify the test.
In order to achieve the above object, the present invention provides an electronic load control circuit with current pumping and recharging capability, which comprises a voltage-controlled follower circuit and a pumping and recharging loop switching circuit,
the pull-irrigation loop switching circuit comprises a testing end, a power end, a grounding end, a plurality of switches and a series circuit consisting of a sampling resistor and a switching tube, wherein the pull-irrigation loop switching circuit establishes a pull-current loop from the testing end to the grounding end through the series circuit through the switching of the plurality of switches, or establishes an irrigation current loop from the power end to the testing end through the series circuit;
the voltage-controlled follower circuit comprises a voltage control end, a sampling input end and an output end;
the voltage control end is used for inputting external control voltage;
the sampling input end is used for collecting voltage on the sampling resistor;
the output end is connected with the control electrode of the switch tube and used for controlling the conduction current of the switch tube to enable the voltage on the sampling resistor to be equal to the external control voltage.
Further, the plurality of switches includes a first switch, a second switch, a third switch, and a fourth switch;
the first switch is connected between the test end and the series circuit in series;
the second switch is connected in series between the series circuit and the ground terminal;
the third switch is connected between the power supply end and the series circuit in series;
the fourth switch is connected between the series circuit and the test end in series;
the first switch is linked with the second switch, the third switch and the fourth switch are linked, and the first switch/the second switch and the third switch/the fourth switch are mutually exclusive, so that a pull current loop is formed from the test end to the grounding end through the first switch, the series circuit and the second switch; or a current-filling loop is formed, wherein the power supply end of the current-filling loop is connected to the test end through the third switch, the series circuit and the fourth switch.
Furthermore, the first switch, the second switch, the third switch and the fourth switch are switch units of a double-pole double-throw switch, and the double-pole double-throw switch meets three state relation requirements of first switch/second switch linkage, third switch/fourth switch linkage and mutual exclusion of the first switch/second switch and the third switch/fourth switch.
Further, the first switch, the second switch, the third switch and the fourth switch are switch units of an optical coupler.
Further, the voltage-controlled follower circuit also comprises a first operational amplifier and a second operational amplifier,
the positive input end of the first operational amplifier is connected with the voltage control end, the output end of the first operational amplifier is connected with the control electrode of the switching tube, and the negative input end of the first operational amplifier is connected with the output end of the second operational amplifier;
and the sampling resistor is connected between the positive input end and the negative input end of the second operational amplifier in a bridging manner.
Further, the switching tube is an MOS tube.
Further, the MOS transistor is IPS060N 03L.
The utility model has the advantages that:
the utility model discloses an electronic load control circuit can realize drawing/irritating the current capability test simultaneously to the chip pin, if carry out the bearing capacity test to MCU's GPIO interface (general input/output interface), the circuit is simple and practical, to the bearing capacity test of optimizing GPIO, has positive meaning.
Drawings
FIG. 1 is an electrical schematic of a conventional electronic load control circuit;
fig. 2 is an electrical schematic diagram of the electronic load control circuit of the present invention.
Detailed Description
To further illustrate the embodiments, the present invention provides the accompanying drawings. The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the embodiments. With these references, one of ordinary skill in the art will appreciate other possible embodiments and advantages of the present invention. Elements in the figures are not drawn to scale and like reference numerals are generally used to indicate like elements.
The present invention will now be further described with reference to the accompanying drawings and detailed description.
The utility model discloses an electronic load control circuit with possess simultaneously and draw and irritate electric current ability, as shown in figure 2. The circuit is provided with a voltage control end DAC and a test end PIN, wherein the voltage control end DAC is used for being connected with the DAC output of the control unit, and the test end PIN is connected with a PIN to be tested, such as a GPIO interface of an MCU.
In the present embodiment, the electronic load control circuit includes an operational amplifier U1, an operational amplifier U2, a MOS transistor Q1, a sampling resistor Rs, and switches K1, K2, K3, and K4.
The sampling resistor Rs, the operational amplifier U1 and the operational amplifier U2 form a voltage-controlled follower circuit; the pull-fill loop switching circuit is formed by a test end, a power end, a grounding end, a plurality of switches K1, K2, K3 and K4 and a series circuit formed by sampling resistors and switching tubes, and the pull-fill loop switching circuit establishes a pull-current loop from the test end to the grounding end through the series circuit or a fill-current loop from the power end to the test end through the series circuit by switching of the switches K1, K2, K3 and K4.
The voltage-controlled follower circuit comprises a voltage control end, a sampling input end and an output end.
The positive input end of the operational amplifier U1 is a voltage control end of the voltage-controlled follower circuit, is connected with a DAC (digital-to-analog converter) of the voltage control end, and is used for inputting an external control voltage; the negative input end of the operational amplifier U1 is connected with the input end of the operational amplifier U2, the output end of the operational amplifier U1 is connected with the grid electrode of the MOS tube Q1, and the operational amplifier U1 is used for controlling the conduction current of the MOS tube Q1 to enable the voltage on the sampling resistor Rs to be equal to the external control voltage;
two input ends of the operational amplifier U2 are sampling input ends of the voltage-controlled follower circuit; the positive input end and the negative output end of the operational amplifier U2 are connected across a sampling resistor Rs, and the positive input end is connected with the source electrode of the MOS tube Q1.
A switch K1 (first switch) is connected in series between the test terminal PIN and the series circuit;
a switch K2 (second switch) is connected in series between the series circuit and the ground;
a switch K3 (third switch) is connected in series between the Power supply terminal Power and the series circuit;
a switch K4 (fourth switch) is connected in series between the series circuit and the test terminal PIN;
specifically, the negative input end of the operational amplifier U2 is connected with one ends of the switches K2 and K4, the other end of the switch K2 is grounded, and the other end of the switch K4 is connected with the PIN of the test end;
the drain electrode of the MOS tube Q1 is connected with the switches K1 and K3, the other end of the switch K1 is connected with the test end PIN, and the other end of the switch K3 is connected with the power supply, wherein the switches K1/K2 are linked, the switches K3/K4 are linked, and simultaneously the switches K1/K2 and the switches K3/K4 are mutually exclusive.
The control principle is as follows:
the sampling resistor Rs, the operational amplifier U1 and the operational amplifier U2 form a voltage-controlled follower circuit. The control unit sets the output voltage Vset of the pin DAC, samples the voltage Vs at two ends of the sampling resistor Rs by using a differential operational amplifier U2, and controls the load current I to be Vset/Rs according to the Vset to be Vs.
The switches K1, K2, K3 and K4 are used for switching the pull-sink loop to establish a pull-sink current loop from the test terminal PIN to the ground terminal through the sampling resistor Rs or establish a sink current loop from the power terminal PIN to the test terminal PIN through the sampling resistor Rs.
When the current is pulled, the switch K1/K2 is set to be closed through the control unit, and the switch K3/K4 is opened; when current is filled, the control unit sets the switch K3/K4 to be closed and the switch K1/K2 to be opened.
In this embodiment, the switches K1, K2, K3, and K4 may be switch units of a double-pole double-throw switch or a two-way and two-way switching relay, and are controlled manually or by a control unit to achieve three state relationship requirements of switch K1/K2 linkage, switch K3/K4 linkage, and switch K1/K2 and switch K3/K4 mutual exclusion.
In this embodiment, the switches K1, K2, K3, and K4 may also be electrically controlled switches directly controlled by the control unit, such as optocouplers, and the linkage and mutual exclusion between the switches are realized through internal logic of the control unit, or realized through other conventional technical means, which will not be further described herein.
In this embodiment, the switching transistor Q1 is a general MOS transistor, such as an N-channel MOS transistor of IPS060N 03L.
In this embodiment, the first operational amplifier and the second operational amplifier may be amplifier units of a common operational amplifier, such as LM 358. And an operational amplifier is adopted for voltage following, so that the circuit is simple and the control precision is high.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (7)
1. The utility model provides an electronic load control circuit that possesses draw and irritate current ability simultaneously which characterized in that: comprises a voltage-controlled follower circuit and a pull-filling loop switching circuit,
the pull-irrigation loop switching circuit comprises a testing end, a power end, a grounding end, a plurality of switches and a series circuit consisting of a sampling resistor and a switching tube, wherein the pull-irrigation loop switching circuit establishes a pull-current loop from the testing end to the grounding end through the series circuit through the switching of the plurality of switches, or establishes an irrigation current loop from the power end to the testing end through the series circuit;
the voltage-controlled follower circuit comprises a voltage control end, a sampling input end and an output end;
the voltage control end is used for inputting external control voltage;
the sampling input end is used for collecting voltage on the sampling resistor;
the output end is connected with the control electrode of the switch tube and used for controlling the conduction current of the switch tube to enable the voltage on the sampling resistor to be equal to the external control voltage.
2. The electrical load control circuit with current sinking capability as claimed in claim 1, wherein: the plurality of switches includes a first switch, a second switch, a third switch, and a fourth switch;
the first switch is connected between the test end and the series circuit in series;
the second switch is connected in series between the series circuit and the ground terminal;
the third switch is connected between the power supply end and the series circuit in series;
the fourth switch is connected between the series circuit and the test end in series;
the first switch is linked with the second switch, the third switch and the fourth switch are linked, and the first switch/the second switch and the third switch/the fourth switch are mutually exclusive, so that a pull current loop is formed from the test end to the grounding end through the first switch, the series circuit and the second switch; or a current-filling loop is formed, wherein the power supply end of the current-filling loop is connected to the test end through the third switch, the series circuit and the fourth switch.
3. The electronic load control circuit with current sinking and pulling capability of claim 2, further comprising: the first switch, the second switch, the third switch and the fourth switch are switch units of a double-pole double-throw switch, and the double-pole double-throw switch meets three state relation requirements of first switch/second switch linkage, third switch/fourth switch linkage and mutual exclusion of the first switch/second switch and the third switch/fourth switch.
4. The electronic load control circuit with current sinking and pulling capability of claim 2, further comprising: the first switch, the second switch, the third switch and the fourth switch are switch units of an optical coupler.
5. The electrical load control circuit with current sinking capability as claimed in claim 1, wherein: the voltage controlled follower circuit further comprises a first operational amplifier and a second operational amplifier,
the positive input end of the first operational amplifier is connected with the voltage control end, the output end of the first operational amplifier is connected with the control electrode of the switching tube, and the negative input end of the first operational amplifier is connected with the output end of the second operational amplifier;
and the sampling resistor is connected between the positive input end and the negative input end of the second operational amplifier in a bridging manner.
6. The electrical load control circuit with current sinking capability as claimed in claim 1, wherein: the switch tube is an MOS tube.
7. The electrical load control circuit with current sinking capability as claimed in claim 6, wherein: the MOS tube is IPS060N 03L.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020820718.6U CN212302243U (en) | 2020-05-18 | 2020-05-18 | Electronic load control circuit with current drawing and filling capacity |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020820718.6U CN212302243U (en) | 2020-05-18 | 2020-05-18 | Electronic load control circuit with current drawing and filling capacity |
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| Publication Number | Publication Date |
|---|---|
| CN212302243U true CN212302243U (en) | 2021-01-05 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202020820718.6U Active CN212302243U (en) | 2020-05-18 | 2020-05-18 | Electronic load control circuit with current drawing and filling capacity |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115102541A (en) * | 2022-08-26 | 2022-09-23 | 广东大普通信技术股份有限公司 | Fast convergence frequency trimming circuit and method |
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2020
- 2020-05-18 CN CN202020820718.6U patent/CN212302243U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115102541A (en) * | 2022-08-26 | 2022-09-23 | 广东大普通信技术股份有限公司 | Fast convergence frequency trimming circuit and method |
| CN115102541B (en) * | 2022-08-26 | 2022-10-28 | 广东大普通信技术股份有限公司 | Fast convergence frequency trimming circuit and method |
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Effective date of registration: 20220411 Address after: B201, zero one square, Xi'an Software Park, 72 Keji 2nd Road, high tech Zone, Xi'an City, Shaanxi Province, 710000 Patentee after: Tuoer Microelectronics Co.,Ltd. Address before: Unit 410, No. 1702, Gangzhong Road, Xiamen area, China (Fujian) pilot Free Trade Zone, Xiamen City, Fujian Province 361000 Patentee before: INMICRO (XIAMEN) MICROELECTRONIC TECHNOLOGY CO.,LTD. |