CN212258799U - Ultrasonic power supply circuit - Google Patents
Ultrasonic power supply circuit Download PDFInfo
- Publication number
- CN212258799U CN212258799U CN202021915265.1U CN202021915265U CN212258799U CN 212258799 U CN212258799 U CN 212258799U CN 202021915265 U CN202021915265 U CN 202021915265U CN 212258799 U CN212258799 U CN 212258799U
- Authority
- CN
- China
- Prior art keywords
- diode
- bridge
- capacitor
- input end
- vbus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Inverter Devices (AREA)
Abstract
The utility model discloses an ultrasonic power supply circuit, which comprises a preceding stage rectification circuit and a rear stage inverter circuit which are connected in series, and an ultrasonic transducer connected with the rear stage inverter circuit; the method is characterized in that: the former stage rectification circuit adopts a voltage doubling rectification circuit or a full-bridge voltage doubling rectification circuit, and the latter stage inversion circuit adopts a high-frequency inversion circuit. The utility model has higher output voltage, and the output current can be smaller under the condition of outputting the same power, thereby being beneficial to improving the efficiency; the surge and lightning stroke protection capability of the ultrasonic power supply is also improved. In addition, the SiC MOSFET and the SiC diode which are connected in parallel are adopted by the utility model to realize ultra-high switching frequency, mainly because the reverse recovery characteristic of the body diode of the SiC MOSFET is much worse than that of the SiC diode, and the voltage drop is much higher; better high frequency switching characteristics can be obtained using a SiC MOSFET and a SiC diode in parallel.
Description
Technical Field
The utility model relates to an ultrasonic power supply equipment technical field, concretely relates to ultrasonic power supply circuit.
Background
Ultrasonic equipment is widely used in various industrial situations, such as ultrasonic cleaning, ultrasonic welding, and the like. The principle is that a power supply device is used for outputting signals with specific voltage amplitude and frequency on an ultrasonic transducer to enable the ultrasonic transducer to generate periodic mechanical vibration, and energy is transmitted through the mechanical vibration to achieve required operation.
The switching frequency of the traditional ultrasonic power supply generally working is consistent with the output frequency, and because the parameters (voltage, resonant frequency and the like) of the ultrasonic transducers are different, the traditional ultrasonic power supply and the ultrasonic transducers need complicated impedance matching when being used in a matching way; therefore, the conventional ultrasonic power supply has several problems: (1) a specific ultrasonic power supply can only work together with a specific ultrasonic transducer generally; (2) after the device is put into use for a period of time, as the parameters of the transducer and the impedance matching network drift, the working conditions of the whole system can be deteriorated (such as reduced efficiency, insufficient driving voltage, too high driving voltage, etc.), which is often the main reason for system failure; (3) due to the existence of the ultrasonic power supply output matching network, a large voltage drop exists on the matching network, so that the voltage amplitude utilization rate of the system is low, and the efficiency of the whole machine is low.
SUMMERY OF THE UTILITY MODEL
In view of the above technical problems, the present technical solution provides an ultrasonic power supply circuit.
The utility model discloses a following technical scheme realizes:
an ultrasonic power supply circuit comprises a front-stage rectifying circuit, a rear-stage inverter circuit and an ultrasonic transducer connected with the rear-stage inverter circuit; the rectification circuit is connected with the inverter circuit in series; the rectifier circuit is a power frequency rectifier circuit, the power frequency rectifier circuit adopts a voltage doubling rectifier circuit or a full-bridge voltage doubling rectifier circuit, and the inverter circuit adopts a high-frequency inverter circuit.
Further, the voltage-multiplying rectifying circuit or the full-bridge voltage-multiplying rectifying circuit comprises an input end, an output end, a rectifying bridge circuit and a passive PFC, wherein the rectifying bridge circuit and the passive PFC are arranged between the input end and the output end; and the inductor of the passive PFC is arranged on the front side of the rectifying bridge arm and close to the alternating current input end, or is arranged on the rear side of the rectifying bridge arm and close to the position of the output capacitor.
Furthermore, the voltage doubling rectifying circuit comprises input ends L and N, output ends Vbus + and Vbus-, and two loops which are respectively connected with the input ends L and N and are mutually connected in parallel;
the two loops are respectively: a loop one: the diode D1, the inductor L1 and the capacitor C2 are connected with the input end L and are mutually connected in series, and the capacitor C2 is connected with the input end N; and a second loop: the diode D2, the inductor L2 and the capacitor C1 are connected with the input end L and are mutually connected in series, and the capacitor C1 is connected with the input end N;
or, the two loops are respectively: a loop one: the inductor L1, the diode D1 and the capacitor C2 are connected with the input end L and are mutually connected in series, and the capacitor C2 is connected with the input end N; and a second loop: and the inductor L2, the diode D2 and the capacitor C1 are connected with the input end L and are mutually connected in series, and the capacitor C1 is connected with the input end N.
Furthermore, the full-bridge voltage-doubling rectifying circuit comprises input ends L and N, output ends Vbus + and Vbus-, and a rectifying bridge circuit which is arranged between the input ends and the output ends and consists of four bridge arms D1, D2, D3 and D4.
Further, the rectifier bridge circuit comprises two loops which are respectively connected with the input ends L and N and are mutually connected in parallel, and two bridge arms which are grafted between the two loops;
the two loops are respectively: a third loop: the diode D1, the inductor L1 and the capacitor C2 are connected with the input end L and are mutually connected in series, and the capacitor C2 is connected with the input end N; and a loop IV: the diode D2, the inductor L2 and the capacitor C1 are connected with the input end L and are mutually connected in series, and the capacitor C1 is connected with the input end N;
two bridge arms grafted between the two loops include: a diode D3 grafted between the diode D1 and the anode of the diode D2, and a diode D4 grafted between the diode D1 and the cathode of the diode D2;
or, the two loops are respectively: a third loop: the inductor L1, the diode D1 and the capacitor C2 are connected with the input end L and are mutually connected in series, and the capacitor C2 is connected with the input end N; and a loop IV: the inductor L2, the diode D2 and the capacitor C1 are connected with the input end L and are mutually connected in series, and the capacitor C1 is connected with the input end N;
two bridge arms grafted between the two loops include: a diode D3 grafted between the diode D1 and the anode of the diode D2, and a diode D4 grafted between the diode D1 and the cathode of the diode D2.
Further, when the input voltage of the full-bridge voltage-doubling rectifying circuit is a positive half wave of the alternating current input, namely the L voltage is greater than the N voltage, the C2 is charged in two ways: the first method is as follows: l → L1 → D1 → C2 → N; the second method comprises the following steps: l → L2 → D4 → C2 → N;
when the input voltage of the full-bridge voltage-doubling rectifying circuit is negative half wave of alternating current input, namely the L voltage is less than the N voltage, C1 is charged through two modes: the third method comprises the following steps: n → C1 → D2 → L2 → L; the method is as follows: n → C1 → D3 → L1 → L; the full-bridge voltage-doubling rectification is realized in this way;
when the full-bridge voltage-multiplying rectifying circuit is in no-load, namely the output currents of the output ends Vbus + and Vbus-are zero, the output voltage, namely the voltage between the Vbus + and the Vbus-is the peak-to-peak value of the input alternating voltage minus the conduction voltages of the two bridge arms.
Furthermore, the high-speed bridge arm is formed by connecting a silicon carbide diode and a silicon carbide metal oxide semiconductor field effect transistor in parallel; the low-speed bridge arm is composed of an insulated gate bipolar transistor with a diode.
Furthermore, the high-frequency inverter circuit comprises input ends Vbus + and Vbus-, a full-bridge inverter circuit and an output end; the full-bridge inverter circuit comprises four bridge arms, wherein the four bridge arms comprise two high-speed bridge arms and two low-speed bridge arms; the output end of the full-bridge inverter circuit is connected with the ultrasonic transducer through an inductor L3, a filter circuit, a blocking capacitor and a transformer T1.
Furthermore, the working frequency of the high-speed bridge arm is more than 5 times of the output frequency, and the low-speed bridge arm works at the output frequency.
Furthermore, the high-speed bridge arm is formed by connecting a silicon carbide diode and a silicon carbide metal oxide semiconductor field effect transistor in parallel; the low-speed bridge arm is composed of an insulated gate bipolar transistor with a diode.
Furthermore, the high-frequency inverter circuit comprises input ends Vbus + and Vbus-, a high-speed bridge arm comprises silicon carbide diodes D5 and D6 which are connected with the input ends Vbus + and Vbus in series, and the silicon carbide diodes D5 and D6 are respectively connected with silicon carbide metal oxide semiconductor field effect transistors S1 and S2 in parallel; the low-speed bridge arm comprises insulated gate bipolar transistors S3 and S4 which are connected with input ends Vbus + and Vbus-in series and connected with the high-speed bridge arm in parallel; the insulated gate bipolar transistors S3 and S4 in the low-speed bridge arm are insulated gate bipolar transistors with diodes;
the insulated gate bipolar transistors S3 and S4 are driven complementarily; when the insulated gate bipolar transistor S3 is turned on, the silicon carbide metal oxide semiconductor field effect transistor S2 emits a wave; when the insulated gate bipolar transistor S4 is turned on, the silicon carbide metal oxide semiconductor field effect transistor S1 emits a wave;
when the positive half wave is output, namely the voltage at the upper end of the filter capacitor C3 is greater than that at the lower end; the insulated gate bipolar transistor S3 is always on, and the silicon carbide metal oxide semiconductor field effect transistor S2 works in a high-frequency switch state;
when the insulated gate bipolar transistor S3 is always conducted and the silicon carbide metal oxide semiconductor field effect transistor S2 is conducted, the input voltage of high-frequency inversion, namely the voltage between Vbus + and Vbus-, is excited to the inductor L3, and the current of the inductor L3 is increased; the current flow direction is as follows: vbus + → S2 → L3 → C3 → S3 → Vbus-; when the silicon carbide mosfet S2 is turned off, the current in the inductor L3 freewheels through the silicon carbide diode D5, and is reduced by the voltage across the filter capacitor C3, and the current flows as follows: vbus- → D5 → L3 → C3 → S3 → Vbus-;
when the negative half wave is output, namely the voltage at the upper end of the filter capacitor C3 is less than that at the lower end; the insulated gate bipolar transistor S4 is always on, and the silicon carbide metal oxide semiconductor field effect transistor S1 works in a high-frequency switch state;
when the insulated gate bipolar transistor S4 is always conducted and the silicon carbide metal oxide semiconductor field effect transistor S1 is conducted, the input voltage of high-frequency inversion, namely the voltage between Vbus + and Vbus-, is excited to the inductor L3, and the current of the inductor L3 is increased; the current flow direction is as follows: vbus + → S4 → C3 → L3 → S1 → Vbus-;
when the silicon carbide mosfet S1 is turned off, the current in the inductor L3 freewheels through the silicon carbide diode D5, and is reduced by the voltage across the filter capacitor C3, and the current flows as follows: vbus- → D5 → L3 → C3 → Vbus-.
Furthermore, the high-speed bridge arm consists of a silicon carbide metal oxide semiconductor field effect transistor; the low-speed bridge arm is composed of an insulated gate bipolar transistor without a body diode and a silicon carbide diode connected in parallel.
Furthermore, the high-frequency inverter circuit comprises input ends Vbus + and Vbus-, the high-speed bridge arm comprises two silicon carbide metal oxide semiconductor field effect transistors S2 and S4 which are respectively connected with the input end Vbus + in series, the low-speed bridge arm comprises two silicon carbide diodes D5 and D6 which are respectively connected with the input end Vbus-in series, and the two silicon carbide diodes are respectively connected with insulated gate bipolar transistors S1 and S3 in parallel; the silicon carbide metal oxide semiconductor field effect transistor S2 is connected with the insulated gate bipolar transistor S1 in series, and the silicon carbide metal oxide semiconductor field effect transistor S4 is connected with the insulated gate bipolar transistor S3 in series;
insulated gate bipolar transistors S1 and S3 in the low-speed bridge arm are insulated gate bipolar transistors without body diodes;
an inductor L3 is connected at the midpoint of S1 and S2, the other end of the inductor L3 is connected with a filter circuit C3, and the other end of the filter circuit C3 is connected at the midpoint of S3 and S4; the filter circuit C3 is connected with the blocking capacitor C4 and the transformer T1, and the transformer T1 is connected with the ultrasonic transducer;
the insulated gate bipolar transistors S1 and S3 are in complementary driving; when the insulated gate bipolar transistor S3 is turned on, the silicon carbide metal oxide semiconductor field effect transistor S2 emits a wave; when the insulated gate bipolar transistor S1 is turned on, the silicon carbide metal oxide semiconductor field effect transistor S4 emits a wave;
when the positive half wave is output, namely the voltage at the upper end of the filter capacitor C3 is greater than that at the lower end; the insulated gate bipolar transistor S3 is always on, and the silicon carbide metal oxide semiconductor field effect transistor S2 works in a high-frequency switch state;
when the insulated gate bipolar transistor S3 is always conducted and the silicon carbide metal oxide semiconductor field effect transistor S2 is conducted, the input voltage of high-frequency inversion, namely the voltage between Vbus + and Vbus-, is excited to the inductor L3, and the current of the inductor L3 is increased; the current flow direction is as follows: vbus + → S2 → L3 → C3 → S3 → Vbus-; when the silicon carbide mosfet S2 is turned off, the current in the inductor L3 freewheels through the silicon carbide diode D5, and is reduced by the voltage across the filter capacitor C3, and the current flows as follows: vbus- → D5 → L3 → C3 → S3 → Vbus-;
when the negative half wave is output, namely the voltage at the upper end of the filter capacitor C3 is less than that at the lower end; the insulated gate bipolar transistor S1 is always on, and the silicon carbide metal oxide semiconductor field effect transistor S4 works in a high-frequency switch state;
when the insulated gate bipolar transistor S1 is always conducted and the silicon carbide metal oxide semiconductor field effect transistor S4 is conducted, the input voltage of high-frequency inversion, namely the voltage between Vbus + and Vbus-, is reversely excited to the inductor L3, and the current of the inductor L3 is increased; the current flow direction is as follows: vbus + → S4 → C3 → L3 → S1 → Vbus-; when the silicon carbide mosfet S4 is turned off, the current in the inductor L3 freewheels through the silicon carbide diode D5, and is reduced by the voltage across the filter capacitor C3, and the current flows as follows: vbus- → D5 → L3 → C3 → Vbus-.
Furthermore, the high-frequency inverter circuit comprises input ends Vbus + and Vbus-, and the high-speed bridge arm comprises two silicon carbide metal oxide semiconductor field effect transistors S1 and S3 which are respectively connected with the input end Vbus-in series; the low-speed bridge arm comprises two silicon carbide diodes D5 and D6 which are respectively connected with the input end Vbus + in series, and the two silicon carbide diodes are respectively connected with insulated gate bipolar transistors S2 and S4 in parallel; the silicon carbide metal oxide semiconductor field effect transistor S1 is connected with the insulated gate bipolar transistor S2 in series, and the silicon carbide metal oxide semiconductor field effect transistor S3 is connected with the insulated gate bipolar transistor S4 in series;
insulated gate bipolar transistors S2 and S4 in the low-speed bridge arm are insulated gate bipolar transistors without body diodes;
an inductor L3 is connected at the midpoint of S1 and S2, the other end of the inductor L3 is connected with a filter circuit C3, and the other end of the filter circuit C3 is connected at the midpoint of S3 and S4; the filter circuit C3 is connected with the blocking capacitor C4 and the transformer T1, and the transformer T1 is connected with the ultrasonic transducer;
the insulated gate bipolar transistors S2 and S4 are in complementary driving; when the insulated gate bipolar transistor S2 is turned on, the silicon carbide metal oxide semiconductor field effect transistor S3 emits a wave; when the insulated gate bipolar transistor S4 is turned on, the silicon carbide metal oxide semiconductor field effect transistor S1 emits a wave;
when the positive half wave is output, namely the voltage at the upper end of the filter capacitor C3 is greater than that at the lower end; the insulated gate bipolar transistor S2 is always on, and the silicon carbide metal oxide semiconductor field effect transistor S3 works in a high-frequency switch state;
when the insulated gate bipolar transistor S2 is always conducted and the silicon carbide metal oxide semiconductor field effect transistor S3 is conducted, the input voltage of high-frequency inversion, namely the voltage between Vbus + and Vbus-, is excited to the inductor L3, and the current of the inductor L3 is increased; the current flow direction is as follows: vbus + → S2 → L3 → C3 → S3 → Vbus-; when the silicon carbide mosfet S3 is turned off, the current in the inductor L3 freewheels through the silicon carbide diode D6, and is reduced by the voltage across the filter capacitor C3, and the current flows as follows: vbus + → S2 → L3 → C3 → D6 → Vbus +;
when the negative half wave is output, namely the voltage at the upper end of the filter capacitor C3 is less than that at the lower end; the insulated gate bipolar transistor S4 is always on, and the silicon carbide metal oxide semiconductor field effect transistor S1 works in a high-frequency switch state;
when the insulated gate bipolar transistor S4 is always conducted and the silicon carbide metal oxide semiconductor field effect transistor S1 is conducted, the input voltage of high-frequency inversion, namely the voltage between Vbus + and Vbus-, is reversely excited to the inductor L3, and the current of the inductor L3 is increased; the current flow direction is as follows: vbus + → S4 → C3 → L3 → S1 → Vbus-; when the silicon carbide mosfet S1 is turned off, the current in the inductor L3 freewheels through the silicon carbide diode D5, and is reduced by the voltage across the filter capacitor C3, and the current flows as follows: vbus + → S4 → C3 → L3 → D5 → Vbus +.
Furthermore, the current of the inductor L3 adopts a CCM-current continuous mode, a DCM-current discontinuous mode or a BCM-current boundary mode.
Advantageous effects
The utility model provides an ultrasonic power supply circuit compares with prior art, and it has following beneficial effect:
(1) in the voltage-multiplying rectifying circuit adopted by the utility model, any input half-wave only passes through one bridge arm when charging the output capacitors (C1 and C2), and compared with the traditional mode that the full-bridge rectification needs to pass through two bridge arms, the efficiency is higher; and the output voltage of the voltage doubling rectifying circuit is higher, and the output current can be smaller under the condition of outputting the same power, thereby being beneficial to improving the efficiency.
(2) The utility model adopts the full-bridge voltage-doubling rectification composed of D1, D2, D3 and D4, which has higher efficiency and is more beneficial to realizing miniaturization; in the two bridge arms of the full-bridge inversion, two bridge arms are high-speed bridge arms formed by SiC devices, and the other bridge arm is low-speed bridge arms formed by traditional IGBT devices; the peak current of the full-bridge voltage-doubling rectifier inductor and the peak current of the bridge arms (D1, D2, D3 and D4) are reduced to half of the full bridge, the current stress is greatly reduced, and the efficiency is improved; and the inductor of the passive PFC is placed on the front side of a rectifier bridge (consisting of D1, D2, D3 and D4), so that the surge and lightning stroke protection capability of the ultrasonic power supply is greatly improved.
(3) In order to obtain a sine wave with a frequency of up to 100KHz, the switching frequency needs to be at least about 1MHz, and at such a high frequency, the control of the switching loss is very serious. The utility model adopts the SiC MOSFET and the SiC diode to realize the ultra-high switching frequency, mainly because the reverse recovery characteristic of the body diode of the SiC MOSFET is much worse than that of the SiC diode, and the voltage drop is much higher; better high frequency switching characteristics can be obtained using a SiC MOSFET and a SiC diode in parallel.
Drawings
Fig. 1 is a schematic diagram of a full-bridge voltage-doubling rectifier circuit according to embodiment 1 of the present invention.
Fig. 2 is a schematic diagram of a high-frequency inverter circuit according to embodiment 1 of the present invention.
Fig. 3 is a schematic diagram of a drive control waveform in embodiment 1 of the present invention.
Fig. 4 is a schematic diagram of a full-bridge voltage-doubling rectifier circuit according to embodiment 2 of the present invention.
Fig. 5 is a schematic diagram of a voltage-doubler rectifier circuit according to embodiment 3 of the present invention.
Fig. 6 is a schematic diagram of a voltage-doubler rectifier circuit in embodiment 4 of the present invention.
Fig. 7 is a schematic diagram of a high-frequency inverter circuit according to embodiment 5 of the present invention.
Fig. 8 is a schematic diagram of a high-frequency inverter circuit according to embodiment 6 of the present invention.
Fig. 9 is a schematic diagram of a high-frequency inverter circuit according to embodiment 7 of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. The described embodiments are only some, but not all embodiments of the invention. Under the prerequisite that does not deviate from the design concept of the utility model, the ordinary person in the art should fall into the protection scope of the utility model to the various changes and improvements that the technical scheme of the utility model made.
An ultrasonic power supply circuit comprises a front-stage rectifying circuit, a rear-stage inverter circuit and an ultrasonic transducer connected with the rear-stage inverter circuit; the rectification circuit is connected with the inverter circuit in series; the rectifier circuit is a power frequency rectifier circuit, the power frequency rectifier circuit adopts a voltage doubling rectifier circuit or a full-bridge voltage doubling rectifier circuit, and the inverter circuit adopts a high-frequency inverter circuit.
The voltage-multiplying rectifying circuit or the full-bridge voltage-multiplying rectifying circuit comprises an input end, an output end, a rectifying bridge circuit and a passive PFC, wherein the rectifying bridge circuit and the passive PFC are arranged between the input end and the output end; and the inductor of the passive PFC is arranged on the front side of the rectifying bridge arm and close to the alternating current input end, or is arranged on the rear side of the rectifying bridge arm and close to the position of the output capacitor.
The high-frequency inverter circuit comprises input ends Vbus + and Vbus-, a full-bridge inverter circuit and an output end; the full-bridge inverter circuit comprises four bridge arms, wherein the four bridge arms comprise two high-speed bridge arms and two low-speed bridge arms; the output end of the full-bridge inverter circuit is connected with the ultrasonic transducer through a filter circuit, a blocking capacitor and a transformer T1; the output signal of the full-bridge inverter circuit is filtered by an inductor L3 and a filter capacitor C3 to form a sine wave, and the sine wave is output to the ultrasonic transducer after passing through a blocking capacitor C4 and a transformer T1. The working frequency of the high-speed bridge arm is more than 5 times of the output frequency, and the low-speed bridge arm works at the output frequency.
Example 1:
an ultrasonic power supply circuit comprises a front-stage full-bridge voltage-doubling rectifying circuit and a high-frequency inverter circuit.
As shown in fig. 1, the full-bridge voltage-doubling rectifying circuit comprises input ends L and N, output ends Vbus + and Vbus-, and a rectifying bridge circuit arranged between the input ends and the output ends and composed of four bridge arms D1, D2, D3 and D4. The rectifier bridge circuit comprises two loops which are respectively connected with the input ends L and N and are mutually connected in parallel, and two bridge arms which are grafted between the two loops;
the two loops are respectively: loop 1: the diode D1, the inductor L1 and the capacitor C2 are connected with the input end L and are mutually connected in series, and the capacitor C2 is connected with the input end N; loop 2: the diode D2, the inductor L2 and the capacitor C1 are connected with the input end L and are mutually connected in series, and the capacitor C1 is connected with the input end N;
two bridge arms grafted between the two loops include: a diode D3 grafted between the diode D1 and the anode of the diode D2, and a diode D4 grafted between the diode D1 and the cathode of the diode D2.
When the input voltage of the full-bridge voltage-doubling rectifying circuit is the positive half wave of alternating current input, namely the L voltage is greater than the N voltage, C2 is charged through two modes: the first method is as follows: l → L1 → D1 → C2 → N; the second method comprises the following steps: l → L2 → D4 → C2 → N;
when the input voltage of the full-bridge voltage-doubling rectifying circuit is negative half wave of alternating current input, namely the L voltage is less than the N voltage, C1 is charged through two modes: the third method comprises the following steps: n → C1 → D2 → L2 → L; the method is as follows: n → C1 → D3 → L1 → L; the full-bridge voltage-doubling rectification is realized in this way;
when the full-bridge voltage-multiplying rectifying circuit is in no-load, namely the output currents of the output ends Vbus + and Vbus-are zero, the output voltage, namely the voltage between the Vbus + and the Vbus-is the peak-to-peak value of the input alternating voltage minus the conduction voltages of the two bridge arms.
As shown in fig. 2, the high-frequency inverter circuit comprises input terminals Vbus + and Vbus-, and the high-speed bridge arm comprises silicon carbide diodes D5 and D6 connected in series with the input terminals Vbus + and Vbus-, wherein the silicon carbide diodes D5 and D6 are respectively connected in parallel with silicon carbide metal oxide semiconductor field effect transistors S1 and S2; the low-speed bridge arm comprises insulated gate bipolar transistors S3 and S4 which are connected with input ends Vbus + and Vbus-in series and connected with the high-speed bridge arm in parallel; and the insulated gate bipolar transistors S3 and S4 in the low-speed bridge arm are insulated gate bipolar transistors with diodes.
The inductor L3 is connected to the midpoint of the high-speed bridge arm, the other end of the inductor L3 is connected with the filter circuit C3, the other end of the filter circuit C3 is connected to the midpoint of the low-speed bridge arm, the filter circuit C3 is connected with the blocking capacitor C4 and the transformer T1, and the transformer T1 is connected with the ultrasonic transducer. In the present embodiment, the current of the inductor L3 may adopt CCM (current continuous mode), DCM (current discontinuous mode) or BCM (current boundary mode).
The insulated gate bipolar transistors S3 and S4 are in complementary driving; when the insulated gate bipolar transistor S3 is turned on, the silicon carbide metal oxide semiconductor field effect transistor S2 emits a wave; when the insulated gate bipolar transistor S4 is turned on, the silicon carbide mosfet S1 emits a wave.
As shown in fig. 3, when the positive half wave is outputted, i.e., the voltage at the upper end of the filter capacitor C3 is greater than the voltage at the lower end; the insulated gate bipolar transistor S3 is always on, and the silicon carbide metal oxide semiconductor field effect transistor S2 works in a high-frequency switch state;
when the insulated gate bipolar transistor S3 is always conducted and the silicon carbide metal oxide semiconductor field effect transistor S2 is conducted, the input voltage of high-frequency inversion, namely the voltage between Vbus + and Vbus-, is excited to the inductor L3, and the current of the inductor L3 is increased; the current flow direction is as follows: vbus + → S2 → L3 → C3 → S3 → Vbus-; when the silicon carbide mosfet S2 is turned off, the current in the inductor L3 freewheels through the silicon carbide diode D5, and is reduced by the voltage across the filter capacitor C3, and the current flows as follows: vbus- → D5 → L3 → C3 → S3 → Vbus-;
when the negative half wave is output, namely the voltage at the upper end of the filter capacitor C3 is less than that at the lower end; the insulated gate bipolar transistor S4 is always on, and the silicon carbide metal oxide semiconductor field effect transistor S1 works in a high-frequency switch state;
when the insulated gate bipolar transistor S4 is always conducted and the silicon carbide metal oxide semiconductor field effect transistor S1 is conducted, the input voltage of high-frequency inversion, namely the voltage between Vbus + and Vbus-, is reversely excited to the inductor L3, and the current of the inductor L3 is increased; the current flow direction is as follows: vbus + → S4 → C3 → L3 → S1 → Vbus-; when the silicon carbide mosfet S1 is turned off, the current in the inductor L3 freewheels through the silicon carbide diode D5, and is reduced by the voltage across the filter capacitor C3, and the current flows as follows: vbus + → S4 → C3 → L3 → Vbus +.
Example 2:
as shown in fig. 4, in addition to embodiment 1, an inductor L1 and an inductor L2 in the full-bridge voltage-doubler rectifier circuit at the front stage may be provided on the rear side of the rectifier bridge circuit composed of four arms D1, D2, D3, and D4.
The two loops are respectively: loop 3: the inductor L1, the diode D1 and the capacitor C2 are connected with the input end L and are mutually connected in series, and the capacitor C2 is connected with the input end N; loop 4: the inductor L2, the diode D2 and the capacitor C1 are connected with the input end L and are mutually connected in series, and the capacitor C1 is connected with the input end N;
two bridge arms grafted between the two loops include: a diode D3 grafted between the diode D1 and the anode of the diode D2, and a diode D4 grafted between the diode D1 and the cathode of the diode D2.
When the input voltage of the full-bridge voltage-doubling rectifying circuit is the positive half wave of alternating current input, namely the L voltage is greater than the N voltage, C2 is charged through two modes: the first method is as follows: l → D1 → L1 → C2 → N; the second method comprises the following steps: l → D4 → L1 → C2 → N;
when the input voltage of the full-bridge voltage-doubling rectifying circuit is negative half wave of alternating current input, namely the L voltage is less than the N voltage, C1 is charged through two modes: the third method comprises the following steps: n → C1 → L2 → D2 → L; the method is as follows: n → C1 → L2 → D3 → L; in this way, full-bridge voltage-doubling rectification is realized.
Other structures, the positional relationship and the connection relationship between the structures, and the principle in this embodiment are the same as those in embodiment 1, and are not described in detail here.
Example 3:
as shown in fig. 5, in an ultrasonic power supply circuit, a voltage doubler rectifier circuit may be used at a previous stage in addition to embodiment 1, and although the effect of the voltage doubler rectifier circuit is not as good as that of the full-bridge voltage doubler rectifier circuits in embodiments 1 and 2, this embodiment is still an embodiment that can be implemented by this technical solution if the implementation cost is reduced.
The voltage doubling rectifying circuit comprises input ends L and N, output ends Vbus + and Vbus-, and two loops which are respectively connected with the input ends L and N and are mutually connected in parallel;
the two loops are respectively: loop 5: the diode D1, the inductor L1 and the capacitor C2 are connected with the input end L and are mutually connected in series, and the capacitor C2 is connected with the input end N; the loop 6: and the diode D2, the inductor L2 and the capacitor C1 are connected with the input end L and are mutually connected in series, and the capacitor C1 is connected with the input end N.
Other structures, the positional relationship and the connection relationship between the structures, and the principle in this embodiment are the same as those in embodiment 1, and are not described in detail here.
Example 4:
as shown in fig. 6, in addition to embodiments 1 and 5, an inductor L1 and an inductor L2 in the voltage doubler rectifier circuit may be provided behind two legs D1 and D2.
The front stage can also adopt a voltage doubling rectifying circuit which comprises input ends L and N, output ends Vbus + and Vbus-, and two loops which are respectively connected with the input ends L and N and are mutually connected in parallel;
the two loops are respectively: a loop one: the inductor L1, the diode D1 and the capacitor C2 are connected with the input end L and are mutually connected in series, and the capacitor C2 is connected with the input end N; and a second loop: and the inductor L2, the diode D2 and the capacitor C1 are connected with the input end L and are mutually connected in series, and the capacitor C1 is connected with the input end N.
Other structures, the positional relationship and the connection relationship between the structures, and the principle in this embodiment are the same as those in embodiment 1, and are not described in detail here.
Example 5:
as shown in fig. 7, in the ultrasonic power supply circuit, in addition to embodiment 1, the inductor L3 in the high-frequency inverter circuit may be disposed below the filter capacitor.
When the insulated gate bipolar transistor S3 is always turned on and the silicon carbide metal oxide semiconductor field effect transistor S2 is turned on when the positive half wave is output, the current flows as follows: vbus + → S2 → C3 → L3 → S3 → Vbus-; when the silicon carbide mosfet S2 is turned off, the current flows as follows: vbus- → D5 → C3 → L3 → S3 → Vbus-;
when the insulated gate bipolar transistor S4 is always turned on and the silicon carbide metal oxide semiconductor field effect transistor S1 is turned on when the negative half wave is output, the current flows as follows: vbus + → S4 → L3 → C3 → S1 → Vbus-;
when the silicon carbide mosfet S1 is turned off, the current flows as follows: vbus + → S4 → L3 → C3 → D6 → Vbus +.
Other structures, the positional relationship and the connection relationship between the structures, and the principle in this embodiment are the same as those in embodiment 1, and are not described in detail here.
Example 6:
an ultrasonic power supply circuit, based on embodiment 1, the high-frequency inverter circuit at the subsequent stage can also be implemented by a circuit as shown in fig. 8, although the effect of the circuit is not as good as that of the high-frequency inverter circuits in embodiments 1 and 5, if the implementation cost is reduced, the embodiment is still an implementation manner that can be implemented by the technical solution.
The high-frequency inverter circuit comprises input ends Vbus + and Vbus-, the high-speed bridge arm comprises two silicon carbide metal oxide semiconductor field effect transistors S2 and S4 which are respectively connected with the input ends Vbus + in series, the low-speed bridge arm comprises two silicon carbide diodes D5 and D6 which are respectively connected with the input ends Vbus-in series, and the two silicon carbide diodes are respectively connected with insulated gate bipolar transistors S1 and S3 in parallel. The insulated gate bipolar transistors S1 and S3 in the low-speed bridge arm are insulated gate bipolar transistors without body diodes.
An inductor L3 is connected at the midpoint of S1 and S2, the other end of the inductor L3 is connected with a filter circuit C3, and the other end of the filter circuit C3 is connected at the midpoint of S3 and S4, namely between D5 and S1; the filter circuit C3 is connected to the dc blocking capacitor C4 and the transformer T1, and the transformer T1 is connected to the ultrasonic transducer.
The insulated gate bipolar transistors S1 and S3 are in complementary driving; when the insulated gate bipolar transistor S3 is turned on, the silicon carbide metal oxide semiconductor field effect transistor S2 emits a wave; when the insulated gate bipolar transistor S1 is turned on, the silicon carbide metal oxide semiconductor field effect transistor S4 emits a wave;
when the positive half wave is output, namely the voltage at the upper end of the filter capacitor C3 is greater than that at the lower end; the insulated gate bipolar transistor S3 is always on, and the silicon carbide metal oxide semiconductor field effect transistor S2 works in a high-frequency switch state;
when the insulated gate bipolar transistor S3 is always conducted and the silicon carbide metal oxide semiconductor field effect transistor S2 is conducted, the input voltage of high-frequency inversion, namely the voltage between Vbus + and Vbus-, is excited to the inductor L3, and the current of the inductor L3 is increased; the current flow direction is as follows: vbus + → S2 → L3 → C3 → S3 → Vbus-; when the silicon carbide mosfet S2 is turned off, the current in the inductor L3 freewheels through the silicon carbide diode D5, and is reduced by the voltage across the filter capacitor C3, and the current flows as follows: vbus- → D5 → L3 → C3 → S3 → Vbus-;
when the negative half wave is output, namely the voltage at the upper end of the filter capacitor C3 is less than that at the lower end; the insulated gate bipolar transistor S1 is always on, and the silicon carbide metal oxide semiconductor field effect transistor S4 works in a high-frequency switch state;
when the insulated gate bipolar transistor S1 is always conducted and the silicon carbide metal oxide semiconductor field effect transistor S4 is conducted, the input voltage of high-frequency inversion, namely the voltage between Vbus + and Vbus-, is reversely excited to the inductor L3, and the current of the inductor L3 is increased; the current flow direction is as follows: vbus + → S4 → C3 → L3 → S1 → Vbus-; when the silicon carbide mosfet S4 is turned off, the current in the inductor L3 freewheels through the silicon carbide diode D5, and is reduced by the voltage across the filter capacitor C3, and the current flows as follows: vbus- → D5 → L3 → C3 → Vbus-.
Other structures, the positional relationship and the connection relationship between the structures, and the principle in this embodiment are the same as those in embodiment 1, and are not described in detail here.
Example 7:
as shown in fig. 9, an ultrasonic power supply circuit, based on embodiment 6, a high-frequency inverter circuit of a subsequent stage can also be implemented by the circuit shown in fig. 9.
The high-frequency inverter circuit comprises input ends Vbus + and Vbus-, and the high-speed bridge arm comprises two silicon carbide metal oxide semiconductor field effect transistors S1 and S3 which are respectively connected with the input ends Vbus-in series; the low-speed bridge arm comprises two silicon carbide diodes D5 and D6 which are respectively connected with the input end Vbus + in series, and the two silicon carbide diodes are respectively connected with insulated gate bipolar transistors S2 and S4 in parallel. The insulated gate bipolar transistors S2 and S4 in the low-speed bridge arm are insulated gate bipolar transistors without body diodes.
The insulated gate bipolar transistors S2 and S4 are in complementary driving; when the insulated gate bipolar transistor S2 is turned on, the silicon carbide metal oxide semiconductor field effect transistor S3 emits a wave; when the insulated gate bipolar transistor S4 is turned on, the silicon carbide metal oxide semiconductor field effect transistor S1 emits a wave;
when the positive half wave is output, namely the voltage at the upper end of the filter capacitor C3 is greater than that at the lower end; the insulated gate bipolar transistor S2 is always on, and the silicon carbide metal oxide semiconductor field effect transistor S3 works in a high-frequency switch state;
when the insulated gate bipolar transistor S2 is always conducted and the silicon carbide metal oxide semiconductor field effect transistor S3 is conducted, the input voltage of high-frequency inversion, namely the voltage between Vbus + and Vbus-, is excited to the inductor L3, and the current of the inductor L3 is increased; the current flow direction is as follows: vbus + → S2 → L3 → C3 → S3 → Vbus-; when the silicon carbide mosfet S3 is turned off, the current in the inductor L3 freewheels through the silicon carbide diode D6, and is reduced by the voltage across the filter capacitor C3, and the current flows as follows: vbus + → S2 → L3 → C3 → D6 → Vbus +;
when the negative half wave is output, namely the voltage at the upper end of the filter capacitor C3 is less than that at the lower end; the insulated gate bipolar transistor S4 is always on, and the silicon carbide metal oxide semiconductor field effect transistor S1 works in a high-frequency switch state;
when the insulated gate bipolar transistor S4 is always conducted and the silicon carbide metal oxide semiconductor field effect transistor S1 is conducted, the input voltage of high-frequency inversion, namely the voltage between Vbus + and Vbus-, is reversely excited to the inductor L3, and the current of the inductor L3 is increased; the current flow direction is as follows: vbus + → S4 → C3 → L3 → S1 → Vbus-; when the silicon carbide mosfet S1 is turned off, the current in the inductor L3 freewheels through the silicon carbide diode D5, and is reduced by the voltage across the filter capacitor C3, and the current flows as follows: vbus + → S4 → C3 → L3 → D5 → Vbus +.
Other structures, the positional relationship and the connection relationship between the structures, and the principle in this embodiment are the same as those in embodiment 1, and are not described in detail here.
Example 8:
as shown in fig. 7, in addition to embodiments 1, 5, 6, and 7, a dc blocking capacitor C4 may be provided on the lower left side of a transformer T1.
Other structures, the positional relationship and the connection relationship between the structures, and the principle in this embodiment are the same as those in embodiment 1, and are not described in detail here.
Claims (11)
1. An ultrasonic power supply circuit comprises a front-stage rectifying circuit, a rear-stage inverter circuit and an ultrasonic transducer connected with the rear-stage inverter circuit; the rectification circuit is connected with the inverter circuit in series; the method is characterized in that: the inverter circuit adopts a high-frequency inverter circuit.
2. An ultrasonic power supply circuit according to claim 1, wherein: the rectifying circuit is a power frequency rectifying circuit, and the power frequency rectifying circuit adopts a half-bridge voltage-multiplying rectifying circuit or a full-bridge voltage-multiplying rectifying circuit.
3. An ultrasonic power supply circuit according to claim 2, wherein: the half-bridge voltage-multiplying rectifying circuit or the full-bridge voltage-multiplying rectifying circuit comprises an input end, an output end, a rectifying bridge circuit and a passive PFC, wherein the rectifying bridge circuit and the passive PFC are arranged between the input end and the output end; and the inductor of the passive PFC is arranged on the front side of the rectifying bridge arm and close to the alternating current input end, or is arranged on the rear side of the rectifying bridge arm and close to the position of the output capacitor.
4. An ultrasonic power supply circuit according to claim 2 or 3, wherein: the half-bridge voltage-multiplying rectifying circuit comprises input ends L and N, output ends Vbus + and Vbus-, and two loops which are respectively connected with the input ends L and N and are mutually connected in parallel;
the two loops are respectively: a loop one: the diode D1, the inductor L1 and the capacitor C2 are connected with the input end L and are mutually connected in series, and the capacitor C2 is connected with the input end N; and a second loop: the diode D2, the inductor L2 and the capacitor C1 are connected with the input end L and are mutually connected in series, and the capacitor C1 is connected with the input end N;
or, the two loops are respectively: a loop one: the inductor L1, the diode D1 and the capacitor C2 are connected with the input end L and are mutually connected in series, and the capacitor C2 is connected with the input end N; and a second loop: and the inductor L2, the diode D2 and the capacitor C1 are connected with the input end L and are mutually connected in series, and the capacitor C1 is connected with the input end N.
5. An ultrasonic power supply circuit according to claim 2 or 3, wherein: the full-bridge voltage-multiplying rectifying circuit comprises input ends L and N, output ends Vbus + and Vbus-, and a rectifying bridge circuit which is arranged between the input ends and the output ends and consists of four bridge arms D1, D2, D3 and D4.
6. An ultrasonic power supply circuit according to claim 5, wherein: the rectifier bridge circuit comprises two loops which are respectively connected with the input ends L and N and are mutually connected in parallel, and two bridge arms which are grafted between the two loops;
the two loops are respectively: a third loop: the diode D1, the inductor L1 and the capacitor C2 are connected with the input end L and are mutually connected in series, and the capacitor C2 is connected with the input end N; and a loop IV: the diode D2, the inductor L2 and the capacitor C1 are connected with the input end L and are mutually connected in series, and the capacitor C1 is connected with the input end N;
two bridge arms grafted between the two loops include: a diode D3 grafted between the diode D1 and the anode of the diode D2, and a diode D4 grafted between the diode D1 and the cathode of the diode D2;
or, the two loops are respectively: a third loop: the inductor L1, the diode D1 and the capacitor C2 are connected with the input end L and are mutually connected in series, and the capacitor C2 is connected with the input end N; and a loop IV: the inductor L2, the diode D2 and the capacitor C1 are connected with the input end L and are mutually connected in series, and the capacitor C1 is connected with the input end N;
two bridge arms grafted between the two loops include: a diode D3 grafted between the diode D1 and the anode of the diode D2, and a diode D4 grafted between the diode D1 and the cathode of the diode D2.
7. An ultrasonic power supply circuit according to claim 1, wherein: the high-frequency inverter circuit comprises an input end Vbus + and a input end Vbus-, a full-bridge inverter circuit and an output end; the full-bridge inverter circuit comprises four bridge arms, wherein the four bridge arms comprise two high-speed bridge arms and two low-speed bridge arms; the output end of the full-bridge inverter circuit is connected with the ultrasonic transducer through an inductor L3, a filter circuit, a blocking capacitor and a transformer T1.
8. An ultrasonic power supply circuit according to claim 7, wherein: the working frequency of the high-speed bridge arm is more than 5 times of the output frequency, and the low-speed bridge arm works at the output frequency.
9. An ultrasonic power supply circuit according to claim 7, wherein: the high-speed bridge arm is formed by connecting a silicon carbide diode and a silicon carbide metal oxide semiconductor field effect transistor in parallel; the low-speed bridge arm is composed of an insulated gate bipolar transistor with a diode.
10. An ultrasonic power supply circuit according to claim 7, wherein: the high-speed bridge arm consists of a silicon carbide metal oxide semiconductor field effect transistor; the low-speed bridge arm is composed of an insulated gate bipolar transistor without a body diode and a silicon carbide diode connected in parallel.
11. An ultrasonic power supply circuit according to any one of claims 7 to 10, wherein: the current of the inductor L3 adopts a CCM-current continuous mode, a DCM-current discontinuous mode or a BCM-current boundary mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021915265.1U CN212258799U (en) | 2020-09-04 | 2020-09-04 | Ultrasonic power supply circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021915265.1U CN212258799U (en) | 2020-09-04 | 2020-09-04 | Ultrasonic power supply circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212258799U true CN212258799U (en) | 2020-12-29 |
Family
ID=73981875
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021915265.1U Active CN212258799U (en) | 2020-09-04 | 2020-09-04 | Ultrasonic power supply circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN212258799U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113381520A (en) * | 2021-05-31 | 2021-09-10 | 电子科技大学 | 2.4G microwave wireless single-phase AC-AC conversion circuit |
-
2020
- 2020-09-04 CN CN202021915265.1U patent/CN212258799U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113381520A (en) * | 2021-05-31 | 2021-09-10 | 电子科技大学 | 2.4G microwave wireless single-phase AC-AC conversion circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP2321894B1 (en) | Generalized ac-dc synchronous rectification techniques for single-phase systems | |
| CN107204717B (en) | Bridgeless boost CUK PFC circuit | |
| CN109639170B (en) | Auxiliary resonant pole active clamping three-level soft switching inverter circuit and modulation method | |
| CN212969479U (en) | Heric inverter circuit and Heric inverter | |
| CN104852567A (en) | Totem-pole bridgeless power factor correction circuit of soft switch | |
| CN109586602B (en) | Auxiliary resonant conversion pole T-type three-level soft switching inverter circuit and modulation method | |
| CN111669044B (en) | Cascaded staggered totem-pole bridgeless PFC circuit and control method thereof | |
| CN105811785A (en) | Transformer distribution parameter based LCC resonant type electrostatic precipitator high-frequency high-voltage power supply | |
| CN212258799U (en) | Ultrasonic power supply circuit | |
| CN111934561A (en) | Ultrasonic power supply circuit and control method thereof | |
| CN212572416U (en) | I-type three-level converter and uninterruptible power supply module | |
| CN104682762A (en) | Low-leakage-current grid-connected inverter | |
| WO2018209866A1 (en) | T-type conversion circuit and corresponding three-phase conversion circuit and conversion device | |
| CN106059312B (en) | A kind of control method of the source Z DC converter | |
| CN107072020A (en) | A kind of single-stage HID digital ballast circuits based on piezoelectric transformer | |
| CN109861573B (en) | Low switching loss power inverter | |
| CN108011538B (en) | Low-power high-frequency bidirectional AC-DC single-tube converter and wireless charging method | |
| CN113224962A (en) | Active clamping three-level inverter circuit and method | |
| CN102255546A (en) | Inverter | |
| RU61964U1 (en) | AUTONOMOUS AGREED RESONANCE INVERTER | |
| CN114142762B (en) | Bidirectional soft switching DC-AC converter | |
| CN214281237U (en) | Vehicle-mounted inverter | |
| WO2022041586A1 (en) | Power factor correction circuit, and control apparatus and control method therefor | |
| CN214851023U (en) | Motor driving circuit for power factor correction | |
| WO2022041587A1 (en) | Power factor correction circuit, and control apparatus and control method therefor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |