CN212231423U - Phase frequency detector and phase-locked loop circuit - Google Patents
Phase frequency detector and phase-locked loop circuit Download PDFInfo
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- CN212231423U CN212231423U CN202020885882.5U CN202020885882U CN212231423U CN 212231423 U CN212231423 U CN 212231423U CN 202020885882 U CN202020885882 U CN 202020885882U CN 212231423 U CN212231423 U CN 212231423U
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Abstract
The utility model provides a phase frequency detector and phase-locked loop circuit, phase frequency detector and phase-locked loop circuit include that first falling edge D flip-flop, second rise along D flip-flop, third rise along D flip-flop or logic unit and reset circuit, can carry out the phase comparison through a rising edge and the falling edge that utilizes input clock. The design can complete two phase comparisons in one clock period, which is equivalent to using 2 times of reference clock frequency, reduces the frequency division ratio and phase noise in the bandwidth of the phase-locked loop, and improves the performance of the output signal of the phase-locked loop.
Description
Technical Field
The utility model relates to an integrated circuit design field especially relates to a phase frequency detector and phase-locked loop circuit.
Background
Phase-locked loops are becoming more and more widely used as a general purpose module in integrated circuits. In a transceiver system, a phase-locked loop may be used to generate a local oscillator signal to perform modulation and demodulation of the signal. In analog circuits, a pll may be used to generate a high precision clock as an input to an analog-to-digital Converter (ADC).
The phase-locked loop system has various structures, and the charge pump-based analog phase-locked loop system is a phase-locked loop structure which is widely applied at present, and the structural principle of the phase-locked loop system is specifically shown in fig. 1 and comprises a phase frequency detector, a charge pump, a filter, a voltage-controlled oscillator and a programmable N-frequency divider. According to the difference of the 1/N value-taking modes of the frequency divider, the frequency synthesis phase-locked loop mainly has two forms: an integer-division phase-locked loop and a fractional-division phase-locked loop. When N is an integer, the N is an integer frequency division phase-locked loop; and when N is a decimal number, the fractional-N phase-locked loop is adopted.
However, the fractional-n pll circuit in the prior art has high phase noise and poor performance of output signals.
SUMMERY OF THE UTILITY MODEL
The utility model provides a phase frequency detector, a serial communication port, include: the circuit comprises a first falling edge D trigger, a second rising edge D trigger, a third rising edge D trigger, an OR logic unit and a reset circuit; a data input end of the first falling edge D trigger is coupled to a high level, a clock signal input end is coupled to a reference clock signal, a reset end is coupled to an output end of the reset circuit, and an output end is coupled to an input end of the OR logic unit; a data input end of the second rising edge D trigger is coupled to a high level, a clock signal input end is coupled to a reference clock signal, a reset end is coupled to an output end of the reset circuit, and an output end is coupled to an input end of the OR logic unit; a data input end of the third rising edge D trigger is coupled to a high level, a clock signal input end is coupled to a feedback clock signal, a reset end is coupled to an output end of the reset circuit, and an output end is coupled to the reset circuit input end and the charge pump respectively; and the output end of the OR logic unit is respectively coupled with the input end of the reset circuit and the charge pump.
Optionally, the or logic unit includes an or gate circuit; the input end of the or gate circuit is respectively coupled to the output end of the first falling edge D trigger and the output end of the second rising edge D trigger, and the output end of the or gate circuit is coupled with the charge pump.
Optionally, the reset circuit is an and circuit; a first input end of the and circuit is coupled to an output end of the or logic unit, a second input end of the and circuit is coupled to an output end of the third rising edge D flip-flop, and output ends of the and circuit and the third rising edge D flip-flop are coupled to a reset end of the first falling edge D flip-flop, a reset end of the second rising edge D flip-flop, and a reset end of the third rising edge D flip-flop, respectively.
Optionally, the phase frequency detector further includes a duty ratio correction circuit, and the reference clock signal is corrected by the duty ratio correction circuit and then respectively coupled to the clock signal input ends of the first falling edge D flip-flop and the second rising edge D flip-flop.
Optionally, the phase frequency detector further includes an inverting unit; the output end of the OR logic unit is coupled to the charge pump after passing through the inverting unit.
Optionally, the inverting unit includes a not gate circuit, an input terminal of the not gate circuit is coupled to an output terminal of the or logic unit, and an output terminal of the not gate circuit is coupled to the charge pump.
The utility model also provides a phase-locked loop circuit, including any one above-mentioned phase frequency detector.
Compared with the prior art, the technical scheme of the utility model has following advantage:
the utility model discloses an utilize the rising edge and the falling edge of input clock to carry out the phase comparison. The design can complete two phase comparisons in one clock period, which is equivalent to using 2 times of reference clock frequency, reduces the frequency division ratio and phase noise in the bandwidth of the phase-locked loop, and improves the performance of the output signal of the phase-locked loop.
Drawings
FIG. 1 is a schematic diagram of a phase-locked loop architecture;
fig. 2 is a schematic diagram of a connection structure of a phase frequency detector and a charge pump in a conventional fractional-n pll circuit;
fig. 3 is a schematic structural diagram of a phase frequency detector in an embodiment of the present invention;
fig. 4 is a schematic diagram of a connection structure of a phase frequency detector and a charge pump in a first phase-locked loop circuit according to an embodiment of the present invention;
fig. 5 is a waveform of a phase frequency detector using a pull-up/pull-down current charge pump according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a connection structure between the phase frequency detector and the charge pump in the third phase-locked loop circuit according to an embodiment of the present invention
Fig. 7 is a schematic diagram of a connection structure between a phase frequency detector and a charge pump in a phase-locked loop circuit according to a third embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 is a schematic diagram of a connection structure of a phase frequency detector and a charge pump in a conventional fractional-n pll circuit. As shown in fig. 2, the frequency of the conventional fractional pll circuit has a certain bandwidth, and the main contributors of the phase noise in the final output bandwidth are the reference clock, the phase frequency detector, the charge pump and other modules. The phase noise output by the phase-locked loop comes from the phase noise of these modules multiplied by the division ratio. When the circuit is designed, the performance is improved mainly by adjusting the size of MOS devices such as a switch. Besides optimizing the performance of each module and reducing the phase noise, the frequency division ratio can also be reduced by increasing the frequency of the input reference clock. High frequency reference clocks are costly and the system design itself limits the reference clock frequency that can be used. Conventional phase-locked loop designs utilize only the rising or falling edge of the input clock for phase comparison. Therefore, the problems of high phase noise and poor output signal performance are to be solved.
Fig. 3 is a schematic structural diagram of a phase frequency detector in an embodiment of the present invention. Wherein:
the phase frequency detector 100 includes: a first falling edge D flip-flop DFF1, a second rising edge D flip-flop DFF2, a third rising edge D flip-flop DFF3, or a logic cell 101 and a reset circuit 102.
The data input terminal D of the first falling edge D flip-flop DFF1 is coupled to the high level Vdd, the clock signal input terminal CK is coupled to the reference clock signal Fref, the reset terminal RS is coupled to the output terminal a of the reset circuit AND, AND the output terminal Q is coupled to the input terminal of the or logic unit 101.
The data input terminal D of the second rising edge D flip-flop DFF2 is coupled to the high level Vdd, the clock signal input terminal CK is coupled to the reference clock signal Fref, the reset terminal RS is coupled to the output terminal a of the reset circuit 102, and the output terminal Q is coupled to the input terminal of the or logic unit 101.
The data input end D of the third rising edge D flip-flop DFF3 is coupled to the high level Vdd, the clock signal input end CK is coupled to the feedback clock signal Fdiv, the reset end RS is coupled to the output end a of the reset circuit 102, and the DOWN signal output by the output end Q is coupled to the input end of the reset circuit 102 and the charge pump, respectively.
The UP signal output by the output B of the or logic unit 101 is coupled to the input of the reset circuit 102 and the charge pump, respectively.
Specifically, in an embodiment of the present invention, the OR logic unit 101 includes an OR gate circuit OR; the inputs of the OR gate OR are coupled to the output of the first falling edge D flip-flop DFF1 and the output of the second rising edge D flip-flop DFF2, respectively, and the UP signal output from the output B of the OR gate OR is coupled to the charge pump 200.
Specifically, in an embodiment of the present invention, the reset circuit 102 is an AND circuit AND; a first input terminal a1 of the AND circuit AND is coupled to the output terminal B of the or logic unit 101, a second input terminal a2 is coupled to the output terminal Q of the third rising edge D flip-flop DFF3, AND an output terminal a is coupled to the reset terminal RS of the first falling edge D flip-flop DFF1, the reset terminal RS of the second rising edge D flip-flop DFF2, AND the reset terminal RS of the third rising edge D flip-flop DFF3, respectively.
Fig. 4 is a schematic diagram of a connection structure of the phase frequency detector and the charge pump in the phase-locked loop circuit according to an embodiment of the present invention. In this example, the charge pump 200 is a pull-up/pull-down current charge pump. The charge pump 200 includes a first current source C201, a second current source C202, a first control switch S201, and a second control switch S202.
A first terminal of the first current source C201 is coupled to a second terminal of the first control switch S201, a first terminal of the first control switch S201 is coupled to a power supply (Vdd), a second terminal of the first current source C201 is coupled to a first terminal of the second current source C202, a second terminal of the second current source C202 is coupled to a first terminal of the second control switch S202, and a second terminal of the second control switch S202 is coupled to Ground (GND).
A control terminal of the first control switch S201 is coupled to an UP signal of the phase frequency detector, and a control terminal of the second control switch S202 is coupled to a DN signal of the phase frequency detector; a second terminal of the first current source C201 is connected to a first terminal of the second current source C202, and is coupled to an output terminal of the charge pump 200, and an output terminal of the charge pump 200 is coupled to a loop filter.
In an embodiment of the present invention, the first current source C201 is a PMOS transistor; the second current source is an NMOS transistor. Specifically, the source S of the PMOS transistor is connected to the first control switch S201, the drain D of the PMOS transistor is connected to the drain D of the NMOS transistor and coupled to the output terminal of the charge pump 200, and the source S of the NMOS transistor is coupled to the first terminal of the second control switch S202.
In the embodiment of the present invention, since the phase of the feedback signal Fdiv is ahead of the reference clock signal Fref when the phase-locked loop is locked in the present design, since the first falling edge D flip-flop DFF1 is a falling edge flip-flop and the second rising edge D flip-flop DFF2 is a rising edge flip-flop, when the reference clock signal Fref is a rising edge signal, the second rising edge D flip-flop DFF2 is triggered, that is, the state change of the output Q of the second rising edge D flip-flop DFF2 occurs at the rising edge of the reference clock signal Fref, and the logic value thereof is determined by the data signal D. When Fref reaches a rising edge, the output end Q of the second rising edge D flip-flop DFF2 is triggered to change from low to high, and passes through the OR gate OR, the output signal UP of the phase frequency detector 100 changes from low to high, and the first control switch S201 of the charge pump 200 is closed. When the feedback signal Fdiv is a rising signal, the third rising edge D flip-flop DFF3 is triggered, the output Q of the third rising edge D flip-flop DFF3 is triggered to change from low to high, the second control switch S202 of the charge pump 200 is closed, and at this time, the charge pump 200 starts to discharge.
Meanwhile, the input terminals of the reset circuit 102 simultaneously go high, and the first falling edge D flip-flop DFF1, the second rising edge D flip-flop DFF2, and the third rising edge D flip-flop DFF3 are simultaneously reset. The output ends of the first falling edge D flip-flop DFF1, the second rising edge D flip-flop DFF2 and the third rising edge D flip-flop DFF3 are all at a low level, and when the output end B of the OR gate OR passes through the OR gate OR, the output UP signal of the phase frequency detector 100 changes from a high level to a low level, the first control switch S201 is turned on, and the charge pump 200 stops discharging. Similarly, the DOWN signal also goes from high to low, the second control switch S202 is turned on, and the charge pump 200 stops discharging. When the charge pump 200 is in the discharge stop state, the leakage current charges the loop filter, the output voltage of the loop filter increases, and the frequency of the vco accordingly increases. This is also why the phase of the feedback signal Fdiv leads the reference clock signal Fref when the phase-locked loop is locked.
With reference to fig. 4, when the reference clock signal Fref is a falling edge signal, the first falling edge D flip-flop DFF1 is triggered to trigger the output Q of the first falling edge D flip-flop DFF1 to change from low to high, after passing through the OR gate OR, the output signal UP of the phase frequency detector 100 changes from low to high, and the first control switch S201 of the charge pump 200 is closed. When the feedback signal Fdiv is a rising signal, the third rising edge D flip-flop DFF3 is triggered, the output Q of the third rising edge D flip-flop DFF3 is triggered to change from low to high, the second control switch S202 of the charge pump 200 is closed, and at this time, the charge pump 200 starts to discharge.
As described above, the input terminals of the reset circuit 102 simultaneously go high, and the first falling edge D flip-flop DFF1, the second rising edge D flip-flop DFF2, and the third rising edge D flip-flop DFF3 are simultaneously reset. And will not be described in detail below.
It can be known from this embodiment that, two phase comparisons are completed in one clock cycle, which is equivalent to using 2 times of the reference clock frequency, and the frequency dividing ratio is reduced, thereby reducing the phase noise in the bandwidth of the phase-locked loop and improving the performance of the output signal of the phase-locked loop. Referring to fig. 5, a phase frequency detector waveform using pull-up/pull-down current charge pumps is disclosed for an embodiment of the present invention.
Referring to fig. 6, fig. 6 is a schematic diagram of a connection structure of a phase frequency detector and a charge pump in a phase-locked loop circuit according to another embodiment of the present invention. In the embodiment of the present invention, the phase frequency detector 100 further includes a phase inverting unit 303; the output B of the or logic unit 101 is coupled to the charge pump 300 through the inverting unit 303. Specifically, the inverting unit 303 includes a not gate circuit, an input terminal of the not gate circuit is coupled to the output terminal B of the or logic unit 101, and an output terminal of the not gate circuit is coupled to the charge pump 300.
Referring to fig. 7, fig. 7 is a schematic diagram of a connection structure of a phase frequency detector and a charge pump in a phase-locked loop circuit according to a third embodiment of the present invention. In the embodiment of the present invention, the phase frequency detector 100 further includes a duty ratio correction circuit 400, and the reference clock signal Fref passes through the correction of the duty ratio correction circuit 400 and then is coupled to the first falling edge D flip-flop DFF1 and the second rising edge D flip-flop DFF2 respectively.
Since the present design uses the rising and falling edges of the input reference clock, the duty cycle requirement for the input clock is 50%. This requirement is particularly important in fractional frequency locked loops using bias current charge pumps. A 50% deviation in duty cycle may affect the linearity of the phase frequency detector and the resulting non-linear effects may degrade the phase noise performance in the phase locked loop band. In most application scenarios, the duty cycle of the reference clock can meet the requirement. In a scene that the duty ratio of a few input clocks is not 50%, a duty ratio correction circuit can be introduced to adjust the duty ratio of the input clocks to 50%. The duty cycle is corrected to conventional circuit, and any one of the designs that satisfies the requirements can be applied to the utility model discloses in.
To sum up, the utility model provides an among the technical scheme, utilize the rising edge and the falling edge of input clock to carry out the phase comparison. The design can complete two phase comparisons in one clock period, which is equivalent to using 2 times of reference clock frequency, reduces the frequency division ratio and phase noise in the bandwidth of the phase-locked loop, and improves the performance of the output signal of the phase-locked loop.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present invention, and the scope of the present invention is defined by the appended claims.
Claims (7)
1. A phase frequency detector, comprising: the circuit comprises a first falling edge D trigger, a second rising edge D trigger, a third rising edge D trigger, an OR logic unit and a reset circuit;
a data input end of the first falling edge D trigger is coupled to a high level, a clock signal input end is coupled to a reference clock signal, a reset end is coupled to an output end of the reset circuit, and an output end is coupled to an input end of the OR logic unit;
a data input end of the second rising edge D trigger is coupled to a high level, a clock signal input end is coupled to a reference clock signal, a reset end is coupled to an output end of the reset circuit, and an output end is coupled to an input end of the OR logic unit;
a data input end of the third rising edge D trigger is coupled to a high level, a clock signal input end is coupled to a feedback clock signal, a reset end is coupled to an output end of the reset circuit, and an output end is coupled to the reset circuit input end and the charge pump respectively;
and the output end of the OR logic unit is respectively coupled with the input end of the reset circuit and the charge pump.
2. A phase frequency detector as claimed in claim 1, wherein said or logic unit comprises an or gate circuit; the input end of the or gate circuit is respectively coupled to the output end of the first falling edge D trigger and the output end of the second rising edge D trigger, and the output end of the or gate circuit is coupled with the charge pump.
3. A phase frequency detector as claimed in claim 1 wherein said reset circuit is an and gate; a first input end of the and circuit is coupled to an output end of the or logic unit, a second input end of the and circuit is coupled to an output end of the third rising edge D flip-flop, and output ends of the and circuit and the third rising edge D flip-flop are coupled to a reset end of the first falling edge D flip-flop, a reset end of the second rising edge D flip-flop, and a reset end of the third rising edge D flip-flop, respectively.
4. The phase frequency detector as claimed in claim 1, further comprising a duty cycle correction circuit, wherein the reference clock signal is corrected by the duty cycle correction circuit and then respectively coupled to the clock signal input terminals of the first falling edge D flip-flop and the second rising edge D flip-flop.
5. A phase frequency detector as claimed in claim 1, wherein said phase frequency detector further comprises an inverting unit; the output end of the OR logic unit is coupled to the charge pump after passing through the inverting unit.
6. The phase frequency detector as claimed in claim 5, wherein said inverting unit comprises a not gate circuit having an input coupled to an output of said or logic unit and an output coupled to said charge pump.
7. A phase locked loop circuit comprising the phase frequency detector of claims 1, 2, 3, 4 or 5.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202020885882.5U CN212231423U (en) | 2020-05-25 | 2020-05-25 | Phase frequency detector and phase-locked loop circuit |
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| CN202020885882.5U CN212231423U (en) | 2020-05-25 | 2020-05-25 | Phase frequency detector and phase-locked loop circuit |
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| CN212231423U true CN212231423U (en) | 2020-12-25 |
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| CN202020885882.5U Active CN212231423U (en) | 2020-05-25 | 2020-05-25 | Phase frequency detector and phase-locked loop circuit |
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