CN113676177A - Phase frequency detector, charge pump and phase-locked loop circuit - Google Patents
Phase frequency detector, charge pump and phase-locked loop circuit Download PDFInfo
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- CN113676177A CN113676177A CN202010410164.7A CN202010410164A CN113676177A CN 113676177 A CN113676177 A CN 113676177A CN 202010410164 A CN202010410164 A CN 202010410164A CN 113676177 A CN113676177 A CN 113676177A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
Abstract
In the technical scheme provided by the invention, the phase frequency detector does not comprise a delay unit for eliminating dead zones, so that the circuit structure is simplified, meanwhile, the charge pump only needs unidirectional current in work, the design requirement on a current source is low, the problem of matching of pull-up current and pull-down current is avoided, the design is simple and reliable, the linearity is high, and the phase-locked loop is very suitable for using fractional frequency dividers.
Description
Technical Field
The invention relates to the field of integrated circuit design, in particular to a phase frequency detector, a charge pump and a phase-locked loop circuit.
Background
Phase-locked loops are becoming more and more widely used as a general purpose module in integrated circuits. In a transceiver system, a phase-locked loop may be used to generate a local oscillator signal to perform modulation and demodulation of the signal. In analog circuits, a phase-locked loop may be used to generate a high-precision clock as an input to an analog-to-digital Converter (ADC).
The phase-locked loop system has various structures, and the charge pump-based analog phase-locked loop system is a phase-locked loop structure which is widely applied at present, and the structural principle of the phase-locked loop system is specifically shown in fig. 1 and comprises a phase frequency detector, a charge pump, a filter, a voltage-controlled oscillator and a programmable N-frequency divider. According to the difference of the 1/N value-taking modes of the frequency divider, the frequency synthesis phase-locked loop mainly has two forms: an integer-division phase-locked loop and a fractional-division phase-locked loop. When N is an integer, the N is an integer frequency division phase-locked loop; and when N is a decimal number, the fractional-N phase-locked loop is adopted.
However, the fractional-n pll circuit in the prior art has the problems of low linearity and complex structure.
Disclosure of Invention
The invention provides a phase frequency detector, which is characterized by comprising: the circuit comprises a first rising edge D trigger, a second rising edge D trigger, an inverting unit and a reset circuit; a data input end of the first rising edge D trigger is coupled to a high level, a clock signal input end is coupled to a reference clock signal, a reset end is coupled to an output end of the reset circuit, an output end of the first rising edge D trigger is coupled to an input end of the inverting unit, and an output end of the inverting unit is coupled to the charge pump; the data input end of the second rising edge D trigger is coupled to a high level, the clock signal input end is coupled to a feedback clock signal, the reset end is coupled to the output end of the reset circuit, and the output end is coupled to the charge pump.
Optionally, the inverting unit includes a not gate circuit; the input end of the NOT gate circuit is coupled to the output end of the first rising edge D trigger, and the output end of the NOT gate circuit is coupled to the charge pump.
Optionally, the reset circuit is an and circuit; the first input end of the and circuit is coupled with the output end of the first rising edge D trigger, the second input end of the and circuit is coupled with the output end of the second rising edge D trigger, and the output ends of the and circuit are respectively coupled with the reset end of the first rising edge D trigger and the reset end of the second rising edge D trigger.
The present invention also provides a charge pump, comprising: first current source, second current source, first control switch and second control switch, wherein: a first terminal of the first current source is coupled to a power supply, a second terminal of the first current source is coupled to a first terminal of the second current source, a second terminal of the second current source is coupled to a first terminal of the first control switch, a second terminal of the first control switch is coupled to a first terminal of the second control switch, and a second terminal of the second control switch is grounded; the control end of the first control switch is coupled with an UP signal of the phase frequency detector, and the control end of the second control switch is coupled with a DN signal of the phase frequency detector; the second terminal of the first current source is connected to the first terminal of the second current source and coupled to the output terminal of the charge pump.
Optionally, the first current source is a PMOS transistor.
Optionally, the second current source is an NMOS transistor.
Optionally, the charge pump further includes a third control switch and a fourth control switch, a first end of the third control switch and a first end of the fourth control switch are both coupled to the power supply, and a second end of the third control switch and a second end of the fourth control switch are connected and coupled to the first end of the first control switch; the control end of the third control switch is coupled with an UP signal of the phase frequency detector, and the control end of the fourth control switch is coupled with a DN signal of the phase frequency detector.
The invention also provides a phase-locked loop circuit which is characterized by comprising the phase frequency detector and the charge pump.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the technical scheme, the phase frequency detector does not comprise a delay unit for eliminating dead zones, the circuit structure is simplified, meanwhile, the charge pump only needs unidirectional current in work, the design requirement on a current source is low, the problem of matching of pull-up current and pull-down current is avoided, the design is simple and reliable, the linearity is high, and the phase-locked loop is very suitable for using a fractional frequency divider.
Drawings
FIG. 1 is a schematic diagram of a phase-locked loop architecture;
fig. 2 is a schematic diagram of a connection structure of a phase frequency detector and a charge pump in a conventional fractional-n pll circuit;
fig. 3 is a schematic structural diagram of a phase frequency detector in an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a charge pump in an embodiment of the present invention;
fig. 5 is a schematic diagram of a connection structure of a phase frequency detector and a charge pump in a phase-locked loop circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of waveforms at various points of a PLL locking circuit according to an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 is a schematic diagram of a connection structure of a phase frequency detector and a charge pump in a conventional fractional-n pll circuit. As shown in fig. 2, the conventional fractional pll circuit has a dead zone problem due to delay and response speed of the circuit, and a delay circuit is required to eliminate the dead zone. In addition, unlike integer-division charge pump phase-locked loops, the charge pump in fractional-division charge pump phase-locked loops has a greater impact on the performance of the phase-locked loop. Since the fractional division phase-locked loop is characterized in that the division ratio is randomly changed and the average value is the fractional division ratio, the performance requirement of the charge pump is high. In particular, the better the linearity of the charge pump, the higher the phase noise performance. When the circuit is designed, the linearity is improved mainly by adjusting the sizes of MOS devices such as a switch and the like. In addition, the charge pump uses both the pull-up current Iup and the pull-down current Idown, and in order to make the phase noise performance higher, the matching accuracy of the pull-up current Iup and the pull-down current Idown is improved in circuit design.
Therefore, the phase frequency detector and the charge pump in the traditional fractional-N phase-locked loop circuit have the problems of high design difficulty, complex structure, low linearity and the like.
Fig. 3 is a schematic structural diagram of a phase frequency detector according to an embodiment of the present invention. Wherein:
the phase frequency detector 100 includes a first rising edge D flip-flop DFF1, a second rising edge D flip-flop DFF2, an inverting unit 101, and a reset circuit 102.
The data input terminal (terminal D) of the first rising edge D flip-flop DFF1 is coupled to a high level (Vdd), the clock signal input terminal (terminal CK) is coupled to a reference clock signal Fref, the reset terminal (terminal RS) is coupled to the output terminal of the reset circuit 102, the output terminal (terminal Q) is coupled to the input terminal of the inverting unit 101, and the output terminal (terminal UP) of the inverting unit 101 is coupled to the charge pump.
The data input terminal (terminal D) of the second rising edge D flip-flop DFF2 is coupled to the high level (Vdd), the clock signal input terminal (terminal CK) is coupled to the feedback clock signal Fdiv, the reset terminal (terminal RS) is coupled to the output terminal of the reset circuit 102, and the output terminal (terminal Q) is coupled to the charge pump.
In an embodiment of the present invention, the inverting unit 102 includes a not gate circuit 1011; the not gate 1011 has an input coupled to the output (Q) of the first rising edge D flip-flop DFF1, and an output (UP) coupled to the charge pump.
In an embodiment of the present invention, the reset circuit 102 is an and circuit 1021; a first input terminal of the and circuit 1021 is coupled to the output terminal (Q terminal) of the first rising edge D flip-flop DFF1, a second input terminal thereof is coupled to the output terminal (Q terminal) of the second rising edge D flip-flop DFF2, and output terminals thereof are coupled to the reset terminal (RS terminal) of the first rising edge D flip-flop DFF1 and the reset terminal (RS terminal) of the second rising edge D flip-flop DFF2, respectively.
Fig. 4 shows a schematic structural diagram of a charge pump in an embodiment of the present invention, where:
the charge pump 200 includes: a first current source C201, a second current source C202, a first control switch S201 and a second control switch S202.
A first terminal of the first current source C201 is coupled to a power supply (Vdd), a second terminal is coupled to a first terminal of the second current source C202, a second terminal of the second current source C202 is coupled to a first terminal of the first control switch S201, a second terminal of the first control switch S201 is coupled to a first terminal of the second control switch S202, and a second terminal of the second control switch S202 is coupled to Ground (GND); a control terminal of the first control switch S201 is coupled to an UP signal of the phase frequency detector, and a control terminal of the second control switch S202 is coupled to a DN signal of the phase frequency detector; the second terminal of the first current source C201 is connected to the first terminal of the second current source C202, and is coupled to the output terminal (Vc terminal) of the charge pump 200.
In an embodiment of the present invention, the first current source C201 is a PMOS transistor; the second current source is an NMOS transistor. Specifically, the source S of the PMOS transistor is connected to a power supply (Vdd), the drain D of the PMOS transistor is connected to the drain D of the NMOS transistor and coupled to the output terminal (Vc terminal) of the charge pump 200, and the source S of the NMOS transistor is coupled to the first terminal of the first control switch S201.
With continued reference to fig. 4, in an embodiment of the present invention, the charge pump 200 further includes a third control switch S203 and a fourth control switch S204, a first terminal of the third control switch S203 and a first terminal of the fourth control switch S204 are both coupled to a power supply (Vdd), a second terminal of the third control switch S203 and a second terminal of the fourth control switch S204 are connected and coupled to the first terminal of the first control switch S201; a control terminal of the third control switch S203 is coupled to an UP signal of the phase frequency detector, and a control terminal of the fourth control switch S204 is coupled to a DN signal of the phase frequency detector. Since the UP signal controls the first control switch S201 and the third control switch S203, and the DN signal controls the second control switch S202 and the fourth control switch S204, when the switches are closed, the charge pump 200 starts to discharge, and the third control switch S203 and the fourth control switch S204 increase the discharge response rate of the charge pump 200.
Fig. 5 is a schematic diagram illustrating a connection structure of a phase frequency detector and a charge pump in a phase-locked loop circuit according to an embodiment of the present invention. The phase locked loop circuit shown in fig. 5 may include a phase frequency detector 100 and a charge pump 200. The phase frequency detector and the charge pump are configured as the phase frequency detector 100 and the charge pump 200. Fig. 6 is a schematic diagram showing waveforms of various points of a phase-locked loop locking timing circuit according to an embodiment of the present invention.
In the phase frequency detector 100 of the phase locked loop circuit, the first rising edge D flip-flop DFF1 and the second rising edge D flip-flop DFF2 are both clock rising edge triggered D flip-flops, that is, the state changes of the output ends (Q ends) of the first rising edge D flip-flop DFF1 and the second rising edge D flip-flop DFF2 occur at the rising edge of the clock input, and the logic values thereof are determined by data signals.
Since the charge pump 200 in the embodiment of the present invention is designed for discharging (pull-down current), when the phase-locked loop circuit is locked, the phase of the feedback clock signal Fdiv leads the reference clock signal Fref, as shown in fig. 6, at the rising edge of the feedback clock signal Fdiv, the output end (Q end) of the second rising edge D flip-flop DFF2 changes from low to high, the switch S202 is closed, and at this time, the charge pump 200 starts to discharge; when the rising edge of the reference clock signal Fref arrives, the output end (Q end) of the first rising edge D flip-flop DFF1 changes from low to high, the UP signal changes from high to low, the switch S201 is turned on, and the charge pump 200 stops discharging; at the same time, the and gate 1021 outputs high, the first rising edge D flip-flop DFF1 and the second rising edge D flip-flop DFF2 are reset, the outputs of the two D flip-flops change from high to low, the UP signal changes from low to high, the DN signal changes from high to low, and the charge pump 200 is still in the stop discharge state.
When the charge pump 200 stops discharging, the leakage current charges a loop filter (not shown), the output voltage of the loop filter increases, and the frequency of the vco accordingly increases. This is also why the phase of the feedback clock signal Fdiv will lead the reference clock signal Fref when the phase-locked loop is locked.
As shown in fig. 5, when the charge pump 200 is in the on state, only one-way current is needed, and matching between the pull-up current and the pull-down current is not needed, which greatly reduces the design difficulty. The leakage current design requirement is low, the current value is far smaller than the working current, and the selection of the size depends on the design of the fractional frequency divider. Meanwhile, the phase frequency detector does not comprise a delay unit for eliminating dead zones, so that the circuit structure is simplified.
In summary, in the technical solution provided by the present invention, the phase frequency detector does not include a delay unit for eliminating a dead zone, so as to simplify a circuit structure, and meanwhile, the charge pump only needs a unidirectional current during operation, so that the design requirement on a current source is low, the problem of matching between a pull-up current and a pull-down current is avoided, the design is simple and reliable, the linearity is high, and the phase frequency detector is very suitable for a phase-locked loop using a fractional frequency divider.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (8)
1. A phase frequency detector, comprising: the circuit comprises a first rising edge D trigger, a second rising edge D trigger, an inverting unit and a reset circuit;
a data input end of the first rising edge D trigger is coupled to a high level, a clock signal input end is coupled to a reference clock signal, a reset end is coupled to an output end of the reset circuit, an output end of the first rising edge D trigger is coupled to an input end of the inverting unit, and an output end of the inverting unit is coupled to the charge pump;
the data input end of the second rising edge D trigger is coupled to a high level, the clock signal input end is coupled to a feedback clock signal, the reset end is coupled to the output end of the reset circuit, and the output end is coupled to the charge pump.
2. A phase frequency detector as claimed in claim 1, wherein said inverting unit comprises a not gate circuit; the input end of the NOT gate circuit is coupled to the output end of the first rising edge D trigger, and the output end of the NOT gate circuit is coupled to the charge pump.
3. A phase frequency detector as claimed in claim 1 wherein said reset circuit is an and gate; the first input end of the and circuit is coupled with the output end of the first rising edge D trigger, the second input end of the and circuit is coupled with the output end of the second rising edge D trigger, and the output ends of the and circuit are respectively coupled with the reset end of the first rising edge D trigger and the reset end of the second rising edge D trigger.
4. A charge pump, comprising: first current source, second current source, first control switch and second control switch, wherein:
a first terminal of the first current source is coupled to a power supply, a second terminal of the first current source is coupled to a first terminal of the second current source, a second terminal of the second current source is coupled to a first terminal of the first control switch, a second terminal of the first control switch is coupled to a first terminal of the second control switch, and a second terminal of the second control switch is grounded;
the control end of the first control switch is coupled with an UP signal of the phase frequency detector, and the control end of the second control switch is coupled with a DN signal of the phase frequency detector;
the second terminal of the first current source is connected to the first terminal of the second current source and coupled to the output terminal of the charge pump.
5. The charge pump of claim 4, wherein the first current source is a PMOS transistor.
6. The charge pump of claim 4, wherein the second current source is an NMOS transistor.
7. The charge pump of claim 4, further comprising a third control switch and a fourth control switch, wherein a first terminal of the third control switch and a first terminal of the fourth control switch are both coupled to a power source, and a second terminal of the third control switch is connected to a second terminal of the fourth control switch and coupled to the first terminal of the first control switch; the control end of the third control switch is coupled with an UP signal of the phase frequency detector, and the control end of the fourth control switch is coupled with a DN signal of the phase frequency detector.
8. A phase locked loop circuit comprising a phase frequency detector according to any one of claims 1 to 3 and a charge pump according to any one of claims 4 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010410164.7A CN113676177A (en) | 2020-05-15 | 2020-05-15 | Phase frequency detector, charge pump and phase-locked loop circuit |
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| CN202010410164.7A CN113676177A (en) | 2020-05-15 | 2020-05-15 | Phase frequency detector, charge pump and phase-locked loop circuit |
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| CN113676177A true CN113676177A (en) | 2021-11-19 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115694477A (en) * | 2022-11-16 | 2023-02-03 | 华南理工大学 | Sub-sampling phase-locked loop based on small-range dead zone generation module architecture |
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2020
- 2020-05-15 CN CN202010410164.7A patent/CN113676177A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115694477A (en) * | 2022-11-16 | 2023-02-03 | 华南理工大学 | Sub-sampling phase-locked loop based on small-range dead zone generation module architecture |
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