CN212211224U - Video processing apparatus and system - Google Patents
Video processing apparatus and system Download PDFInfo
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- CN212211224U CN212211224U CN202021476983.3U CN202021476983U CN212211224U CN 212211224 U CN212211224 U CN 212211224U CN 202021476983 U CN202021476983 U CN 202021476983U CN 212211224 U CN212211224 U CN 212211224U
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Abstract
The utility model discloses a video processing device, including interface circuit board, master control circuit board and coding circuit board. The interface circuit board is used for connecting external equipment; the main control circuit board comprises a processor electrically connected with the interface circuit board and a memory electrically connected with the processor; the encoding circuit board comprises an FPGA chip and one or more encoding chips, the FPGA chip is connected with the processor through a PCIe bus, and the FPGA chip is connected with the encoding chips through a SelectIO interface; this practicality is through adjusting the quantity of selectIO interface, controls the effect of the quantity of the coding chip that coding circuit provided, has realized the quantity according to coding demand control coding chip, further reaches the speed of adjustment code, improves coding efficiency to accomplish the purpose of code.
Description
Technical Field
The present invention relates to the field of electronic device technology, and in particular, to a video processing device and system for encoding/decoding.
Background
With the development of security and video monitoring equipment, the technology of network transmission of videos is widely applied. At present, video pictures shot by a camera generally need to be processed through a video coding technology provided by a network video monitoring system, and then are uploaded to a server or other terminals through a network. The video encoding technology is a method for converting a file in an original video format into a file in another video format by a compression technology.
The related video coding technology mainly utilizes a processor to perform coding and decoding processing on video pictures shot by a camera. Therefore, the following technical problems mainly exist in the current video coding technology: firstly, when video coding is carried out, the device coding speed is limited frequently; secondly, when a large amount of video data is encountered, the purpose of real-time encoding is often difficult to achieve due to the performance problem of the processor.
SUMMERY OF THE UTILITY MODEL
To solve at least one of the problems described above, the present invention provides a video processing apparatus and system for encoding/decoding.
A video processing device for encoding, comprising:
the interface circuit board is used for connecting external equipment;
the main control circuit board comprises a processor electrically connected with the interface circuit board and a memory electrically connected with the processor, and the processor acquires an original video acquired by the external equipment through the interface circuit board;
the encoding circuit board comprises an FPGA chip and one or more encoding chips, the FPGA chip is connected with the processor through a PCIe bus, and the FPGA chip is connected with the encoding chips through a SelectIO interface; and the FPGA chip acquires the original video forwarded by the processor, and the encoding chip is utilized to encode the original video to obtain an encoded video.
Further, the SelectIO interface includes at least one of BT1120, I2C, and SDIO.
Furthermore, the encoding circuit board further comprises an HDMI receiving circuit, wherein the input end of the HDMI receiving circuit is connected with the processor through a high-definition multimedia interface (HDMI), and the output end of the HDMI receiving circuit is connected with the FPGA chip.
Further, the interface circuit board comprises an input interface and an output interface, the input interface comprises at least one gigabit Ethernet PHY interface, and the output interface comprises one or more of another gigabit Ethernet PHY interface, a high-capacity storage interface mSATA, wireless WIFI, a wireless 4G network, a serial port RS485, an HDMI display interface and a MicroSD card socket.
Further, the memory includes at least one of a memory DDR4 and a memory eMMC.
Further, the SelectIO interface is in gated connection with the coding chip.
A video processing device, for decoding, comprising:
the interface circuit board is used for connecting external equipment;
the main control circuit board comprises a processor electrically connected with the interface circuit board and a memory electrically connected with the processor, and the processor acquires the coded video input by the external equipment through the interface circuit board;
the decoding circuit board comprises an FPGA chip and one or more decoding chips, the FPGA chip is connected with the processor through a PCIe bus, and the FPGA chip is connected with the decoding chips through a SelectIO interface; the FPGA chip acquires the coded video forwarded by the processor, and the coded video is decoded by using the decoding chip to obtain the original video.
Further, the interface circuit board comprises an input interface and an output interface, the output interface comprises at least one gigabit Ethernet PHY interface, and the input interface comprises one or more of another gigabit Ethernet PHY interface, a high-capacity storage interface mSATA, wireless WIFI, a wireless 4G network, a serial port RS485, an HDMI display interface and a MicroSD card socket.
A video processing system includes a video processing device, and an electronic device connected thereto, the video processing device transmitting encoded video or decoded video to the electronic device. When coding, the electronic device comprises a terminal and a server which are connected with an output interface of an interface circuit board of the video processing device, and one or more network cameras which are connected with an input interface of the interface circuit board, and when decoding, the electronic device comprises a display device which is connected with the output interface of the interface circuit board of the video processing device.
According to the technical scheme, the FPGA chip and the multiple coding chips are provided through the coding circuit board, data transmission is carried out between the FPGA chip and the multiple coding chips through the SelectIO interfaces, the number of the coding chips provided by the coding circuit is controlled by adjusting the number of the SelectIO interfaces, the number of the coding chips is controlled according to coding requirements, the self-adaptive coding speed is adjusted, and the coding efficiency is improved.
When the video processing device performs coding, the processor of the main control circuit board can also bear part of the coding function and is responsible for data splitting and data merging after final coding. When the data is split, the data can be only processed primarily by the processor, the specific codes are all processed by the coding circuit board, the processor and the coding circuit board can also perform coding work, and the output interfaces can all output simultaneously or select any number of the output interfaces to output.
When the video processing equipment decodes, the input and output states of the interface circuit board interfaces are all reversed, and at the moment, a plurality of input interfaces are selected to be connected. The output interface is an Ethernet interface and is externally connected with a display device. Two video processing devices can be connected into a set of codec system.
Drawings
In order to more clearly illustrate the technical solution in the embodiment of the present invention, the drawings used in the description of the embodiment of the present invention will be briefly described below.
Fig. 1 is a schematic structural diagram of an embodiment of a video processing apparatus according to the present invention; and
fig. 2 is a schematic structural diagram of a video processing system according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
Embodiment 1 provides a video processing apparatus, as shown in fig. 1, for encoding, including an interface circuit board 10, a main control circuit board 20, and an encoding circuit board 30. The interface circuit board is used for connecting external equipment; the main control circuit board comprises a processor electrically connected with the interface circuit board and a memory electrically connected with the processor, and the processor acquires an original video acquired by the external equipment through the interface circuit board; the encoding circuit board comprises an FPGA chip and one or more encoding chips, the FPGA chip is connected with the processor through a PCIe bus, and the FPGA chip is connected with the encoding chips through a SelectIO interface; and the FPGA chip acquires the original video forwarded by the processor, and the encoding chip is utilized to encode the original video to obtain an encoded video.
In this embodiment, the FPGA chip provides 4 SelectIO interfaces, so that the coding circuit board can be connected to 4 coding chips, that is, 4 coding chips are provided to code the original video data at the same time, thereby achieving the purpose of parallel coding processing of the original video data and improving the coding efficiency.
It should be noted that the number of SelectIO interfaces may also be adjusted according to the video data amount and the coding efficiency requirement, so as to adjust the number of coding chips. In particular, the coding circuit board may also provide a natural number of coding chips of 1, 2, 3 or more than 4.
In this embodiment, the encoding circuit board further includes an HDMI receiving circuit, an input end of the HDMI receiving circuit is connected to the processor through a high-definition multimedia interface HDMI interface, and an output end of the HDMI receiving circuit is connected to the FPGA chip. The FPGA chip can acquire original video data through the HDMI receiving circuit and can also acquire the original video data through the PCIe bus. Specifically, a high-definition multimedia interface HDMI is generally arranged on a main control circuit board, a processor is connected with an HDMI receiving circuit through the high-definition multimedia interface HDMI, original video data are forwarded to an encoding circuit board through the high-definition multimedia interface HDMI, the encoding circuit board obtains the original video data through the HDMI receiving circuit, a plurality of encoding chips are controlled by an FPGA chip to encode the original video data, and the encoded original video data are returned to the processor through a PCIe bus after encoding is completed, so that the encoded video is reported by the processor.
Specifically, the SelectIO interface is configured as one of BT1120, I2C, and SDIO.
Specifically, the memory includes a memory DDR4 and a memory eMMC, and the original video data acquisition coded video is stored by the two storage elements to be uploaded.
Specifically, the main control circuit board and the coding circuit board both use the PCB as a carrier, that is, the processor and the plurality of memories are mounted on the PCB to obtain the main control circuit board; or the FPGA chip and the plurality of coding chips are installed on the PCB printed circuit to obtain a coding circuit board; as above, an interface circuit board is provided. More specifically, the interface circuit board, the main control circuit board, and the coding circuit board may be mounted within the housing.
In the embodiment of the present invention, the interface circuit board includes an input interface and an output interface, including: the input interface comprises a gigabit Ethernet PHY interface, and the output interface comprises one or more of another gigabit Ethernet PHY interface, a high-capacity storage interface mSATA, wireless WIFI, a wireless 4G network, a serial port RS485, an HDMI display interface and a MicroSD card socket.
The video processing equipment interface board is provided with two Ethernet interfaces, one is an input interface and the other is an output interface, and when coding is carried out, only one data input port, namely the Ethernet input interface, is used for transmitting video data through the interface. The other interfaces are output ports, and when the interface is used, all the interfaces can be simultaneously output or any number of the interfaces can be selected to output.
The embodiment 2 of the present application provides a video processing device for decoding, and as shown in fig. 1, the video processing device includes an interface circuit board 10, a main control circuit board 20, and a decoding circuit board 30. The interface circuit board 10 is used for connecting external equipment; the main control circuit board 20 comprises a processor electrically connected with the interface circuit board and a memory electrically connected with the processor, and the processor acquires the coded video input by the external equipment through the interface circuit board; the decoding circuit board 30 comprises an FPGA chip and one or more decoding chips, the FPGA chip is connected with the processor through a PCIe bus, and the FPGA chip is connected with the decoding chips through a SelectIO interface; the FPGA chip acquires the coded video forwarded by the processor, and the coded video is decoded by using the decoding chip to obtain the original video.
When the above-mentioned video processing device is decoding, compared with the interface circuit board interface described in embodiment 1, the input and output states are all reversed, and at this time, there are a plurality of input interfaces, and one of them is selected to be turned on. The output interface is an Ethernet interface and is externally connected with a display device.
It should be noted that the above describes independently the video processing device for encoding and the video processing device for decoding in two embodiments, but those skilled in the art can know that two video processing devices can be connected into a set of codec system. When the specific connection is a set of coding system, the coding system can be directly spliced from hardware, and some repeated components can be omitted to form a complete hardware device with the coding and decoding functions.
Embodiment 3 of the present application further provides a video processing system, which includes the video processing apparatus 100 and an electronic apparatus. As shown in fig. 2, in this embodiment, a video processing apparatus 100 is connected to a high-definition camera 200 and a display screen 101, and an electronic apparatus includes a terminal 300 and a server 400.
In application, the high definition video camera 200 is connected to the video processing apparatus 100 through an interface (e.g. an ethernet PHY interface) provided by an interface circuit board of the video processing apparatus 100, and the display screen 101 is connected through an interface (e.g. an RJ45 interface) provided by the interface circuit board of the video processing apparatus 100, that is, the display screen is used as a display device of the video processing apparatus, so that a user can view a processing result. Specifically, after the video processing device 100 acquires a video acquired by the high-definition camera 200, a processor on the main control circuit board may send the video to the encoding circuit board through a high-definition multimedia interface HDMI interface or a PCIe bus, an FPGA chip of the encoding circuit board acquires the video forwarded by the processor through the PCIe bus or acquires the video forwarded by the processor through a HDMI receiving circuit, and performs encoding processing through a plurality of preconfigured SelectIO interfaces and a plurality of encoding chips, so as to obtain an encoded video, wherein a SelectIO interface and the encoding chip corresponding to the SelectIO interface are in gated connection, and one encoding chip or a plurality of encoding chips may be selectively used according to requirements; at this point, the FPGA chip may return the encoded video to the processor over the PCIe bus. After the processor obtains the encoded video, the encoded video may be uploaded to the terminal 300 or the server 400 through a wireless communication technology or an ethernet PHY interface.
When the video processing device decodes, the output interface of the video processing device interface circuit board is an Ethernet interface which is used for connecting display devices such as a display.
While the preferred embodiments of the present invention have been described, the present invention is not limited to the above embodiments, and those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention, and such equivalent modifications or substitutions are intended to be included within the scope of the present invention defined by the appended claims.
Claims (10)
1. A video processing device for encoding, comprising:
the interface circuit board is used for connecting external equipment;
the main control circuit board comprises a processor electrically connected with the interface circuit board and a memory electrically connected with the processor, and the processor acquires an original video acquired by the external equipment through the interface circuit board;
the encoding circuit board comprises an FPGA chip and one or more encoding chips, the FPGA chip is connected with the processor through a PCIe bus, and the FPGA chip is connected with the encoding chips through a SelectIO interface; and the FPGA chip acquires the original video forwarded by the processor, and the encoding chip is utilized to encode the original video to obtain an encoded video.
2. The video processing device of claim 1, wherein the SelectIO interface comprises at least one of BT1120, I2C, and SDIO.
3. The video processing device of claim 1, wherein the encoding circuit board further comprises an HDMI receiving circuit, an input of the HDMI receiving circuit is connected to the processor through a high-definition multimedia interface (HDMI) interface, and an output of the HDMI receiving circuit is connected to the FPGA chip.
4. The video processing device of claim 1, wherein the interface circuit board comprises an input interface and an output interface, the input interface comprises at least one gigabit ethernet PHY interface, and the output interface comprises one or more of another gigabit ethernet PHY interface, a mass storage interface mSATA, WIFI wireless, 4G wireless, RS485 serial port, an HDMI display interface, and a MicroSD socket.
5. The video processing device according to claim 1, wherein the memory comprises at least one of a memory DDR4, a memory eMMC.
6. The video processing device of claim 1, wherein the SelectIO interface is gated to the encoding chip.
7. A video processing device for decoding, comprising:
the interface circuit board is used for connecting external equipment;
the main control circuit board comprises a processor electrically connected with the interface circuit board and a memory electrically connected with the processor, and the processor acquires the coded video input by the external equipment through the interface circuit board;
the decoding circuit board comprises an FPGA chip and one or more decoding chips, the FPGA chip is connected with the processor through a PCIe bus, and the FPGA chip is connected with the decoding chips through a SelectIO interface; the FPGA chip acquires the coded video forwarded by the processor, and the coded video is decoded by using the decoding chip to obtain the original video.
8. The video processing device of claim 7, wherein the interface circuit board comprises an input interface and an output interface, the output interface comprises at least one gigabit Ethernet PHY interface, and the input interface comprises one or more of another gigabit Ethernet PHY interface, a mass storage interface mSATA, WIFI, a wireless 4G network, a serial RS485 interface, an HDMI display interface, and a MicroSD card socket.
9. A video processing system comprising the video processing apparatus of any one of claims 1 to 6 and the video processing apparatus of any one of claims 7 to 8, and an electronic apparatus connected thereto, the video processing apparatus transmitting the encoded video or the decoded video to the electronic apparatus.
10. A video processing system according to claim 9, wherein the electronic device comprises a terminal connected to the video processing device interface circuit board output interface of any one of claims 1 to 6, a server and one or more webcams connected to the interface circuit board input interface, and/or wherein the electronic device comprises a display device connected to the video processing device interface circuit board output interface of any one of claims 7 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021476983.3U CN212211224U (en) | 2020-07-23 | 2020-07-23 | Video processing apparatus and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021476983.3U CN212211224U (en) | 2020-07-23 | 2020-07-23 | Video processing apparatus and system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212211224U true CN212211224U (en) | 2020-12-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021476983.3U Active CN212211224U (en) | 2020-07-23 | 2020-07-23 | Video processing apparatus and system |
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| Country | Link |
|---|---|
| CN (1) | CN212211224U (en) |
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- 2020-07-23 CN CN202021476983.3U patent/CN212211224U/en active Active
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