CN212183140U

CN212183140U - Standby power supply

Info

Publication number: CN212183140U
Application number: CN201821103658.5U
Authority: CN
Inventors: 彭碧龙
Original assignee: Shenzhen Eno Musical Instrument Co ltd
Current assignee: Shenzhen Eno Musical Instrument Co ltd
Priority date: 2018-07-12
Filing date: 2018-07-12
Publication date: 2020-12-18
Anticipated expiration: 2028-07-12

Abstract

The utility model discloses a standby power supply, which comprises a charging circuit, a charging and discharging management circuit and a battery pack, wherein the charging circuit transforms the voltage of a matched external power supply and inputs the voltage into the charging and discharging circuit; one end of the charge and discharge circuit is connected with the battery pack, the other end of the charge and discharge circuit is connected with a load, and the charge and discharge management circuit is connected with the charge and discharge circuit and controls the charge and discharge of the charge and discharge circuit. The utility model discloses a charge circuit for battery charging to switch on at the in-process that charges through charge-discharge circuit, the in-process secondary that discharges steps up and discharges, can be for the long-time effective power supply of music equipment.

Description

Standby power supply

Technical Field

The utility model relates to a power field, concretely relates to stand-by power supply.

Background

The development of electronic technology brings great progress for music, no matter traditional musical instruments or electronic musical instruments are available, the music is usually not powered on in daily training and performance, however, most of the existing music or instrumental music uses 9V power supply, so a special power supply is needed, a battery module is usually installed on related equipment in the existing scheme, and required voltage is output, because the battery is heavy, the use of the related equipment is influenced, meanwhile, the endurance is not ideal, another existing scheme is to use a voltage transformation device, the on-site alternating current is directly transformed into required voltage, and meanwhile, multiple paths of output are output, and the scheme is also not beneficial to use due to the need of an external power supply.

SUMMERY OF THE UTILITY MODEL

In order to overcome the defects of the prior art, the utility model aims to provide a stand-by power supply which breaks away from the mains supply can provide electric energy with set voltage for music related equipment while ensuring cruising power.

The utility model provides a technical scheme as follows:

a standby power supply comprises a charging circuit, a charging and discharging management circuit and a battery pack, wherein the charging circuit transforms a matched external power supply and inputs the transformed external power supply to the charging and discharging circuit; one end of the charge and discharge circuit is connected with the battery pack, the other end of the charge and discharge circuit is connected with a load, and the charge and discharge management circuit is connected with the charge and discharge circuit and controls the charge and discharge of the charge and discharge circuit.

Further, the charging circuit includes a first PMOS transistor Q6, a first NMOS transistor Q12, a first inductor L1, a first diode D3, a second diode D4, a first capacitor C3, a second capacitor C16, a third capacitor C17, a first relay J1, a first resistor R29 and a boost chip FLD5912, wherein an input end of the first relay J1 is connected with an anode of an external power supply, an output end of the first relay J1 is respectively connected with two ends of the first resistor R29 and an anode and a cathode of the first capacitor C3, a source of the first PMOS transistor Q6 is connected with one end of the battery management module, and a source of the first PMOS transistor Q6 is connected in parallel with an anode of the first capacitor C3; the drain electrode of the first MOS tube is respectively connected with the cathode of a second diode D4, the drain electrode of a first NMOS tube Q12 and the input end of a first inductor L1; the grid electrode of the first PMOS tube Q6 is connected with the second port of the boost chip FLD 5912; the output end of the first inductor L1 is connected to the anode of a first diode D3, and the cathode of the first diode D3 is connected to the anode of the second capacitor C16, the anode of the third capacitor C17 and the anode of the load, respectively. The cathode of the first capacitor C3, the anode of the second diode D4, the source of the first NMOS transistor Q12, the cathode of the second capacitor C16 and the cathode of the third capacitor C17 are connected in parallel and grounded.

Further, the charging and discharging circuit comprises a battery pack interface, at least one group of boosting capacitors, a second PMOS transistor Q1, a third PMOS transistor Q2, a fourth PMOS transistor Q3 and a fifth PMOS transistor Q4, wherein the battery pack interface comprises at least one group of battery ports connected with a battery pack, the battery ports are connected with battery cells in the battery pack, and the battery ports correspond to the boosting capacitors; the battery port is connected with the source electrode of the second PMOS tube Q1, the battery port is also connected with one end of a boosting capacitor, the other end of the boosting capacitor is connected with the source electrode of the second PMOS tube Q1, and the drain electrode of the PMOS tube Q1 is connected with the drain electrode of the third PMOS tube Q2; the source electrode of the third PMOS tube Q2 is connected with the drain electrode of the fourth PMOS tube Q3, the source electrode of the fourth PMOS tube Q3 is connected with the source electrode of the fifth PMOS tube, the grid electrode of the fifth PMOS tube is connected with the grid electrode of the fourth MOS tube and is connected with the charge and discharge management circuit, and the drain electrode of the fifth PMOS tube is connected with the load and the charge circuit.

Furthermore, the charge and discharge management circuit comprises a charge and discharge control chip S8254AAK, a port 1 of the charge and discharge control chip S8254AAK is connected with a grid electrode of a third PMOS tube Q2, a port 3 of the charge and discharge control chip S8254AAK is connected with a grid electrode of a second PMOS tube Q1, a port 11 of the charge and discharge control chip S8254AAK is connected with the battery pack interface, and ports 12 to 15 of the charge and discharge control chip S8254AAK are connected with a low-voltage end of the boost capacitor in a charging state.

Furthermore, the ports 12 to 15 of the charge and discharge control chip S8254AAK are connected to the battery pack interface.

Further, the charge and discharge circuit comprises a sixth capacitor C1, one end of the sixth capacitor C1 is connected with the positive pole of the load, and the other end of the sixth capacitor C1 is connected with the negative pole of the load.

Further, the charging and discharging detection circuit comprises a voltage feedback amplifier SGM358 and a fourth capacitor C14, one end of the fourth capacitor C14 is connected with the battery pack, and the other end of the fourth capacitor C14 is grounded; one end of the fourth capacitor C14 is connected to the non-inverting terminal of the first comparator of the voltage feedback amplifier SGM358 and the inverting terminal of the second comparator as an SRN terminal, the first comparator outputs a charging voltage, the SRP terminal of the fourth capacitor C14 is connected to the inverting terminal of the first comparator and the non-inverting terminal of the second comparator, and the second comparator outputs a discharging voltage.

Furthermore, the electric quantity detection circuit comprises an electric quantity detection controller SN8F570210, a first triode Q11, a second triode Q9 and a fifth capacitor C18, wherein the base of the first triode Q11 is connected with the output end of the first comparator, the collector of the first triode Q11 is connected with the port No. 4 of the electric quantity detection controller SN8F570210, a low level is output during charging, the base of the second triode Q9 is connected with the output end of the second comparator, the collector of the second triode Q9 is connected with the port No. 6 of the electric quantity detection controller SN8F570210, and a low level is output in a discharging state; no. 11 port of electric quantity detection controller SN8F570210 is connected with external power supply positive pole, No. 10 port of electric quantity detection controller SN8F570210 is connected with the group battery positive pole, the one end of fifth electric capacity C18 with No. 9 port of electric quantity detection controller SN8F570210 is connected, the other end of fifth electric capacity C18 is connected with the group battery positive pole.

Compared with the prior art, the utility model discloses a charge circuit is battery charging to switch on at the in-process that charges through charge-discharge circuit, boost at the in-process secondary that discharges and discharge, can be for the long-time effective power supply of music equipment.

Drawings

Fig. 1 is a block diagram of a standby power supply according to the present invention.

Fig. 2 is a circuit diagram of a charging circuit of the standby power supply of the present invention.

Fig. 3 is a circuit diagram of the boost chip FLD5912 of the charging circuit of the standby power supply of the present invention.

Fig. 4 is a circuit diagram of the charging and discharging circuit and the charging and discharging management circuit of the standby power supply of the present invention.

Fig. 5 is the utility model relates to a charging and discharging detection circuit of stand-by power supply.

Fig. 6 is the utility model relates to a stand-by power supply electric quantity detection circuit.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The standby power supply comprises a charging circuit, a charging and discharging management circuit and a battery pack, wherein the charging circuit transforms a matched external power supply and inputs the transformed external power supply to the charging and discharging circuit; one end of the charge and discharge circuit is connected with the battery pack, the other end of the charge and discharge circuit is connected with a load, and the charge and discharge management circuit is connected with the charge and discharge circuit and controls the charge and discharge of the charge and discharge circuit.

In a charging state, an external 5V direct-current power supply raises the voltage to be higher than the charging voltage of a battery pack through a charging circuit, the charging and discharging circuit is conducted under the control of the charging and discharging control circuit to charge the battery pack, in one embodiment, the battery pack is a two-string four-parallel lithium battery pack, at the moment, the charging circuit raises the voltage to be more than 8.4V, and all switch elements on the charging and discharging circuit are opened under the control of the charging and discharging circuit; in the discharging state, the charging and discharging circuit raises the voltage to the working voltage under the control of the charging and discharging control circuit, and the voltage is stably output.

The charging circuit comprises a first PMOS tube Q6, a first NMOS tube Q12, a first inductor L1, a first diode D3, a second diode D4, a first capacitor C3, a second capacitor C16, a third capacitor C17, a first relay J1, a first resistor R29 and a boost chip FLD5912, wherein the input end of the first relay J1 is connected with the anode of an external power supply, the output end of the first relay J1 is respectively connected with the two ends of the first resistor R29 and the anode and the cathode of the first capacitor C3, the source of the first PMOS tube Q6 is connected with one end of a battery management module, and the source of the first PMOS tube Q6 is connected with the anode of the first capacitor C3 in parallel; the drain electrode of the first MOS tube is respectively connected with the cathode of a second diode D4, the drain electrode of a first NMOS tube Q12 and the input end of a first inductor L1; the grid electrode of the first PMOS tube Q6 is connected with the second port of the boost chip FLD 5912; the output end of the first inductor L1 is connected to the anode of a first diode D3, and the cathode of the first diode D3 is connected to the anode of the second capacitor C16, the anode of the third capacitor C17 and the anode of the load, respectively. The cathode of the first capacitor C3, the anode of the second diode D4, the source of the first NMOS transistor Q12, the cathode of the second capacitor C16 and the cathode of the third capacitor C17 are connected in parallel and grounded.

The charging circuit adopts a DC-DC circuit, an external power supply boosts the voltage through the first inductor L1 under the switching action of a first PMOS transistor Q6, the voltage boosting chip FLD5912 controls the voltage boosting circuit to boost the voltage through constantly outputting a high level to the grid electrode of the first MOS transistor Q6, and controls the work of the charging circuit through the first NMOS transistor Q12 serving as a switch of the voltage boosting circuit.

The charging and discharging circuit comprises a battery pack interface, at least one group of boosting capacitors, a second PMOS tube Q1, a third PMOS tube Q2, a fourth PMOS tube Q3 and a fifth PMOS tube Q4, wherein the battery pack interface comprises at least one group of battery ports connected with a battery pack, the battery ports are connected with battery monomers in the battery pack, and the battery ports correspond to the boosting capacitors; the battery port is connected with the source electrode of the second PMOS tube Q1, the battery port is also connected with one end of a boosting capacitor, the other end of the boosting capacitor is connected with the source electrode of the second PMOS tube Q1, and the drain electrode of the PMOS tube Q1 is connected with the drain electrode of the third PMOS tube Q2; the source electrode of the third PMOS tube Q2 is connected with the drain electrode of the fourth PMOS tube Q3, the source electrode of the fourth PMOS tube Q3 is connected with the source electrode of the fifth PMOS tube, the grid electrode of the fifth PMOS tube is connected with the grid electrode of the fourth MOS tube and is connected with the charge and discharge management circuit, the drain electrode of the fifth PMOS tube is connected with a load and the charge circuit, the charge and discharge circuit comprises a sixth capacitor C1, one end of the sixth capacitor C1 is connected with the positive electrode of the load, and the other end of the sixth capacitor C1 is connected with the negative electrode of the load.

In a charging state, the grids of the third PMOS transistor Q2 and the fourth PMOS transistor Q3 receive a high level and are conducted, the charging and discharging circuit forms a path to charge the battery pack through the charging and discharging circuit, in a discharging state, the grid of the fifth PMOS transistor Q4 is connected with the high level and is conducted, the grid of the second PMOS transistor Q1 serves as a switch, under the coordination of the boosting capacitor, the voltage is boosted and 9V voltage is output to a load, in a discharging process, the voltage is stabilized through the sixth capacitor C1, noise of a power supply is reduced, and the music equipment is prevented from being interfered by the discharging process.

The charge and discharge management circuit comprises a charge and discharge control chip S8254AAK, a port 1 of the charge and discharge control chip S8254AAK is connected with a grid electrode of a third PMOS tube Q2, a port 3 of the charge and discharge control chip S8254AAK is connected with a grid electrode of a second PMOS tube Q1, and a port 11 of the charge and discharge control chip S8254AAK is connected with a battery pack interface. The ports 12 to 15 of the charge and discharge control chip S8254AAK are connected to the battery pack interface, and in a charged state, the ports 12 to 15 of the charge and discharge control chip S8254AAK are connected to the low-voltage end of the boost capacitor.

The charge and discharge management circuit controls the on-off of the circuit by controlling the grids of the second PMOS tube Q1 and the third PMOS tube Q2 to control the charge and discharge of the battery pack, and the charge and discharge control chip S8254AAK controls the on-off of the second MOS tube Q1 according to the voltage of the boost capacitor to charge the load by pump type boost.

The first comparator is oppositely connected with the high level of the SRN in a charging state and outputs a charging voltage signal, and the second comparator is oppositely connected with the high level of the SRP in a discharging state and outputs a discharging voltage signal.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention should be covered by the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A standby power supply is characterized by comprising a charging circuit, a charging and discharging management circuit and a battery pack, wherein the charging circuit transforms a matched external power supply and inputs the transformed external power supply to the charging and discharging circuit; one end of the charge and discharge circuit is connected with the battery pack, the other end of the charge and discharge circuit is connected with a load, and the charge and discharge management circuit is connected with the charge and discharge circuit and controls the charge and discharge circuit to be conducted in the charging process and to be subjected to voltage boosting and voltage stabilizing discharge in the discharging process.

2. A backup power supply according to claim 1, characterized in that: the charging circuit comprises a first PMOS tube Q6, a first NMOS tube Q12, a first inductor L1, a first diode D3, a second diode D4, a first capacitor C3, a second capacitor C16, a third capacitor C17, a first relay J1, a first resistor R29 and a boost chip FLD5912, wherein the input end of the first relay J1 is connected with the anode of an external power supply, the output end of the first relay J1 is respectively connected with the two ends of the first resistor R29 and the anode and the cathode of the first capacitor C3, the source of the first PMOS tube Q6 is connected with one end of a battery management module, and the source of the first PMOS tube Q6 is connected with the anode of the first capacitor C3 in parallel; the drain electrode of the first NMOS transistor Q12 is respectively connected with the cathode of the second diode D4, the drain electrode of the first NMOS transistor Q12 and the input end of the first inductor L1; the grid electrode of the first PMOS tube Q6 is connected with the second port of the boost chip FLD 5912; the output end of the first inductor L1 is connected with the anode of a first diode D3, the cathode of the first diode D3 is respectively connected with the anode of a second capacitor C16, the anode of a third capacitor C17 and the anode of a load, and the cathode of the first capacitor C3, the anode of a second diode D4, the source of the first NMOS transistor Q12, the cathode of the second capacitor C16 and the cathode of the third capacitor C17 are connected in parallel and grounded.

3. A backup power supply according to claim 1, characterized in that: the charging and discharging circuit comprises a battery pack interface, at least one group of boosting capacitors, a second PMOS tube Q1, a third PMOS tube Q2, a fourth PMOS tube Q3 and a fifth PMOS tube Q4, wherein the battery pack interface comprises at least one group of battery ports connected with a battery pack, the battery ports are connected with battery monomers in the battery pack, and the battery ports correspond to the boosting capacitors; the battery port is connected with the source electrode of the second PMOS tube Q1, the battery port is also connected with one end of a boosting capacitor, the other end of the boosting capacitor is connected with the source electrode of the second PMOS tube Q1, and the drain electrode of the PMOS tube Q1 is connected with the drain electrode of the third PMOS tube Q2; the source electrode of the third PMOS tube Q2 is connected with the drain electrode of the fourth PMOS tube Q3, the source electrode of the fourth PMOS tube Q3 is connected with the source electrode of the fifth PMOS tube, the grid electrode of the fifth PMOS tube is connected with the grid electrode of the fourth MOS tube and is connected with the charge and discharge management circuit, and the drain electrode of the fifth PMOS tube is connected with the load and the charge circuit.

4. A backup power supply according to claim 3, characterized in that: the charge and discharge management circuit comprises a charge and discharge control chip S8254AAK, a port 1 of the charge and discharge control chip S8254AAK is connected with a grid electrode of a third PMOS tube Q2, a port 3 of the charge and discharge control chip S8254AAK is connected with a grid electrode of a second PMOS tube Q1, a port 11 of the charge and discharge control chip S8254AAK is connected with a battery pack interface, ports 12 to 15 of the charge and discharge control chip S8254AAK are connected with the battery pack interface, and ports 12 to 15 of the charge and discharge control chip S8254AAK are connected with a low-voltage end of the boost capacitor in a charging state.

5. A backup power supply according to claim 1, characterized in that: the charging and discharging circuit comprises a sixth capacitor C1, one end of the sixth capacitor C1 is connected with the anode of the load, and the other end of the sixth capacitor C1 is connected with the cathode of the load.

6. A backup power supply according to claim 1, characterized in that: the charging and discharging detection circuit comprises a voltage feedback amplifier SGM358 and a fourth capacitor C14, one end of the fourth capacitor C14 is connected with the battery pack, and the other end of the fourth capacitor C14 is grounded; one end of the fourth capacitor C14 is connected to the non-inverting terminal of the first comparator of the voltage feedback amplifier SGM358 and the inverting terminal of the second comparator as an SRN terminal, the first comparator outputs a charging voltage, the SRP terminal of the fourth capacitor C14 is connected to the inverting terminal of the first comparator and the non-inverting terminal of the second comparator, and the second comparator outputs a discharging voltage.

7. The backup power supply of claim 6, wherein: the electric quantity detection circuit comprises an electric quantity detection controller SN8F570210, a first triode Q11, a second triode Q9 and a fifth capacitor C18, wherein the base electrode of the first triode Q11 is connected with the output end of the first comparator, the collector electrode of the first triode Q11 is connected with the No. 4 port of the electric quantity detection controller SN8F570210, a low level is output during charging, the base electrode of the second triode Q9 is connected with the output end of the second comparator, the collector electrode of the second triode Q9 is connected with the No. 6 port of the electric quantity detection controller SN8F570210, and a low level is output in a discharging state; no. 11 port of electric quantity detection controller SN8F570210 is connected with external power supply positive pole, No. 10 port of electric quantity detection controller SN8F570210 is connected with the group battery positive pole, the one end of fifth electric capacity C18 with No. 9 port of electric quantity detection controller SN8F570210 is connected, the other end of fifth electric capacity C18 is connected with the group battery positive pole.