CN212135670U

CN212135670U - NAVTEX receiving system based on FPGA

Info

Publication number: CN212135670U
Application number: CN202020441959.XU
Authority: CN
Inventors: 张�林; 朱健; 李亮
Original assignee: Suzhou Xinyangsheng Technology Co ltd
Current assignee: Suzhou Xinyangsheng Technology Co ltd
Priority date: 2020-03-31
Filing date: 2020-03-31
Publication date: 2020-12-11
Anticipated expiration: 2030-03-31

Abstract

The utility model discloses a NAVTEX receiving system based on FPGA, include: the display control unit is used for user interaction and related message application services; the power supply management module is used for generating various power supplies in the system; the transmitting unit is used for generating a self-circulation test signal and carrying out power-on self-test of the system; a receiving unit for receiving and sampling radio frequency signals; the signal switching unit is used for selecting a radio frequency signal to be sampled, switching and connecting the radio frequency signal to the transmitting unit during self-checking and switching and connecting the radio frequency signal to the NAVTEX receiving antenna during working; and the FPGA signal processing unit is used for demodulating the sampling radio frequency signal and carrying out 2FSK modulation on the digital signal. The utility model provides a NAVTEX receiving system based on FPGA can realize the NAVTEX signal reception of different frequency channels of multichannel on same hardware device to can carry out the configuration of arbitrary quantity and frequency channel to the receiving channel under the circumstances that FPGA resource allows; meanwhile, because the system adopts a fully digital signal processing unit, the receiving sensitivity of the NAVTEX receiving system has higher consistency.

Description

NAVTEX receiving system based on FPGA

Technical Field

The utility model relates to a NAVTEX message receiving technology, especially NAVTEX receiving system based on FPGA belongs to wireless communication technical field.

Background

NAVTEX (navavailable telex) is an abbreviation for navigation warning dissemination system, which is an important component of global maritime distress and security systems, and is also one of the components of worldwide navigation warning services (WWNWS) specified by International Maritime Organization (IMO) a.419(XI) resolution. The NAVTEX system transmits navigation warnings, weather forecasts and emergency information (collectively referred to as marine safety information MSI) to ships in the 400 nautical and maritime territory by using a relevant coastal radio station in a narrowband direct lettering telegraph (NBDP) mode, and the ships automatically receive messages through the NAVTEX receiving system, so that reliable guarantee is provided for marine navigation safety of the ships.

The NAVTEX receiving system should be capable of receiving NAVTEX information for at least two frequencies simultaneously, where a 518KHz channel is used to receive english NAVTEX information and one or more channels are used to receive NAVTEX information for a home country or region. The traditional NAVTEX receiving system adopts an analog demodulation decision scheme, the structure of a demodulation circuit is very complex, so that the receiving system has unpredictable potential risks in the processes of modulation and volume production, and the cost of the analog demodulation solution is high. Besides, the design of the receiving system is mostly fixed frequency points, which cannot meet different requirements of different regions. The receiving of the multi-channel NAVTEX signals in different frequency bands is realized on the same hardware device, and the receiving channels can be configured in any number and frequency bands according to the actual application requirements, so that the receiving system has better applicability. Meanwhile, the system complexity and cost can be effectively reduced by adopting a fully digital signal processing unit, and the receiving sensitivity can also keep higher consistency.

SUMMERY OF THE UTILITY MODEL

The to-be-solved technical problem of the present invention is to provide a fully digital receiving demodulation scheme and to perform configuration of any number and frequency band for the receiving channel according to the practical application requirement.

In order to solve the technical problem, the utility model provides a NAVTEX receiving system based on FPGA, including showing accuse unit, power management module, transmitting element, receiving element, signal switching unit and FPGA signal processing unit;

the NAVTEX receiving antenna is connected with the signal switching unit, the signal switching unit is connected with the transmitting unit and the receiving unit, the signal switching unit is used for selecting radio frequency signals to be sampled, the NAVTEX receiving system is connected to the transmitting unit during self-checking, and the NAVTEX receiving system is switched to be connected to the NAVTEX receiving antenna during working;

the transmitting unit is connected with the FPGA signal processing unit and generates a radio frequency signal according to the digital signal modulated by the FPGA signal processing unit for detecting the function and the performance of the system when the system is started;

the receiving unit is connected with the FPGA signal processing unit, and is used for carrying out conversion from a radio frequency single end to a difference on an input signal and carrying out digital sampling on the signal after the input impedance matching unit is carried out;

the FPGA signal processing unit demodulates the digitally sampled signal according to a signal demodulation algorithm and performs 2FSK modulation on the digital signal;

the display control unit is connected with the FPGA signal processing unit, analyzes the demodulated digital signal of the FPGA signal processing unit, converts the signal into message information by using message service and displays the message information, and provides a user interaction interface;

and the power supply management module provides power supply for the display control unit, the transmitting unit, the receiving unit, the signal switching unit and the FPGA signal processing unit.

The power management module includes: the DA power supply module is used for generating various power supplies required by the transmitting unit; the AD power supply module is used for generating various power supplies required by the receiving unit; and the FPGA power supply module is used for generating core 1.8V power supply and pin 3.3V power supply of the FPGA signal processing unit.

The transmitting unit includes: the DA unit generates an analog signal according to the modulated digital signal when the machine is powered on and self-checked; and the attenuation unit is used for attenuating the analog signal generated by the DA unit into a useful radio frequency signal so as to realize the detection of the function and the performance of the system.

The receiving unit includes: the radio frequency conversion unit is used for carrying out differential conversion on the input single-ended radio frequency signal; the impedance matching unit is used for matching the input impedance of the AD unit according to the frequency band of the input signal; and the AD unit is used for performing digital conversion on the differential radio frequency signals, and the same radio frequency signal input path is used, so that the mutual interference caused by using different radio frequency paths is reduced.

The signal switching unit includes: the protection unit is used for limiting the amplitude of the radio frequency signal passing through the antenna and preventing the system from being damaged by overlarge input signal; the band-pass filtering unit is used for performing band-pass frequency selection on the radio-frequency signals input through the antenna so as to prevent signals of other frequency bands from generating interference on a system; and the relay is used for switching and selecting signals to be sampled, is connected with the transmitting unit during self-checking and is connected with the output stage of the band-pass filtering unit during working.

The FPGA signal processing unit comprises: the NAVTEX demodulation module is used for carrying out 2FSK demodulation on the digitized signal according to an algorithm and outputting a demodulated digital signal; and the NAVTEX modulation module generates a 2FSK analog signal of a designated frequency point according to the debugging digital signal. The NAVTEX demodulation module can be used for configuring any number and frequency bands according to actual application requirements; the NAVTEX modulation module can configure any frequency band according to actual requirements.

The NAVTEX demodulation module in the FPGA signal processing unit further includes: 4 multipliers, 1 DDS synthesis, 2 CIC extraction, 2 FIR band-pass, 2 time-delay units, 1 adder, 1 synchronous decision, 1 clock frequency division and 1 receiving frequency band register. Two multipliers are used for carrying out digital down-conversion on the sampling signals, and the other two multipliers are used for carrying out quadrature demodulation on the signals; synthesizing 1 DDS for generating sine and cosine signals corresponding to demodulation frequency points; 2 CIC extraction for performing extraction filtering on the data after the digital down-conversion; 2 FIR band-pass filters are used for performing band-pass filtering on the signals extracted by the CIC to obtain baseband signals in the required corresponding frequency band; 2 time delay units for time delay and temporary storage of the signal after band-pass filtering; 1 adder, which is used to carry out quadrature demodulation to the signal after band-pass filtering; 1 synchronous decision, which is used to ensure the correctness and synchronism of the demodulated data; 1 clock frequency division for generating the clock required by the delayer by dividing the clock signal frequency; and 1 receiving frequency range register for setting the demodulation frequency point of the NAVTEX demodulation module.

The NAVTEX modulation module in the FPGA signal processing unit further includes: 2 registers, 1 selector (100bps sync), 2 DDS synthesis, 2 multipliers, 1 adder, and 1 transmit band register. The 2 registers are respectively used for temporarily storing DDS synthesis parameters corresponding to 0.915KHz and 1.085 KHz; 1 selector (100bps synchronous) for selecting parameters to be subjected to DDS synthesis according to the digital modulation signal; 2 DDSs are synthesized, wherein one DDS generates 1K +/-85 Hz sine and cosine baseband signals, and the other DDS generates up-conversion sine and cosine signals of corresponding frequency points; 2 multipliers, which are used for carrying out digital up-conversion on the baseband signals; 1 adder for synthesizing modulated signal; and the 1 transmitting frequency range register is used for setting a modulation frequency point of the NAVTEX modulation module.

Compared with the prior art, the utility model has the following advantage: the receiving of the multi-channel NAVTEX signals in different frequency bands is realized on the same hardware device, and the receiving channels can be configured in any number and frequency bands according to the actual application requirements, so that the receiving system has better applicability; meanwhile, the system complexity and cost can be effectively reduced by adopting a fully digital signal processing unit, and the receiving sensitivity can also keep higher consistency.

Drawings

Fig. 1 is a schematic structural diagram of a NAVTEX receiving system based on an FPGA according to the present invention;

fig. 2 is a schematic diagram of an embodiment of a power management module in an FPGA-based NAVTEX receiving system according to the present invention;

fig. 3 is a schematic diagram of an embodiment of a transmitting unit in a NAVTEX receiving system based on FPGA according to the present invention;

fig. 4 is a schematic diagram of a specific embodiment of a receiving unit in a NAVTEX receiving system based on an FPGA according to the present invention;

fig. 5 is a schematic diagram of an embodiment of a signal switching unit in a NAVTEX receiving system based on FPGA according to the present invention;

fig. 6 is a schematic diagram of an embodiment of a three-channel receiving system of an FPGA signal processing unit in an FPGA-based NAVTEX receiving system according to the present invention;

fig. 7 is a schematic structural diagram of a NAVTEX demodulation module in an embodiment of the NAVTEX receiving system based on the FPGA;

fig. 8 is a schematic structural diagram of a NAVTEX modulation module in an embodiment of the NAVTEX receiving system based on the FPGA.

Detailed Description

The following description and explanation of the invention in a comprehensive and detailed manner is given by referring to the figures as a three-channel exemplary embodiment of the invention:

as shown in fig. 1, the FPGA-based NAVTEX receiving system 100 includes: the device comprises a display control unit 101, a power management module 102, a transmitting unit 103, a receiving unit 104, a signal switching unit 105 and an FPGA signal processing unit 106.

The display and control unit 101 analyzes and demodulates the digital signal, converts the signal into message information by using a message service, displays the message information, and provides a user interaction interface. For example, demodulated digital signals of 518KHz and 486KHz are received from the IO pins of the FPGA signal processing unit 106, respectively; writing parameters into a register in the FPGA signal processing unit 106 through a serial port; the modulated digital signal and the like are transmitted through the IO pin of the FPGA signal processing unit 106.

And the power management module 102 is used for generating power required by each unit in the system. For example, 3.3V digital power and 3V analog power required for the transmission unit 103 are generated; generating a 3.3V digital power supply and a 3V analog power supply required by the receiving unit 104; and generating a 1.8V core voltage, a 3.3V pin voltage and the like required by the FPGA signal processing unit 106.

The transmitting unit 103 generates a radio frequency signal according to the modulated digital signal, and is used for performing function and performance detection when the system is powered on, for example, when the system is powered on for self-test, the transmitting unit transmits a self-test message at a 486KHz frequency point, and the NAVTEX system receives a correct error-free message, which indicates that the system is qualified for self-test and can be used normally.

And the receiving unit 104 is used for performing radio frequency single-end to differential conversion on the input signal, and performing digital sampling on the signal after the input impedance matching unit is performed.

The signal switching unit 105 is configured to select a radio frequency signal to be sampled. For example, when the system is powered on for self-test, the input terminal of the switching receiving unit 104 is connected to the output terminal of the transmitting unit 103; when the system normally receives the NAVTEX message, the input of the switch receive unit 104 is connected to the NAVTEX receive antenna.

The FPGA signal processing unit 106 demodulates the digitally sampled signal according to a signal demodulation algorithm, and performs 2FSK modulation on the digital signal. For example, for a 3-channel receiving system, when the system normally receives a NAVTEX message, it needs to receive 486KHz, 518KHz and 4209.5KHz messages at the same time, configure internal channel parameters through the display and control unit 101, and perform orthogonal demodulation of corresponding frequency points on data output by the receiving unit 104; when the system is started for self-test, self-test messages of 486KHz, 518KHz and 4209.5KHz are generated in batches.

As shown in fig. 2, the power management module 102 in the FPGA-based NAVTEX receiving system 100 further includes: a DA power supply module 2021, an AD power supply module 2022, and an FPGA power supply module 2023.

The DA power supply module 2021 is configured to generate a 3.3V digital power supply and a 3V analog power supply required by the transmitting unit 103.

And the AD power supply module 2022 is configured to generate a 3.3V digital power supply and a 3V analog power supply required by the receiving unit 104.

And the FPGA power supply module 2023 is used for generating a 1.8V core voltage and a 3.3V pin voltage of the FPGA signal processing unit 106.

The ground of the analog power supply and the ground of the digital power supply are both connected to the system ground through a single point nearby.

As shown in fig. 3, the transmitting unit 103 in the FPGA-based NAVTEX receiving system 100 further includes: a DA unit 3031 and an attenuation unit 3032.

The DA unit 3031 receives data from the FPGA signal processing unit 106, and performs digital-to-analog conversion according to the modulated digital signal to generate a modulated analog signal in a corresponding frequency band.

The attenuation unit 3032 is connected to the output end of the DA unit 3031, attenuates the analog signal, and outputs the attenuated analog signal to the signal switching unit 105.

As shown in fig. 4, the receiving unit 104 in the FPGA-based NAVTEX receiving system 100 further includes: a radio frequency conversion unit 4041, a matching impedance 4042 and an AD unit 4043.

The rf conversion unit 4041 is configured to perform single-ended signal to differential signal conversion on the rf signal output by the signal switching unit 105, and then output the rf signal to the matching impedance 4042.

The matching impedance 4042 matches the input impedance of the AD unit according to the frequency band of the input signal, and then further outputs the differential radio frequency signal to the AD unit 4043. For example, an impedance matching network of 120 ohm resistors and 470 picofarad capacitors is used.

AD unit 4043 digitizes and converts the differential rf signal.

The embodiment of the receiving unit uses the same radio frequency signal input path, and reduces mutual interference caused by using different radio frequency paths. Meanwhile, through AD sampling, a subsequent signal demodulation can adopt a fully digital signal processing unit, the complexity and the cost of a system can be effectively reduced, and the receiving sensitivity can also keep higher consistency.

As shown in fig. 5, the signal switching unit 105 in the FPGA-based NAVTEX receiving system 100 further includes: a protection unit 5051, a band-pass filter unit 5052, and a relay 5053.

The protection unit 5051 is connected to a NAVTEX receiving antenna, and limits the amplitude of the radio frequency signal passing through the antenna to prevent the system from being damaged by excessive input signals. For example, a dual diode may be used to clamp the signal.

The band-pass filter unit 5052 is connected to the output end of the protection unit 5051, and performs band-pass frequency selection on the input radio frequency signal to prevent signals of other frequency bands from generating interference on the system. For example, an inductor and a capacitor can be used to build a 7 th order Chebyshev filter low pass with a passband of 0 Hz-30 MHz.

The relay 5053 has two input terminals connected to the output terminal of the band-pass filter unit 5052 and the output terminal of the transmission unit 103, respectively, for switching selection of a signal to be sampled. For example, when the system is turned on for self-test, the relay 5053 is connected to the output terminal of the transmission unit 103; a relay 5053 is connected to the output of the band-pass filter unit 5052 when the system is operating normally to receive NAVTEX messages.

As shown in fig. 6, the FPGA signal processing unit 106 in the FPGA-based NAVTEX receiving system 600 further includes: a first NAVTEX demodulation module 6061, a second NAVTEX demodulation module 6062, a third NAVTEX demodulation module 6063, and a NAVTEX modulation module 6064.

The first NAVTEX demodulation module 6061, the second NAVTEX demodulation module 6062, and the third NAVTEX demodulation module 6063 are connected to the output end of the receiving unit 104, and perform 2FSK demodulation on the digitized signals at three set frequency points respectively according to an algorithm, and output demodulated digital signals, which are output to the display control unit 101 through an IO pin.

The NAVTEX modulation module 6064 generates 2FSK data of a designated frequency point from the debug digital signal, and outputs the data to the transmission unit 103 to generate a radio frequency signal for self-inspection.

As shown in fig. 7, any NAVTEX demodulation module in the FPGA-based NAVTEX receiving system further includes:

multipliers

7001, 7002, 7010, 7011, DDS synthesis 7003, CIC decimation 7004, 7005, FIR filtering 7006, 7007,

delays

7008, 7009, adder 7012, synchronous decision 7013, clock division 7014 and receive band register 7015.

Multipliers

7001 and 7002 are used for digital DDC down-conversion of FSK sampling signals, thereby generating baseband signals corresponding to + -85 Hz quadrature components.

And the DDS synthesis 7003 is used for generating sine and cosine signals corresponding to the demodulation frequency points and is respectively connected to one of the input and output ends of the

multipliers

7001 and 7002.

CIC decimators 7004 and 7005 are used to decimate the digitally down converted data to reduce the data throughput of the signal processing. For example, for a 100MHz sample input, 6250 snapshots are taken to obtain a 16KHz sample output.

And FIR band-pass 7006 and 7007 for band-pass filtering the signal after CIC extraction to obtain the baseband signal in the required corresponding filtering frequency band. For example, a 256-point digital FIR filter can be selected, the band-pass range of 20Hz to 150Hz is used, and the out-of-band attenuation is designed to be-80 dB, so as to meet the out-of-band performance related requirements of the NAVTEX receiving system.

And the

time delays

7008 and 7009 are used for carrying out time delay temporary storage on the band-pass filtered signals for subsequent quadrature demodulation.

Multipliers 7010 and 7011, in conjunction with the

delay buffers

7008 and 7009 at the previous time, are used to quadrature demodulate the FIR filtered signals.

An adder 7012, configured to add the quadrature demodulation components to the band-pass filtered signal to obtain a quadrature demodulation result.

And a synchronization decision 7013, which ensures the correctness and synchronization of the demodulated data through the set demodulation threshold and the synchronization sample.

Clock divider 7014 is used to divide the clock signal to generate the clock required by the delay. For example, 6250 frequency divisions are used to generate a 16KHz reference clock signal.

And the receiving frequency range register 7015 is configured by the display control unit through a serial port and is used for setting a demodulation frequency point of the NAVTEX demodulation module.

The NAVTEX demodulation module can perform related configurations such as demodulation frequency points and demodulation bandwidth according to actual use requirements, so that the NAVTEX demodulation module has good platform universality, maintainability and the like.

As shown in fig. 8, the NAVTEX modulation module in the FPGA-based NAVTEX receiving system further includes: a 0.915KHz register 801, a 1.085KHz register 802, a selector (100bps sync) 803,

DDS synthesis

804 and 805, multipliers 806 and 807, an adder 809, and a transmit band register 809.

The 0.915KHz register 801 and the 1.085KHz register 802 are respectively used for temporarily storing the DDS synthesis parameters corresponding to 0.915KHz and 1.085 KHz.

The selector (100bps synchronization) 803 determines the parameter to be DDS synthesized from the 2FSK digital modulation signal input from the IO pin to be derived from the 0.915KHz register 801 or the 1.085KHz register 802.

The DDS synthesis 804 generates 1K + -85 Hz sine and cosine baseband signals according to the configuration parameters output by the selector (100bps synchronization) 803.

The DDS synthesis 805 generates up-converted sine and cosine signals of the corresponding frequency points according to the transmission frequency band register 809.

Multipliers 806 and 807 perform DUC up-conversion according to the output signals of the DDS synthesis 804 and DDS synthesis 805 to obtain orthogonal components corresponding to the transmission frequency band.

The outputs of the adder 808, multiplier 806 and multiplier 807 combine the final 2FSK modulated signal and load onto the transmit unit bus.

And the transmission frequency range register 809 is configured by the display control unit through a serial port and is used for setting a modulation frequency point of the NAVTEX modulation module.

With reference to the above description of the present invention, those skilled in the art can understand that the present invention has several advantages as follows:

the utility model provides a NAVTEX receiving system based on FPGA adopts FPGA to realize the demodulation of sampled signal and the modulation of self-checking signal, has very strong interference killing feature, can effectual reduction system complexity and cost from the circuit design of system, and the sensitivity of receipt also can keep higher uniformity.

The utility model provides a NAVTEX receiving system based on FPGA can realize the NAVTEX signal reception of the different frequency channels of multichannel on same hardware device to can carry out the configuration of arbitrary quantity and frequency channel to the receiving channel according to the practical application demand, have very strong flexibility, platform commonality and maintainability.

Although the invention has been illustrated and described herein with reference to specific examples, the invention is not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. It is appropriate, therefore, that the appended claims be construed broadly and in a manner consistent with the scope of the invention, as set forth in the following claims.

Claims

1. The utility model provides a NAVTEX receiving system based on FPGA, includes display control unit, power management module, transmitting element, receiving element, signal switching unit and FPGA signal processing unit, its characterized in that: the NAVTEX receiving antenna is connected with the signal switching unit, the signal switching unit is connected with the transmitting unit and the receiving unit, the signal switching unit is used for selecting radio frequency signals to be sampled, the NAVTEX receiving system is connected to the transmitting unit during self-checking, and the NAVTEX receiving system is switched to be connected to the NAVTEX receiving antenna during working;

the receiving unit is connected with the FPGA signal processing unit, and is used for carrying out radio frequency single-end to differential conversion on input signals and carrying out digital sampling on the signals;

2. The NAVTEX receiving system of claim 1, wherein the power management module comprises a DA power supply module for supplying power to the transmitting unit, an AD power supply module for supplying power to the receiving unit, and an FPGA power supply module for supplying power to the core 1.8V and pin 3.3V of the FPGA signal processing unit.

3. The NAVTEX receiving system of claim 1, wherein the transmitting unit comprises a DA unit and an attenuating unit; the DA unit generates an analog signal according to the modulated digital signal when the NAVTEX receiving system is started up and self-checked; the attenuation unit is used for attenuating the analog signal generated by the DA unit into a useful radio frequency signal so as to realize the detection of the function and the performance of the system.

4. The NAVTEX receiving system of claim 1, wherein the receiving unit includes a radio frequency conversion unit, an impedance matching unit, and an AD unit; the radio frequency conversion unit carries out differential conversion on the input single-ended radio frequency signal; the impedance matching unit matches the input impedance of the AD unit according to the frequency band of the input signal; and the AD unit is used for carrying out digital conversion on the differential radio frequency signal.

5. The NAVTEX receiving system of claim 1, wherein the signal switching unit comprises a protection unit, a band-pass filtering unit, and a relay; the protection unit carries out amplitude limiting on the radio frequency signal passing through the antenna, and prevents the system from being damaged by overlarge input signal; the band-pass filtering unit performs band-pass frequency selection on the radio-frequency signals input through the antenna, and prevents signals of other frequency bands from generating interference on a system; and the relay is used for switching and selecting signals to be sampled, is connected with the transmitting unit during self-checking and is connected with the output stage of the band-pass filtering unit during working.

6. The NAVTEX receiving system of claim 1, wherein the FPGA signal processing unit includes a NAVTEX demodulation module and a NAVTEX modulation module; the NAVTEX demodulation module is used for carrying out 2FSK demodulation on the digitized signal according to an algorithm and outputting a demodulated digital signal; and the NAVTEX modulation module generates a 2FSK analog signal of a designated frequency point according to the debugging digital signal.

7. The NAVTEX receiving system of claim 6, wherein the NAVTEX demodulation module comprises:

4 multipliers, wherein two multipliers are used for carrying out digital down-conversion on the sampling signals, and the other two multipliers are used for carrying out quadrature demodulation on the signals;

synthesizing 1 DDS for generating sine and cosine signals corresponding to demodulation frequency points;

2 CIC extraction for performing extraction filtering on the data after the digital down-conversion;

2 FIR band-pass filters are used for performing band-pass filtering on the signals extracted by the CIC to obtain baseband signals in the required corresponding frequency band;

2 time delay units for time delay and temporary storage of the signal after band-pass filtering;

1 adder, which is used to carry out quadrature demodulation to the signal after band-pass filtering;

1 synchronous decision, which is used to ensure the correctness and synchronism of the demodulated data;

1 clock frequency division for generating the clock required by the delayer by dividing the clock signal frequency;

and 1 receiving frequency range register for setting the demodulation frequency point of the NAVTEX demodulation module.

8. The NAVTEX receiving system of claim 6, wherein the NAVTEX modulating module comprises:

2 registers for temporarily storing DDS synthesis parameters corresponding to 0.915KHz and 1.085KHz respectively;

1 selector, according to digital modulation signal selecting needed DDS synthetic parameter;

2 DDSs are synthesized, wherein one DDS generates 1K +/-85 Hz sine and cosine baseband signals, and the other DDS generates up-conversion sine and cosine signals of corresponding frequency points;

2 multipliers, which are used for carrying out digital up-conversion on the baseband signals;

1 adder for synthesizing modulated signal;

and the 1 transmitting frequency range register is used for setting a modulation frequency point of the NAVTEX modulation module.