CN212135207U - Internet of things intelligent power supply detection and control circuit - Google Patents

Abstract

The utility model discloses an intelligent power supply detection and control circuit of the Internet of things, which comprises a circuit board, wherein the circuit board is provided with a MCU circuit, a reset circuit, a detection circuit, a power supply communication bus, a power supply separation circuit and a communication separation circuit; the reset circuit is connected with the MCU circuit and is used for being connected between the Internet of things equipment and the power supply in series; the detection circuit is connected with the MCU circuit and is used for being connected with a power supply; the MCU circuit is connected with a power supply communication bus, the power supply communication bus is used for being connected with an upper computer, the power supply separation circuit is connected between the power supply communication bus and the MCU circuit in series, and the communication separation circuit is connected between the power supply communication bus and the MCU circuit in series. The utility model discloses with power detection and reset circuit integration in a circuit board, can realize detecting and control function through once connecting, wiring when having reduced the use by a wide margin has improved deployment efficiency.

Description

Internet of things intelligent power supply detection and control circuit

Technical Field

The utility model belongs to thing networking equipment field especially relates to a thing networking intelligent power supply detects and control circuit.

Background

At present, the field devices of the internet of things are various, but no special module for detecting and controlling the direct-current power supply of the equipment of the internet of things is provided. In the prior art, a separate detection circuit is used for detecting the power supply, and a separate control module is used for controlling the power supply. For a non-proprietary power control module of the internet of things equipment, an IO module and a relay are integrated, the system complexity is high, and many of the modules do not have a detection function; and the relay generally adopts the general type, has extravagant terminal space and the fault point that the wiring point was many brought many.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to overcome the not enough of prior art, provide a thing networking intelligent power supply detects and control circuit.

The purpose of the utility model is realized through the following technical scheme: an intelligent power supply detection and control circuit of the Internet of things comprises a circuit board, wherein an MCU circuit, a reset circuit, a detection circuit, a power supply communication bus, a power supply separation circuit and a communication separation circuit are arranged on the circuit board; the reset circuit is connected with the MCU circuit and is used for being connected between the Internet of things equipment and the power supply in series; the detection circuit is connected with the MCU circuit and is used for being connected with a power supply; the MCU circuit is connected with a power supply communication bus, the power supply communication bus is used for being connected with an upper computer, the power supply separation circuit is connected between the power supply communication bus and the MCU circuit in series, and the communication separation circuit is connected between the power supply communication bus and the MCU circuit in series.

Preferably, the intelligent power supply detection and control circuit of the internet of things further comprises a display device, and the display device is connected with the MCU circuit.

Preferably, the display device includes a plurality of LED lamps having different emission colors.

Preferably, the MCU circuit comprises a single chip microcomputer, a monitoring chip, a first switching diode and a crystal oscillator, wherein the single chip microcomputer is of the model STM32F103C8T6, the monitoring chip is of the model MP706TESA, the switching diode is of the model BAW56, a BOOT0 pin of the single chip microcomputer is grounded via a first resistor, a VSSA pin of the single chip microcomputer is grounded, and a VDDA pin and a VBAT pin of the single chip microcomputer are connected to a first power supply; a first crystal oscillator pin of the single chip microcomputer is grounded through a first capacitor, a PD1/OSCOUT pin of the single chip microcomputer is grounded through a second capacitor, the first crystal oscillator pin of the single chip microcomputer is connected with a second crystal oscillator pin through a second resistor, the crystal oscillator is connected with the second resistor in parallel, a VDD pin of the single chip microcomputer is connected with a first power supply, the VDD pin of the single chip microcomputer is grounded through a third capacitor, a fourth capacitor and a fifth capacitor are both connected with the third capacitor in parallel, and a VSS pin of the single chip microcomputer is grounded; the PB10 pin of the single chip microcomputer is connected with a watchdog input pin of the monitoring chip, a signal ground pin and a power failure power supply monitoring input pin of the monitoring chip are both grounded, a power supply input pin of the monitoring chip is grounded through a sixth capacitor, a power supply input pin of the monitoring chip is connected with a first power supply, a manual reset input pin of the monitoring chip is connected with a watchdog output pin, a reset output pin of the monitoring chip is connected with a cathode of a first switching diode, and an anode of the first switching diode is connected with a reset pin of the single chip microcomputer; the first power supply is grounded through a seventh capacitor, and the eighth capacitor is connected with the seventh capacitor in parallel.

Preferably, the detection circuit comprises a first register, a second register, a first trigger inverter, a second trigger inverter, a first complementary transistor logic gate to a sixth complementary transistor logic gate, wherein the first register and the second register are of the model number SN74HC165DR, and the first trigger inverter and the second trigger inverter are of the model number 74HC 14;

SH of the first register

The pin is connected with a PB4 pin of the singlechip, an E pin and an F pin of a first register are grounded, a CLK pin of the first register is connected with a PA5 pin of the singlechip, a VCC pin of the first register is connected with a first power supply, GND pins of the first register and a second register are grounded, a SER pin of the first register is connected with a QH pin of the second register, a G pin of the first register is connected with an 8 th pin of a second trigger inverter, an H pin of the first register is connected with a10 th pin of the second trigger inverter, a U3QH pin of the first register is connected with a6 pin of the singlechip, an A pin of the first register is connected with a12 th pin of the first trigger inverter, a B pin of the first register is connected with a10 th pin of the first trigger inverter, a C pin of the first register is connected with an 8 th pin of the first trigger inverter, a D pin of the first register is connected with a12 th pin of the second trigger inverter, and an INH 2 pin of the first register is connected with the NI pin of the singlechip;

SH of a second register

The pin is connected with a PB4 pin of the singlechip, an E pin and an F pin of the second register are grounded, a CLK pin of the second register is connected with a PA5 pin of the singlechip, a VCC pin of the second register is grounded through an eighth capacitor C8, a VCC pin of the second register is connected with a first power supply, a SER pin of the second register is grounded, a G pin of the second register is connected with a6 th pin of the second trigger inverter, an H pin of the second register is connected with a4 th pin of the second trigger inverter, a pin A of the second register is connected with a2 nd pin of the first trigger inverter, a pin B of the second register is connected with a4 th pin of the first trigger inverter, a pin C of the second register is connected with a6 th pin of the first trigger inverter, a pin D of the second register is connected with a2 nd pin of the second trigger inverter, and an INH pin of the second register is connected with a PB2 pin of the singlechip;

the 7 th pin of the first trigger inverter is grounded, the 14 th pin of the first trigger inverter is grounded through a ninth capacitor, the 7 th pin of the second trigger inverter is grounded, and the 14 th pin of the second trigger inverter is grounded through a tenth capacitor;

the CTLIN pin of the first complementary transistor logic gate is connected with the PA8 pin of the singlechip, the G pin of the first complementary transistor logic gate is grounded, the POUTTTST pin of the first complementary transistor logic gate is connected with a first power supply through a third resistor, and the PINTST pin of the first complementary transistor logic gate is connected with the first power supply through a fourth resistor; the CTLIN pin of the logic gate of the second complementary transistor is connected with the PA9 pin of the singlechip, the G pin of the logic gate of the second complementary transistor is grounded, the POUTTTST pin of the logic gate of the second complementary transistor is connected with a first power supply through a fifth resistor, and the PINTST pin of the logic gate of the second complementary transistor is connected with the first power supply through a sixth resistor; the CTLIN pin of the logic gate of the third complementary transistor is connected with the PA10 pin of the singlechip, the G pin of the logic gate of the third complementary transistor is grounded, the POUTTTST pin of the logic gate of the third complementary transistor is connected with a first power supply through a seventh resistor, and the PINTST pin of the logic gate of the third complementary transistor is connected with the first power supply through an eighth resistor; the CTLIN pin of the fourth complementary transistor logic gate is connected with the PA11 pin of the singlechip, the G pin of the fourth complementary transistor logic gate is grounded, the POUTTTST pin of the fourth complementary transistor logic gate is connected with a first power supply through a ninth resistor, and the PINTST pin of the fourth complementary transistor logic gate is connected with the first power supply through a tenth resistor; the CTLIN pin of the fifth complementary transistor logic gate is connected with the PA12 pin of the singlechip, the G pin of the fifth complementary transistor logic gate is grounded, the POUTTTST pin of the fifth complementary transistor logic gate is connected with a first power supply through an eleventh resistor, and the PINTST pin of the fifth complementary transistor logic gate is connected with the first power supply through a twelfth resistor; the CTLIN pin of the sixth complementary transistor logic gate is connected with the PA15 pin of the singlechip, the G pin of the sixth complementary transistor logic gate is grounded, the POUTTTST pin of the sixth complementary transistor logic gate is connected with the first power supply through the thirteenth resistor, and the PINTST pin of the sixth complementary transistor logic gate is connected with the first power supply through the fourteenth resistor.

Preferably, the reset circuit mainly comprises a relay, a first transistor coupler, a second transistor coupler, a third transistor coupler, a first rectifier bridge and a second switching diode, the model of the relay is HHJR4102E-L-5VDC-S-Z, the models of the first transistor coupler, the second transistor coupler and the third transistor coupler are TLP290, the model of the first rectifier bridge is MB6S _600V/0.5A, and the model of the second switching diode is BAW 56; a1 st pin of the first transistor coupler is connected with a CTLIN pin of a complementary transistor logic gate through a fifteenth resistor, a2 nd pin of the first transistor coupler is connected with a G pin of a register, a3 rd pin of the first transistor coupler is connected with a base electrode of a first triode, a3 rd pin of the first transistor coupler is connected with an emitting electrode of the first triode through a sixteenth resistor, a4 th pin of the first transistor coupler is connected with a3 rd pin of a first rectifier bridge through a seventeenth resistor, a collector electrode of the first triode is connected with a3 rd pin of a second switching diode, the 1 st pin and the 2 nd pin of the second switching diode are both connected with a1 st pin of a relay, the collector electrode of the first triode is connected with a2 nd pin of the relay, and the 1 st pin of the relay is connected with a second power supply; a pin 4 of the second transistor coupler is connected with a PINTST pin of a complementary transistor logic gate, a pin 3 of the second transistor coupler is connected with a pin G of the register, a pin 2 of the second transistor coupler is connected with a pin 2 of the first rectifier bridge, and a pin 1 of the second transistor coupler is connected with a pin 5 of the relay through an eighteenth resistor; a pin 4 of the third transistor coupler is connected with a POUTTST pin of the complementary transistor logic gate, a pin 3 of the third transistor coupler is connected with a pin G of the register, a pin 2 of the third transistor coupler is connected with a pin 2 of the first rectifier bridge, and a pin 1 of the third transistor coupler is connected with a pin 4 of the relay through a nineteenth resistor; the 1 st pin of the first rectifier bridge is connected with the 5 th pin of the relay, the 3 rd pin of the first rectifier bridge is connected with the 4 th pin of the first rectifier bridge through an eleventh capacitor, and the 4 th pin of the first rectifier bridge is connected with an emitting electrode of the first triode; the emitter of the second triode is connected with the second power supply, the base of the second triode is connected with the collector of the second triode through a twentieth resistor, the base of the second triode is connected with the anode of the first voltage stabilizing diode through a twelfth capacitor, and the pin of the first voltage stabilizing diode is connected with the base of the second triode.

Preferably, the power supply separation circuit comprises a bus control chip, a second rectifier bridge, a third switch diode and a fourth switch diode, the type of the bus control chip is LCU201PS, the type of the second rectifier bridge is MB6S _600V/0.5A, the types of the third switch diode and the fourth switch diode are BAV99, a TXD pin of the bus control chip is connected with a PA3 pin of the single chip microcomputer, an RXD pin of the bus control chip is connected with a PA2 pin of the single chip microcomputer, a PA8 pin of an nRST pin of the bus control chip, a WDT pin of the bus control chip is connected with a PA7 pin of the single chip microcomputer, a GND pin of the bus control chip is grounded, a SYNC pin of the bus control chip 1 is connected with a PC13/TAMPER _ RTC pin of the single chip microcomputer, a Vcore pin of the bus control chip is grounded through a third capacitor, a VBUS pin of the bus control chip is grounded through a fourteenth capacitor, and a VBUS pin of the bus control chip is connected with a third, the SET pin of the bus control chip is connected with the PA0 pin of the singlechip, the DSR pin of the bus control chip is connected with the PA4 pin of the singlechip, the SIGNAL pin of the bus control chip is connected with the anode of the second voltage stabilizing diode, the 3 rd pin of the second rectifier bridge, the 1 st pin of the third switching diode and the 1 st pin of the fourth switching diode, the pin of the second voltage stabilizing diode is connected with the fourth power supply, the 4 th pin of the second rectifier bridge is grounded, the 1 st pin of the second rectifier bridge is connected with the 2 nd pin of the second rectifier bridge through the bidirectional diode, the 2 nd pin of the third switching diode is connected with the fourth power supply, the 3 rd pin of the third switching diode is connected with the 2 nd pin of the second rectifier bridge through a fifteenth capacitor, the 2 nd pin of the fourth switching diode is connected with the fourth power supply, and the 3 rd pin of the fourth switching diode is connected with the 1 st pin of the second rectifier bridge through a sixteenth capacitor;

the communication separation circuit comprises a voltage converter and a voltage regulator, wherein the model of the voltage converter is PS54202DDC, and the model of the voltage regulator is LM1117 IMPX-33; the fourth power supply is connected with the anode of the seventeenth capacitor, the cathode of the seventeenth capacitor is grounded, the GND pin of the voltage converter is grounded, the VIN pin of the voltage converter is connected with the EN pin through the twenty-first resistor, the VIN pin of the voltage converter is grounded through the eighteenth capacitor, the EN pin of the voltage converter is grounded through the twenty-second resistor, the BOOT pin of the voltage converter is connected with the SW pin through the nineteenth capacitor, the SW pin of the voltage converter is connected with the IN pin of the voltage regulator through the first inductor, the FB pin of the voltage converter is connected with the IN pin of the voltage regulator through the twenty-third resistor, the FB pin of the voltage converter is grounded through the twenty-fourth resistor, the IN pin of the voltage regulator is grounded through the twentieth capacitor, the GND pin of the voltage regulator is grounded, the OUT pin of the voltage regulator is connected with the first power supply, the OUT pin of the voltage regulator is grounded.

The utility model has the advantages that:

(1) the utility model integrates the power detection and reset circuit into one circuit board, and can realize the detection and control functions through one-time connection, thereby greatly reducing the wiring during use and improving the deployment efficiency;

(2) the utility model adopts the power supply communication bus, realizes one-time connection, uses power supply and communication simultaneously, and simplifies the power supply of the MCU circuit;

(3) the utility model discloses in be equipped with display device, convenience of customers knows the testing result fast, accurately.

Drawings

FIG. 1 is a block diagram of an intelligent power supply detection and control circuit of the Internet of things;

FIG. 2 is a schematic circuit diagram of the MCU circuit;

FIG. 3 is a circuit schematic of a first register and a second register in the detection circuit;

FIG. 4 is a circuit schematic of a first flip-flop inverter and a second flip-flop inverter in the detection circuit;

FIG. 5 is a schematic circuit diagram of the first to sixth complementary transistor logic gates of the detection circuit;

FIG. 6 is a schematic diagram of a circuit of the relay in the reset circuit;

FIG. 7 is a schematic circuit diagram of a first rectifier bridge in the reset circuit;

FIG. 8 is a circuit schematic of a power splitting circuit;

fig. 9 is a circuit diagram of a communication separation circuit.

Detailed Description

The technical solution of the present invention will be described clearly and completely with reference to the following embodiments, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present invention.

Referring to fig. 1-9, the present embodiment provides an intelligent power supply detection and control circuit for internet of things:

as shown in fig. 1, the intelligent power supply detection and control circuit for the internet of things comprises a circuit board, wherein an MCU circuit, a reset circuit, a detection circuit, a power supply communication bus, a power supply separation circuit and a communication separation circuit are arranged on the circuit board. The reset circuit and the detection circuit are both connected to the MCU circuit; the reset circuit is also used for being connected in series between the Internet of things equipment and the power supply and executing reset operation according to a second reset signal of the MCU circuit; the detection circuit is used for being connected between the Internet of things equipment and the power supply, detecting current signals output to the Internet of things equipment by the power supply, for example, detecting whether the power supply has current output, current value, voltage value and the like, and transmitting a detection result to the MCU circuit; the MCU circuit is also used for being connected with the upper computer, sending a second reset signal to the reset circuit according to the first reset signal sent by the upper computer, and sending the detection result of the detection circuit to the upper computer.

The power supply communication bus is connected with the MCU circuit and is used for being connected with the upper computer; the power supply separation circuit is connected in series between the power supply communication bus and the MCU circuit and is used for identifying a power supply signal from signals output by the power supply communication bus and supplying power to the MCU circuit; the communication separation circuit is connected in series between the power supply communication bus and the MCU circuit and is used for identifying a communication signal from signals output by the power supply communication bus, converting the communication signal into a signal which can be identified by the MCU circuit and sending the converted signal to the MCU circuit; and the detection circuit is used for driving the power supply communication bus to send a detection result of the detection circuit to the upper computer.

The power supply detection and reset circuit is integrated in one circuit board, the detection and control functions can be realized through one-time connection, wiring in use is greatly reduced, and deployment efficiency is improved. Meanwhile, a power supply communication bus is adopted, one-time connection is realized, power supply and communication are used simultaneously, and the power supply of the MCU circuit is simplified.

In some embodiments, as shown in fig. 2, the MCU circuit includes a single chip microcomputer U1, a monitoring chip U2, a first switch diode D1 and a crystal oscillator X1, the model of the single chip microcomputer U1 is STM32F103C8T6, the model of the monitoring chip U2 is MP706TESA, the model of the switch diode D1 is BAW56, a BOOT0 pin of the single chip microcomputer U1 is grounded through a first resistor R1, a VSSA pin of the single chip microcomputer U1 is grounded, and a VDDA pin and a VBAT pin of the single chip microcomputer U1 are connected to a first VDD; a PD0/OSCIN pin of the singlechip U1 is grounded through a first capacitor C1, a PD1/OSCOUT pin of the singlechip U1 is grounded through a second capacitor C2, a PD0/OSCIN pin of the singlechip U1 is connected with a PD1/OSCOUT pin through a second resistor R2, a crystal oscillator X1 is connected with the second resistor R2 in parallel, a VDD pin of the singlechip U1 is connected with a first power supply VDD, a VDD pin of the singlechip U1 is grounded through a third capacitor C3, a fourth capacitor C4 and a fifth capacitor C5 are connected with the third capacitor C3 in parallel, and a VSS pin of the singlechip U1 is grounded; a PB10 pin of the singlechip U1 is connected with a WDI pin of the monitoring chip U2, a GND pin and a PFI pin of the monitoring chip U2 are both grounded, a VCC pin of the monitoring chip U2 is grounded through a sixth capacitor C6, a VCC pin of the monitoring chip U2 is connected with a first power supply VDD, an nMR pin of the monitoring chip U2 is connected with an nWDO pin, an nRESET pin of the monitoring chip U2 is connected with a cathode of a first switch diode D1, and an anode of the first switch diode D1 is connected with an nRST pin of the singlechip U1; the first power source VDD is grounded through the seventh capacitor C7, and the eighth capacitor C8 is connected in parallel with the seventh capacitor C7.

As shown in fig. 3, 4 and 5, the detection circuit mainly includes a first register U3, a second register U4, a first triggered inverter U5, a second triggered inverter U6, a first complementary transistor logic gate CTL1 to a sixth complementary transistor logic gate CTL6, the first register U3 and the second register U4 are model numbers SN74HC165DR, and the first triggered inverter U5 and the second triggered inverter U6 are model numbers 74HC 14.

First registerSH/of device U3

The PB4 pin of the pin-connected singlechip U1, the E pin and the F pin of the first register U3 are grounded, the CLK pin of the first register U3 is connected with the PA5 pin of the singlechip U1, the VCC pin of the first register U3 is connected with the first power VDD, the GND pins of the first register U3 and the second register U4 are grounded, the SER pin of the first register U3 is connected with the QH pin of the second register U4, the G pin of the first register U3 is connected with the 8 th pin of the second trigger inverter U6, the H pin of the first register U3 is connected with the 10 th pin of the second trigger inverter U6, the B pin of the first register U3 is connected with the PA6 pin of the singlechip U1, the A pin of the first register U3 is connected with the 12 th pin of the first trigger inverter U5, the B pin of the first register U5 is connected with the first trigger inverter U5 pin of the B5, the first register U5 pin 5 is connected with the first trigger inverter U5, the INH pin of the first register U3 is connected with the PB2 pin of the singlechip U1.

SH ^ of the second register U4

The pin is connected with a PB4 pin of a singlechip U1, a pin E and a pin F of a second register U4 are grounded, a pin CLK of the second register U4 is connected with a pin PA5 of the singlechip U1, a pin VCC of the second register U4 is grounded through an eighth capacitor C8, a pin VCC of the second register U4 is connected with a first power VDD, a pin SER of the second register U4 is grounded, a pin G of the second register U4 is connected with a pin 6 of a second trigger inverter U6, a pin H of the second register U4 is connected with a pin 4 of the second trigger inverter U6, a pin A of the second register U4 is connected with a pin 2 of a first trigger inverter U5, a pin B of the second register U4 is connected with a pin 4 of the first trigger inverter U5, a pin C of the second register U4 is connected with a pin PB 6 of the first trigger inverter U5, a pin D of the second register U4 is connected with a pin INH 7 of the second trigger inverter U6, and a pin INH 72 of the singlechip U2.

The 7 th pin of the first trigger inverter U5 is grounded, the 14 th pin of the first trigger inverter U5 is grounded through a ninth capacitor C9, the 7 th pin of the second trigger inverter U6 is grounded, and the 14 th pin of the second trigger inverter U6 is grounded through a tenth capacitor C10.

The ctln pin of the first complementary transistor logic gate CTL1 is connected to the PA8 pin of the monolithic computer U1, the G pin of the first complementary transistor logic gate CTL1 is grounded, the pouttst pin of the first complementary transistor logic gate CTL1 is connected to the first power supply VDD through the third resistor R3, and the PINTST pin of the first complementary transistor logic gate CTL1 is connected to the first power supply VDD through the fourth resistor R4. The ctln pin of the second complementary transistor logic gate CTL2 is connected to the PA9 pin of the monolithic computer U1, the G pin of the second complementary transistor logic gate CTL2 is grounded, the pouttst pin of the second complementary transistor logic gate CTL2 is connected to the first power supply VDD through the fifth resistor R5, and the PINTST pin of the second complementary transistor logic gate CTL2 is connected to the first power supply VDD through the sixth resistor R6. The ctln pin of the third complementary transistor logic gate CTL3 is connected to the PA10 pin of the monolithic computer U1, the G pin of the third complementary transistor logic gate CTL3 is grounded, the pouttst pin of the third complementary transistor logic gate CTL3 is connected to the first power supply VDD through the seventh resistor R7, and the PINTST pin of the third complementary transistor logic gate CTL3 is connected to the first power supply VDD through the eighth resistor R8. The ctln pin of the fourth complementary transistor logic gate CTL4 is connected to the PA11 pin of the monolithic computer U1, the G pin of the fourth complementary transistor logic gate CTL4 is grounded, the pouttst pin of the fourth complementary transistor logic gate CTL4 is connected to the first power supply VDD through the ninth resistor R9, and the PINTST pin of the fourth complementary transistor logic gate CTL4 is connected to the first power supply VDD through the tenth resistor R10. The ctln pin of the fifth complementary transistor logic gate CTL5 is connected to the PA12 pin of the monolithic computer U1, the G pin of the fifth complementary transistor logic gate CTL5 is grounded, the pouttst pin of the fifth complementary transistor logic gate CTL5 is connected to the first power supply VDD through the eleventh resistor R11, and the PINTST pin of the fifth complementary transistor logic gate CTL5 is connected to the first power supply VDD through the twelfth resistor R12. The ctln pin of the sixth complementary transistor logic gate CTL6 is connected to the PA15 pin of the monolithic computer U1, the G pin of the sixth complementary transistor logic gate CTL6 is grounded, the pouttst pin of the sixth complementary transistor logic gate CTL6 is connected to the first power supply VDD through the thirteenth resistor R13, and the PINTST pin of the sixth complementary transistor logic gate CTL6 is connected to the first power supply VDD through the fourteenth resistor R14.

The reset circuit may include multiple paths, and this embodiment takes one path as an example for description. As shown in fig. 6 and 7, the reset circuit mainly includes a relay U7, a first transistor coupler U8, a second transistor coupler U9, a third transistor coupler U10, a first rectifier bridge D2 and a second switching diode D3, the model of the relay U7 is HJR4102E-L-5VDC-S-Z, the models of the first transistor coupler U8, the second transistor coupler U9 and the third transistor coupler U10 are TLP290, the model of the first rectifier bridge D2 is MB6S _600V/0.5A, and the model of the second switching diode D3 is BAW 56. A1 st pin of the first transistor coupler U8 is connected to a ctln pin of the complementary transistor logic gate through a fifteenth resistor R15, a2 nd pin of the first transistor coupler U8 is connected to a G pin of the register, a3 rd pin of the first transistor coupler U8 is connected to a base of a first triode Q1 (the model of the first triode Q1 is MMBT 2222), a3 rd pin of the first transistor coupler U8 is connected to an emitter of a first triode Q1 through a sixteenth resistor R16, a4 th pin of the first transistor coupler U8 is connected to a3 rd pin of a first rectifier bridge D2 through a seventeenth resistor R17, a collector of the first triode Q1 is connected to a3 rd pin of a second switching diode D3, the 1 st pin and the 2 nd pin of the second switching diode D3 are both connected to a1 st pin of a relay U7, a collector of the first triode Q1 is connected to a2 nd pin of an electrical relay U7, and the second pin VCC 1 st pin of the relay U7 is connected to a second electrical source. The 4 th pin of the second transistor coupler U9 is connected with the PINTST pin of the complementary transistor logic gate, the 3 rd pin of the second transistor coupler U9 is connected with the G pin of the register, the 2 nd pin of the second transistor coupler U9 is connected with the 2 nd pin of the first rectifier bridge D2, and the 1 st pin of the second transistor coupler U9 is connected with the 5 th pin of the relay U7 through an eighteenth resistor R18. The 4 th pin of the third transistor coupler U10 is connected to the POUTTST pin of the complementary transistor logic gate, the 3 rd pin of the third transistor coupler U10 is connected to the G pin of the register, the 2 nd pin of the third transistor coupler U10 is connected to the 2 nd pin of the first rectifier bridge D2, and the 1 st pin of the third transistor coupler U10 is connected to the 4 th pin of the relay U7 via a nineteenth resistor R19. The 1 st pin of the first rectifier bridge D2 is connected with the 5 th pin of the relay U7, the 3 rd pin of the first rectifier bridge D2 is connected with the 4 th pin thereof through an eleventh capacitor C11, and the 4 th pin of the first rectifier bridge D2 is connected with the emitter of a first triode Q1. An emitting electrode of the second triode Q2 is connected with a second power VCC (the model of the second triode Q2 is 2SD 1000), a base electrode of the second triode Q2 is connected with a collector electrode of the second triode Q3526 through a twentieth resistor R20, a base electrode of the second triode Q2 is connected with an anode electrode of a first voltage stabilizing diode D4 through a twelfth capacitor C12, and a pin of the first voltage stabilizing diode D4 is connected with a base electrode of the second triode Q2.

In some embodiments, as shown in fig. 8, the power splitting circuit includes a bus control chip U11, a second rectifier bridge D5, a third switch diode D6, and a fourth switch diode D7, the bus control chip U11 is of the type LCU201PS, the second rectifier bridge D5 is of the type MB6S _600V/0.5A, the third switch diode D6 and the fourth switch diode D7 are of the type BAV99, the TXD pin of the bus control chip U11 is connected to the PA1 pin of the monolithic chip U1, the RXD pin of the bus control chip U1 is connected to the PA1 pin of the monolithic chip U1, the nRST pin of the monolithic chip U1 of the bus control chip U1 is connected to the PA1 pin of the monolithic chip U1, the WDT pin of the bus control chip U1 is connected to the PA1 pin of the monolithic chip U1, the bus control chip U1 is connected to ground, the mpu 72 pin of the PC chip U1 is connected to the ground, the vcer pin of the RTC pin of the monolithic chip 72 is connected to the bus control chip vcer 1, the VBUS pin of the bus control chip U11 is grounded through a fourteenth capacitor C14, the VBUS pin of the bus control chip U11 is connected with a third power supply V _ LC, the SET pin of the bus control chip U11 is connected with the PA0 pin of the singlechip U1, the DSR pin of the bus control chip U11 is connected with the PA4 pin of the singlechip U1, the SIGNAL pin of the bus control chip U11 is connected with the anode of the second zener diode D8, the 3 rd pin of the second rectifier bridge D5, the 1 st pin of the third switching diode D6 and the 1 st pin of the fourth switching diode D7, the pin of the second zener diode D8 is connected with the fourth power supply V _ USE, the 4 th pin of the second rectifier bridge D5 is grounded, the 1 st pin of the second rectifier bridge D5 is connected with the 2 nd pin of the bidirectional diode Z1, the 2 nd pin of the third diode D6 is connected with the fourth power supply V _ USE, the fifteenth pin 583D 5732C 24 of the fourth rectifier bridge D15, the 2 nd pin of the fourth switching diode D7 is connected to the fourth power supply V _ USE, and the 3 rd pin of the fourth switching diode D7 is connected to the 1 st pin of the second rectifier bridge D5 through a sixteenth capacitor C16.

In some embodiments, as shown in fig. 9, the communication splitting circuit includes a voltage converter U12 and a voltage regulator U13, the voltage converter U12 is model PS54202DDC, and the voltage regulator U13 is model LM1117 IMPX-33. The fourth power supply V _ USE is connected with the anode of a seventeenth capacitor C17, the cathode of the seventeenth capacitor C17 is grounded, the GND pin of a voltage converter U12 is grounded, the VIN pin of the voltage converter U12 is connected with the EN pin through a twenty-first R21 resistor, the VIN pin of the voltage converter U12 is grounded through an eighteenth capacitor C18, the EN pin of a voltage converter U12 is grounded through a twenty-second resistor R22, the BOOT pin of the voltage converter U12 is connected with the SW pin through a nineteenth capacitor C19, the SW pin of the voltage converter U12 is connected with the IN pin of a voltage regulator U13 through a first inductor L1, the FB pin of the voltage converter U12 is connected with the IN pin of a voltage regulator U23 through a twenty-third resistor R23, the FB pin of the voltage converter U12 is grounded through a twenty-fourth resistor R24, the IN pin of the voltage regulator U13 is grounded through a twenty-capacitor C20, the IN pin of the voltage regulator U13 is connected with the first power supply pin, the GND, the OUT pin of the voltage regulator U13 is connected to the first power supply VDD, the OUT pin of the voltage regulator U13 is connected to ground through a twenty-first capacitor C21, and the TAB pin of the voltage regulator U13 is connected to the first power supply VDD.

In some embodiments, thing networking intelligence power supply detects and control circuit still includes display device, display device connects in the MCU circuit for show detection circuit's testing result, display device includes a plurality of different LED lamps of luminous colour, and the user of being convenient for knows the detection condition fast, accurately.

The foregoing is illustrative of the preferred embodiments of the present invention, and it is to be understood that the invention is not limited to the precise forms disclosed herein, and that various other combinations, modifications, and environments may be resorted to, falling within the scope of the invention as defined by the appended claims. But that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention, which is to be limited only by the claims appended hereto.

Claims (7)

1. An intelligent power supply detection and control circuit of the Internet of things is characterized by comprising a circuit board, wherein an MCU circuit, a reset circuit, a detection circuit, a power supply communication bus, a power supply separation circuit and a communication separation circuit are arranged on the circuit board; the reset circuit is connected with the MCU circuit and is used for being connected between the Internet of things equipment and the power supply in series; the detection circuit is connected with the MCU circuit and is used for being connected with a power supply; the MCU circuit is connected with a power supply communication bus, the power supply communication bus is used for being connected with an upper computer, the power supply separation circuit is connected between the power supply communication bus and the MCU circuit in series, and the communication separation circuit is connected between the power supply communication bus and the MCU circuit in series.

2. The Internet of things intelligent power supply detection and control circuit of claim 1, further comprising a display device, wherein the display device is in circuit connection with the MCU.

3. The Internet of things intelligent power supply detection and control circuit according to claim 2, wherein the display device comprises a plurality of LED lamps with different light emitting colors.

4. The Internet of things intelligent power supply detection and control circuit according to claim 1, wherein the MCU circuit comprises a single chip microcomputer, a monitoring chip, a first switch diode and a crystal oscillator, the model of the single chip microcomputer is STM32F103C8T6, the model of the monitoring chip is MP706TESA, the model of the switch diode is BAW56, a BOOT0 pin of the single chip microcomputer is grounded through a first resistor, a VSSA pin of the single chip microcomputer is grounded, and a VDDA pin and a VBAT pin of the single chip microcomputer are connected with a first power supply; a first crystal oscillator pin of the single chip microcomputer is grounded through a first capacitor, a PD1/OSCOUT pin of the single chip microcomputer is grounded through a second capacitor, the first crystal oscillator pin of the single chip microcomputer is connected with a second crystal oscillator pin through a second resistor, the crystal oscillator is connected with the second resistor in parallel, a VDD pin of the single chip microcomputer is connected with a first power supply, the VDD pin of the single chip microcomputer is grounded through a third capacitor, a fourth capacitor and a fifth capacitor are both connected with the third capacitor in parallel, and a VSS pin of the single chip microcomputer is grounded; the PB10 pin of the single chip microcomputer is connected with a watchdog input pin of the monitoring chip, a signal ground pin and a power failure power supply monitoring input pin of the monitoring chip are both grounded, a power supply input pin of the monitoring chip is grounded through a sixth capacitor, a power supply input pin of the monitoring chip is connected with a first power supply, a manual reset input pin of the monitoring chip is connected with a watchdog output pin, a reset output pin of the monitoring chip is connected with a cathode of a first switching diode, and an anode of the first switching diode is connected with a reset pin of the single chip microcomputer; the first power supply is grounded through a seventh capacitor, and the eighth capacitor is connected with the seventh capacitor in parallel.

5. The Internet of things intelligent power supply detection and control circuit as claimed in claim 4, wherein the detection circuit comprises a first register, a second register, a first trigger inverter, a second trigger inverter, a first complementary transistor logic gate to a sixth complementary transistor logic gate, the first register and the second register are SN74HC165DR, and the first trigger inverter and the second trigger inverter are 74HC 14;

SH of the first register

The pin is connected with a PB4 pin of the singlechip, an E pin and an F pin of the first register are grounded, a CLK pin of the first register is connected with a PA5 pin of the singlechip, a VCC pin of the first register is connected with a first power supply, GND pins of the first register and the second register are grounded, a SER pin of the first register is connected with a QH pin of the second register, a G pin of the first register is connected with an 8 th pin of the second trigger inverter, an H pin of the first register is connected with a10 th pin of the second trigger inverter, a U3QH pin of the first register is connected with a PA6 pin of the singlechip, an A pin of the first register is connected with a12 th pin of the first trigger inverter, a B pin of the first register is connected with a10 th pin of the first trigger inverter, and a C pin of the first register is connected with a first trigger inverterThe 8 th pin of the phase device, the D pin of the first register is connected with the 12 th pin of the second trigger phase inverter, and the INH pin of the first register is connected with the PB2 pin of the single chip microcomputer;

SH of a second register

The pin is connected with a PB4 pin of the singlechip, an E pin and an F pin of the second register are grounded, a CLK pin of the second register is connected with a PA5 pin of the singlechip, a VCC pin of the second register is grounded through an eighth capacitor C8, a VCC pin of the second register is connected with a first power supply, a SER pin of the second register is grounded, a G pin of the second register is connected with a6 th pin of the second trigger inverter, an H pin of the second register is connected with a4 th pin of the second trigger inverter, a pin A of the second register is connected with a2 nd pin of the first trigger inverter, a pin B of the second register is connected with a4 th pin of the first trigger inverter, a pin C of the second register is connected with a6 th pin of the first trigger inverter, a pin D of the second register is connected with a2 nd pin of the second trigger inverter, and an INH pin of the second register is connected with a PB2 pin of the singlechip;

the 7 th pin of the first trigger inverter is grounded, the 14 th pin of the first trigger inverter is grounded through a ninth capacitor, the 7 th pin of the second trigger inverter is grounded, and the 14 th pin of the second trigger inverter is grounded through a tenth capacitor;

the CTLIN pin of the first complementary transistor logic gate is connected with the PA8 pin of the singlechip, the G pin of the first complementary transistor logic gate is grounded, the POUTTTST pin of the first complementary transistor logic gate is connected with a first power supply through a third resistor, and the PINTST pin of the first complementary transistor logic gate is connected with the first power supply through a fourth resistor; the CTLIN pin of the logic gate of the second complementary transistor is connected with the PA9 pin of the singlechip, the G pin of the logic gate of the second complementary transistor is grounded, the POUTTTST pin of the logic gate of the second complementary transistor is connected with a first power supply through a fifth resistor, and the PINTST pin of the logic gate of the second complementary transistor is connected with the first power supply through a sixth resistor; the CTLIN pin of the logic gate of the third complementary transistor is connected with the PA10 pin of the singlechip, the G pin of the logic gate of the third complementary transistor is grounded, the POUTTTST pin of the logic gate of the third complementary transistor is connected with a first power supply through a seventh resistor, and the PINTST pin of the logic gate of the third complementary transistor is connected with the first power supply through an eighth resistor; the CTLIN pin of the fourth complementary transistor logic gate is connected with the PA11 pin of the singlechip, the G pin of the fourth complementary transistor logic gate is grounded, the POUTTTST pin of the fourth complementary transistor logic gate is connected with a first power supply through a ninth resistor, and the PINTST pin of the fourth complementary transistor logic gate is connected with the first power supply through a tenth resistor; the CTLIN pin of the fifth complementary transistor logic gate is connected with the PA12 pin of the singlechip, the G pin of the fifth complementary transistor logic gate is grounded, the POUTTTST pin of the fifth complementary transistor logic gate is connected with a first power supply through an eleventh resistor, and the PINTST pin of the fifth complementary transistor logic gate is connected with the first power supply through a twelfth resistor; the CTLIN pin of the sixth complementary transistor logic gate is connected with the PA15 pin of the singlechip, the G pin of the sixth complementary transistor logic gate is grounded, the POUTTTST pin of the sixth complementary transistor logic gate is connected with the first power supply through the thirteenth resistor, and the PINTST pin of the sixth complementary transistor logic gate is connected with the first power supply through the fourteenth resistor.

6. The Internet of things intelligent power supply detection and control circuit according to claim 5, wherein the reset circuit mainly comprises a relay, a first transistor coupler, a second transistor coupler, a third transistor coupler, a first rectifier bridge and a second switching diode, the model of the relay is HHJR4102E-L-5VDC-S-Z, the models of the first transistor coupler, the second transistor coupler and the third transistor coupler are TLP290, the model of the first rectifier bridge is MB6S _600V/0.5A, and the model of the second switching diode is BAW 56; a1 st pin of the first transistor coupler is connected with a CTLIN pin of a complementary transistor logic gate through a fifteenth resistor, a2 nd pin of the first transistor coupler is connected with a G pin of a register, a3 rd pin of the first transistor coupler is connected with a base electrode of a first triode, a3 rd pin of the first transistor coupler is connected with an emitting electrode of the first triode through a sixteenth resistor, a4 th pin of the first transistor coupler is connected with a3 rd pin of a first rectifier bridge through a seventeenth resistor, a collector electrode of the first triode is connected with a3 rd pin of a second switching diode, the 1 st pin and the 2 nd pin of the second switching diode are both connected with a1 st pin of a relay, the collector electrode of the first triode is connected with a2 nd pin of the relay, and the 1 st pin of the relay is connected with a second power supply; a pin 4 of the second transistor coupler is connected with a PINTST pin of a complementary transistor logic gate, a pin 3 of the second transistor coupler is connected with a pin G of the register, a pin 2 of the second transistor coupler is connected with a pin 2 of the first rectifier bridge, and a pin 1 of the second transistor coupler is connected with a pin 5 of the relay through an eighteenth resistor; a pin 4 of the third transistor coupler is connected with a POUTTST pin of the complementary transistor logic gate, a pin 3 of the third transistor coupler is connected with a pin G of the register, a pin 2 of the third transistor coupler is connected with a pin 2 of the first rectifier bridge, and a pin 1 of the third transistor coupler is connected with a pin 4 of the relay through a nineteenth resistor; the 1 st pin of the first rectifier bridge is connected with the 5 th pin of the relay, the 3 rd pin of the first rectifier bridge is connected with the 4 th pin of the first rectifier bridge through an eleventh capacitor, and the 4 th pin of the first rectifier bridge is connected with an emitting electrode of the first triode; the emitter of the second triode is connected with the second power supply, the base of the second triode is connected with the collector of the second triode through a twentieth resistor, the base of the second triode is connected with the anode of the first voltage stabilizing diode through a twelfth capacitor, and the pin of the first voltage stabilizing diode is connected with the base of the second triode.

7. The Internet of things intelligent power supply detection and control circuit as claimed in claim 6, wherein the power supply separation circuit comprises a bus control chip, a second rectifier bridge, a third switch diode and a fourth switch diode, the bus control chip is of the type LCU201PS, the second rectifier bridge is of the type MB6S _600V/0.5A, the third switch diode and the fourth switch diode are of the type BAV99, a TXD pin of the bus control chip is connected with a PA3 pin of the singlechip, an RXD pin of the bus control chip is connected with a PA2 pin of the singlechip, a RST pin of the bus control chip is 8 pin of the singlechip, a WDT pin of the bus control chip is connected with a PA7 pin of the singlechip, a GND pin of the bus control chip is grounded, a SYNC pin of the bus control chip 1 is connected with a PC13/TAMPER _ RTC pin of the singlechip, a Vcore pin of the bus control chip is grounded through a thirteenth capacitor, the VBUS pin of the bus control chip is grounded through a fourteenth capacitor, the VBUS pin of the bus control chip is connected with a third power supply, the SET pin of the bus control chip is connected with the PA0 pin of the single chip microcomputer, the DSR pin of the bus control chip is connected with the PA4 pin of the single chip microcomputer, the SIGNAL pin of the bus control chip is connected with the anode of the second voltage stabilizing diode and the 3 rd pin of the second rectifier bridge, the 1 st pin of a third switching diode and the 1 st pin of a fourth switching diode, the pin of a second voltage stabilizing diode is connected with a fourth power supply, the 4 th pin of a second rectifier bridge is grounded, the 1 st pin of the second rectifier bridge is connected with the 2 nd pin of the second rectifier bridge through a bidirectional diode, the 2 nd pin of the third switching diode is connected with the fourth power supply, the 3 rd pin of the third switching diode is connected with the 2 nd pin of the second rectifier bridge through a fifteenth capacitor, the 2 nd pin of the fourth switching diode is connected with the fourth power supply, and the 3 rd pin of the fourth switching diode is connected with the 1 st pin of the second rectifier bridge through a sixteenth capacitor;

the communication separation circuit comprises a voltage converter and a voltage regulator, wherein the model of the voltage converter is PS54202DDC, and the model of the voltage regulator is LM1117 IMPX-33; the fourth power supply is connected with the anode of the seventeenth capacitor, the cathode of the seventeenth capacitor is grounded, the GND pin of the voltage converter is grounded, the VIN pin of the voltage converter is connected with the EN pin through the twenty-first resistor, the VIN pin of the voltage converter is grounded through the eighteenth capacitor, the EN pin of the voltage converter is grounded through the twenty-second resistor, the BOOT pin of the voltage converter is connected with the SW pin through the nineteenth capacitor, the SW pin of the voltage converter is connected with the IN pin of the voltage regulator through the first inductor, the FB pin of the voltage converter is connected with the IN pin of the voltage regulator through the twenty-third resistor, the FB pin of the voltage converter is grounded through the twenty-fourth resistor, the IN pin of the voltage regulator is grounded through the twentieth capacitor, the GND pin of the voltage regulator is grounded, the OUT pin of the voltage regulator is connected with the first power supply, the OUT pin of the voltage regulator is grounded.

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