CN211602234U - Water temperature instrument fault detection device - Google Patents
Water temperature instrument fault detection device Download PDFInfo
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- CN211602234U CN211602234U CN202020711934.7U CN202020711934U CN211602234U CN 211602234 U CN211602234 U CN 211602234U CN 202020711934 U CN202020711934 U CN 202020711934U CN 211602234 U CN211602234 U CN 211602234U
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- 238000004891 communication Methods 0.000 claims abstract description 12
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Abstract
The utility model discloses a water temperature instrument fault detection device, which comprises a device main body, wherein a singlechip module circuit, a power module circuit, a program writing module circuit and a signal input/output module circuit are encapsulated in the device main body, the power module circuit, the program writing module circuit and the signal input/output module circuit are respectively and electrically connected with the singlechip module circuit, a power interface, an RS232 serial interface and an RS485 communication interface are arranged on the device main body, and the water temperature instrument fault detection device is connected with the output voltage of equipment to be detected through the power interface; the upper computer writes a fault detection program into the water temperature instrument fault detection device through the RS232 serial interface; the water temperature instrument fault detection device is in communication connection with the equipment to be detected through the RS485 communication interface. The utility model discloses small in size, simple structure to possess stronger interference killing feature, can carry out short-term test to the trouble condition of temperature appearance, greatly promoted temperature appearance fault detection device's practicality and use convenience.
Description
Technical Field
The utility model relates to an equipment trouble detects technical field, concretely relates to temperature appearance fault detection device.
Background
A water temperature gauge is an instrument for monitoring water temperature data. When the water temperature instrument has faults such as power output faults, signal output faults and the like, the fault type of the water temperature instrument needs to be detected and a detection result needs to be fed back. The existing fault detection device for the water temperature instrument is large in size, too complex in internal circuit structure, poor in anti-interference performance, generally high in selling price, low in practicability and convenience in use, and incapable of meeting market demands.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a circuit structure is simple, convenient and practical and have higher job stabilization's temperature appearance fault detection device to the realization is to the automatic short-term test of temperature appearance trouble.
To achieve the purpose, the utility model adopts the following technical proposal:
the fault detection device for the water temperature instrument comprises a device main body, wherein a singlechip module circuit, a power module circuit, a program writing module circuit and a signal input/output module circuit are packaged in the device main body, the power module circuit, the program writing module circuit and the signal input/output module circuit are respectively and electrically connected with the singlechip module circuit, a power interface, an RS232 serial interface and an RS485 communication interface are arranged on the device main body, and the fault detection device for the water temperature instrument is connected with the output voltage of equipment to be detected through the power interface; the upper computer writes a fault detection program into the fault detection device of the water temperature instrument through the RS232 serial interface; and the water temperature instrument fault detection device is in communication connection with the equipment to be detected through the RS485 communication interface.
As a preferred scheme of the utility model, the power module circuit includes a terminal PIN, and a first port PIN1 of the terminal PIN is electrically connected with a negative electrode of the power interface; the second port PIN2 of the wiring terminal PIN is electrically connected with the positive pole of the power interface;
the power module circuit further comprises a voltage regulating chip, and a first PIN of the voltage regulating chip is connected with a second port PIN2 of the wiring terminal PIN; the fifth PIN and the third PIN of the voltage regulating chip are in short circuit and then are connected with the first port PIN1 of the wiring terminal PIN, and the fifth PIN and the third PIN of the voltage regulating chip are in short circuit and then are simultaneously grounded; a diode D1 is connected between the second port PIN2 and the first port PIN1 of the binding post PIN in series; two ends of the diode D1 are connected with a filter capacitor C1 in parallel; two ends of the filter capacitor C1 are connected with a filter capacitor C2 in parallel;
the fourth pin of the voltage regulating chip is sequentially connected in series with a resistor R1 and a light emitting diode L2 and then grounded; the two ends of the resistor R1 and the light-emitting diode L2 which are connected in series are connected with a filter capacitor C5 in parallel; two ends of the filter capacitor C5 are connected with a filter capacitor C4 in parallel; two ends of the filter capacitor C4 are connected with a filter capacitor C3 in parallel; a first pin of the voltage regulating chip is connected with a reverse Schottky diode D2 in series and then is grounded; an inductor L1 is connected between the second pin and the fourth pin of the voltage regulating chip;
and a fourth pin of the voltage regulating chip is used as a voltage output port of the power module circuit to be connected with the singlechip module circuit, the program writing module circuit and the signal input/output module circuit, and supplies power for each module circuit.
As an optimized scheme of the utility model, the pressure regulating chip is LM 2596's pressure regulating chip for the model.
As a preferred embodiment of the present invention, the single chip module circuit includes a single chip, and a reset circuit and a clock circuit electrically connected to the single chip, the reset circuit includes a capacitor C6 and a resistor R10, one end of the capacitor C6 is connected to the ninth pin of the single chip, and the other end is connected to the forty-th pin of the single chip; one end of the resistor R10 is connected with a ninth pin of the singlechip chip, and the other end of the resistor R10 is grounded;
the clock circuit comprises a capacitor C7, a capacitor C8 and a crystal oscillator Y1, wherein one end of the capacitor C7 is connected with eighteen pins of the single chip microcomputer chip, and the other end of the capacitor C7 is grounded; one end of the capacitor C8 is connected with the nineteenth pin of the singlechip chip, and the other end of the capacitor C8 is grounded; one end of the crystal oscillator Y1 is connected with the eighteenth pin of the single chip microcomputer chip, and the other end of the crystal oscillator Y1 is connected with the nineteenth pin of the single chip microcomputer chip.
As an optimal scheme of the utility model, the model of singlechip chip is STC12C5A60S 2.
As a preferred scheme of the present invention, the program writing module circuit includes a COM port and a level shift chip, and the second port COM2 of the COM port is connected to the fourteenth pin of the level shift chip through a resistor R11; a third port COM3 of the COM port is connected with a thirteenth pin of the level shift chip through a resistor R12; a first voltage stabilizing diode TVS1 and a second voltage stabilizing diode TVS2 are connected in series between the second port COM2 and the third port COM3 of the COM port; the intersection point M of the first and second zener diodes TVS1 and TVS2 is grounded;
a sixteenth pin of the level conversion chip is connected with a fortieth pin of the single chip microcomputer chip in the single chip microcomputer module circuit; a fifteenth pin of the level conversion chip is grounded; a capacitor C9 is connected between the sixteenth pin and the fifteenth pin of the level conversion chip;
a twelfth pin of the level conversion chip is connected with a tenth pin of the single chip microcomputer chip; the eleventh pin of the level conversion chip is connected with the eleventh pin of the single chip microcomputer chip; a tenth pin and a ninth pin of the level conversion chip are suspended;
the first pin of the level conversion chip is connected with a third pin after being connected with a capacitor C10;
a second pin of the level conversion chip is externally connected with a 5V working voltage after being connected with a capacitor C11;
a fourth pin of the level conversion chip is connected with a fifth pin after being connected with a capacitor C12;
a sixth pin of the level conversion chip is connected with a capacitor C13 and then grounded;
and a seventh pin and an eighth pin of the level conversion chip are suspended.
As a preferred embodiment of the present invention, the model of the level shift chip is MAX 3232.
As a preferred embodiment of the present invention, the signal input/output module circuit includes an interface chip and a terminal P485, and the first pin of the interface chip is connected to the tenth pin of the single chip in the single chip module circuit;
the second pin and the third pin of the interface chip are connected with the twelfth pin of the single chip microcomputer chip after short circuit;
a fourth pin of the interface chip is connected with an eleventh pin of the single chip microcomputer chip;
the fifth pin of the interface chip is connected with the ninth pin of the singlechip chip through the resistor R10;
the sixth pin of the interface chip is connected with the third port P3 of the binding post P485 through a resistor R13;
the seventh pin of the interface chip is connected with the second port P2 of the binding post P485 through a resistor R14;
the eighth pin of the interface chip is connected with the fortieth pin of the singlechip chip;
a third zener diode TVS3 and a fourth zener diode TVS4 are connected in series between the third port P3 and the second port P2 of the post P485, and an intersection N of the third zener diode TVS3 and the fourth zener diode TVS4 is grounded;
a resistor R16 is connected between the seventh pin and the eighth pin of the interface chip;
the sixth pin of the interface chip is simultaneously connected with the fortieth pin of the singlechip chip through a resistor R15;
the seventh pin of the interface chip is grounded after being connected with a resistor R17 in series;
and the binding post P485 is connected with the RS485 interface.
As an optimized scheme of the utility model, the interface chip is 485 interface chips.
The utility model discloses small in size, simple structure to possess stronger interference killing feature, can carry out short-term test to the trouble condition of temperature appearance, greatly promoted temperature appearance fault detection device's practicality and use convenience.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below. It is obvious that the drawings described below are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be obtained from these drawings without inventive effort.
Fig. 1 is a schematic external structural diagram of a water temperature meter fault detection device according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the internal overall circuit structure of the water temperature gauge fault detection device;
FIG. 3 is a schematic diagram of the circuit structure of the power circuit packaged in the failure detection device of the water temperature instrument;
FIG. 4 is a schematic circuit structure diagram of a single-chip microcomputer module circuit packaged in the water temperature instrument fault detection device;
FIG. 5 is a schematic circuit diagram of a program write module circuit packaged in the water temperature instrument fault detection device;
fig. 6 is a schematic circuit structure diagram of a signal input/output module circuit packaged in the water temperature instrument fault detection device.
Detailed Description
The technical solution of the present invention is further explained by the following embodiments with reference to the accompanying drawings.
Wherein the showings are for the purpose of illustration only and are shown by way of illustration only and not in actual form, and are not to be construed as limiting the present patent; for a better understanding of the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "inner", "outer", etc. are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not indicated or implied that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore, the terms describing the positional relationship in the drawings are used only for illustrative purposes and are not to be construed as limiting the present patent, and the specific meaning of the terms will be understood by those skilled in the art according to the specific circumstances.
In the description of the present invention, unless otherwise explicitly specified or limited, the term "connected" or the like, if appearing to indicate a connection relationship between the components, is to be understood broadly, for example, as being either a fixed connection, a detachable connection, or an integral part; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through one or more other components or may be in an interactive relationship with one another. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In this embodiment, a ZKGD3000-NT water temperature instrument is taken as an example of a fault detection object, and the structure of the water temperature instrument fault detection device provided in this embodiment and a process for realizing fault detection of the water temperature instrument are explained.
Fig. 1 shows an external structure schematic diagram of a water temperature instrument fault detection device provided by the embodiment of the present invention. Fig. 2 is a schematic diagram of an internal overall circuit structure of the water temperature instrument fault detection device provided in this embodiment. Referring to fig. 1 and 2, the water temperature instrument fault detection device provided in this embodiment includes a device main body 1, a single chip module circuit, a power module circuit electrically connected to the single chip module circuit, a program write module circuit, and a signal input/output module circuit are packaged in the device main body 1, the device main body 1 is provided with a power interface 11, an RS232 serial interface 12, and an RS485 communication interface 13, and the water temperature instrument fault detection device is connected to an output voltage of a device to be tested (in this embodiment, a ZKGD3000-NT water temperature instrument) through the power interface 11; the upper computer writes a fault detection program into the water temperature instrument fault detection device through the RS232 serial interface 232; the water temperature instrument fault detection device is in communication connection with the equipment to be detected through the RS485 communication interface 13.
Fig. 3 shows a circuit configuration diagram of the power module circuit. Referring to fig. 3, the power module circuit includes a terminal PIN, and a first port P1N1 of the terminal PIN is electrically connected to a negative electrode of the power interface 11; the second port PIN2 of the wiring terminal PIN is electrically connected with the positive pole of the power supply interface 11;
the power module circuit further comprises a voltage regulating chip 101, wherein a first PIN of the voltage regulating chip 101 is connected with a second port PIN2 of the wiring terminal PIN; the fifth PIN and the third PIN of the voltage regulating chip 101 are in short circuit and then are connected with the first port P1N1 of the wiring terminal PIN, and the fifth PIN and the third PIN of the voltage regulating chip 101 are in short circuit and then are grounded simultaneously; a diode D1 is connected between the second port PIN2 and the first port PIN1 of the wiring terminal PIN in series; two ends of the diode D1 are connected with a filter capacitor C1 in parallel; two ends of the filter capacitor C1 are connected with a filter capacitor C2 in parallel;
the fourth pin of the voltage regulating chip 101 is connected in series with a resistor R1 and a light emitting diode L2 in sequence and then grounded; the two ends of the resistor R1 and the light-emitting diode L2 which are connected in series are connected with a filter capacitor C5 in parallel; two ends of the filter capacitor C5 are connected with a filter capacitor C4 in parallel; two ends of the filter capacitor C4 are connected with a filter capacitor C3 in parallel; the first pin of the voltage regulating chip 101 is connected in series with a reverse schottky diode D2 and then grounded; an inductor L1 is connected between the second pin and the fourth pin of the voltage regulating chip 101;
the fourth pin of the voltage regulation chip 101 is used as a voltage output port of the power module circuit, and is connected with the single chip module circuit, the program writing module circuit and the signal input/output module circuit to supply power to each module circuit.
Preferably, the voltage regulation chip 101 is of the model LM 2596.
The following operation principle of the power module circuit is briefly described as follows:
the power module circuit has the function of converting input 9V direct current voltage into 5V direct current voltage to supply power for each module circuit. The diode D1 is used for reverse connection protection; the first pin of the voltage regulation chip 101 is externally connected with 9V voltage (output voltage of the device to be tested), and the fourth pin of the voltage regulation chip 101 outputs the converted 5V voltage. The schottky diode D2 functions as a current limiting and protection circuit. The inductor L1 is used to prevent the output voltage from changing abruptly when the voltage regulator chip 101 is turned off. The light emitting diode L2 is used as a power indicator of the water temperature instrument fault detection device and is used for indicating whether the output voltage of the equipment to be detected is normal or not.
Fig. 4 shows a circuit configuration diagram of the one-chip microcomputer module circuit. Referring to fig. 4, the single chip module circuit includes a single chip 201, and a reset circuit and a clock circuit electrically connected to the single chip 201, where the reset circuit includes a capacitor C6 and a resistor R10, one end of the capacitor C6 is connected to a ninth pin of the single chip 201, and the other end is connected to a fortieth pin of the single chip 201; one end of the resistor R10 is connected with the ninth pin of the singlechip chip 201, and the other end is grounded;
the clock circuit comprises a capacitor C7, a capacitor C8 and a crystal oscillator Y1, wherein one end of the capacitor C7 is connected with eighteen pins of the singlechip chip 201, and the other end of the capacitor C7 is grounded; one end of the capacitor C8 is connected to the nineteenth pin of the monolithic chip 201, and the other end is grounded; one end of the crystal oscillator Y1 is connected to the eighteenth pin of the monolithic chip 201, and the other end is connected to the nineteenth pin of the monolithic chip 201.
A fortieth pin of the single chip 201 is used as a power input pin of the single chip 201 to be connected with a voltage output port of the power module circuit.
Preferably, the model of the single chip microcomputer chip 201 is STC12C5a60S 2.
The function of the single chip module circuit is briefly explained as follows:
the single chip microcomputer module circuit takes the single chip microcomputer chip 201 as a core, and has the functions of judging the fault type of the equipment to be detected according to the output signal of the equipment to be detected and a fault detection program written in advance and outputting a feedback signal to the equipment to be detected according to the judgment result.
Fig. 5 shows a circuit configuration diagram of the program writing module circuit. Referring to fig. 5, the program writing module circuit includes a COM port (RS232 serial interface) and a level shift chip 301, and a second port COM2 of the COM port is connected to a fourteenth pin of the level shift chip 301 through a resistor R11; the third port COM3 of the COM port is connected to the thirteenth pin of the level shift chip 301 through a resistor R12; a first voltage regulator diode TVS1 and a second voltage regulator diode TVS2 are connected in series between the second port COM2 and the third port COM3 of the COM port; the intersection M of the first and second zener diodes TVS1 and TVS2 is grounded;
a sixteenth pin of the level conversion chip 301 is connected with a fortieth pin of the singlechip chip 201 in the singlechip module circuit; the fifteenth pin of the level shift chip 301 is grounded; a capacitor C9 is connected between the sixteenth pin and the fifteenth pin of the level shift chip 301;
a twelfth pin of the level conversion chip 301 is connected with a tenth pin of the single chip microcomputer chip 201; the eleventh pin of the level shift chip 301 is connected with the eleventh pin of the singlechip chip 201; the tenth pin and the ninth pin of the level shift chip 301 are suspended;
the first pin of the level shift chip 301 is connected to the third pin after being connected to the capacitor C10;
a second pin of the level conversion chip 301 is externally connected with a 5V working voltage after being connected with a capacitor C11;
the fourth pin of the level shift chip 301 is connected to the fifth pin after being connected to the capacitor C12;
the sixth pin of the level shift chip 301 is connected to the capacitor C13 and then grounded;
the seventh pin and the eighth pin of the level shift chip 301 are floating.
Preferably, the model number of the level shift chip 301 is MAX 3232.
The operation of the program-writing module circuit is briefly described as follows:
the program writing module circuit takes a level conversion chip as a core 301, and has the function of writing a written fault detection program into a single chip microcomputer chip through a COM (component object model) port. The COM port is an RS232 serial port for connecting to an upper computer such as a computer to download the fault detection program. The zener diodes TVS1 and TVS2 function as overvoltage protection elements. Since the serial port of the single chip must be subjected to level conversion to communicate with the standard RS232 serial interface, the level conversion chip is required to be used as a conversion medium for level conversion.
Fig. 6 shows a circuit configuration diagram of the signal input/output module circuit. Referring to fig. 6, the signal input/output module circuit includes an interface chip 401 and a binding post P485, and a first pin of the interface chip 401 is connected to a tenth pin of the one-chip microcomputer chip 201 in the one-chip microcomputer module circuit;
the second pin and the third pin of the interface chip 401 are connected with the twelfth pin of the single chip 201 after being short-circuited;
the fourth pin of the interface chip 401 is connected with the eleventh pin of the single chip 201;
the fifth pin of the interface chip 401 is connected with the ninth pin of the single chip 201 through a resistor R10;
the sixth pin of the interface chip 401 is connected with the third port P3 of the binding post P485 through a resistor R13;
the seventh pin of the interface chip 401 is connected to the second port P2 of the post P485 through a resistor R14;
the eighth pin of the interface chip 401 is connected with the fortieth pin of the single chip 201;
a third voltage-regulator diode TVS3 and a fourth voltage-regulator diode TVS4 are connected in series between a third port P3 and a second port P2 of the binding post P485, and a cross point N of the third voltage-regulator diode TVS3 and the fourth voltage-regulator diode TVS4 is grounded;
a resistor R16 is connected between the seventh pin and the eighth pin of the interface chip 401;
the sixth pin of the interface chip 401 is connected to the fortieth pin of the single chip 201 through a resistor R15;
the seventh pin of the interface chip 401 is connected in series with a resistor R17 and then grounded;
and the binding post P485 is connected with the RS485 interface.
Preferably, the interface chip 401 is a 485 interface chip.
In addition, preferably, the water temperature instrument fault detection device provided by this embodiment further includes a signal input indicator light and a signal output indicator light, and the signal input indicator light and the signal output indicator light are respectively connected to the designated pin of the single chip microcomputer chip 201. The signal input indicator light is used for prompting that the current equipment to be tested of the tester has a signal input to the water temperature instrument fault detection device provided by the embodiment. The signal output indicator light is used for prompting a tester that the current water temperature instrument fault detection device has a feedback signal to output to equipment to be tested.
It should be understood that the above-described embodiments are merely illustrative of the preferred embodiments of the present invention and the technical principles thereof. It will be understood by those skilled in the art that various modifications, equivalents, changes, and the like can be made to the present invention. However, these modifications are within the scope of the present invention as long as they do not depart from the spirit of the present invention. In addition, certain terms used in the specification and claims of the present application are not limiting, but are used merely for convenience of description.
Claims (9)
1. A water temperature instrument fault detection device is characterized by comprising a device main body, wherein a singlechip module circuit, a power module circuit, a program writing module circuit and a signal input/output module circuit are packaged in the device main body, the power module circuit, the program writing module circuit and the signal input/output module circuit are respectively and electrically connected with the singlechip module circuit, a power interface, an RS232 serial interface and an RS485 communication interface are arranged on the device main body, and the water temperature instrument fault detection device is connected with the output voltage of equipment to be detected through the power interface; the upper computer writes a fault detection program into the fault detection device of the water temperature instrument through the RS232 serial interface; and the water temperature instrument fault detection device is in communication connection with the equipment to be detected through the RS485 communication interface.
2. The water temperature gauge fault detection device of claim 1, wherein the power module circuit comprises a terminal PIN, a first port PIN1 of the terminal PIN being electrically connected to a negative pole of the power interface; the second port PIN2 of the wiring terminal PIN is electrically connected with the positive pole of the power interface;
the power module circuit further comprises a voltage regulating chip, and a first PIN of the voltage regulating chip is connected with a second port PIN2 of the wiring terminal PIN; the fifth PIN and the third PIN of the voltage regulating chip are in short circuit and then are connected with the first port PIN1 of the wiring terminal PIN, and the fifth PIN and the third PIN of the voltage regulating chip are in short circuit and then are simultaneously grounded; a diode D1 is connected between the second port PIN2 and the first port PIN1 of the binding post PIN in series; two ends of the diode D1 are connected with a filter capacitor C1 in parallel; two ends of the filter capacitor C1 are connected with a filter capacitor C2 in parallel;
the fourth pin of the voltage regulating chip is sequentially connected in series with a resistor R1 and a light emitting diode L2 and then grounded; the two ends of the resistor R1 and the light-emitting diode L2 which are connected in series are connected with a filter capacitor C5 in parallel; two ends of the filter capacitor C5 are connected with a filter capacitor C4 in parallel; two ends of the filter capacitor C4 are connected with a filter capacitor C3 in parallel; a first pin of the voltage regulating chip is connected with a reverse Schottky diode D2 in series and then is grounded; an inductor L1 is connected between the second pin and the fourth pin of the voltage regulating chip;
and a fourth pin of the voltage regulating chip is used as a voltage output port of the power module circuit to be connected with the singlechip module circuit, the program writing module circuit and the signal input/output module circuit, and supplies power for each module circuit.
3. The water temperature instrument fault detection device as claimed in claim 2, wherein the pressure regulating chip is a model LM2596 pressure regulating chip.
4. The water temperature instrument fault detection device as claimed in claim 1, wherein said single chip module circuit comprises a single chip, and a reset circuit and a clock circuit electrically connected to said single chip, said reset circuit comprising a capacitor C6 and a resistor R10, one end of said capacitor C6 being connected to a ninth pin of said single chip, and the other end being connected to a fortieth pin of said single chip; one end of the resistor R10 is connected with a ninth pin of the singlechip chip, and the other end of the resistor R10 is grounded;
the clock circuit comprises a capacitor C7, a capacitor C8 and a crystal oscillator Y1, wherein one end of the capacitor C7 is connected with eighteen pins of the single chip microcomputer chip, and the other end of the capacitor C7 is grounded; one end of the capacitor C8 is connected with the nineteenth pin of the singlechip chip, and the other end of the capacitor C8 is grounded; one end of the crystal oscillator Y1 is connected with the eighteenth pin of the single chip microcomputer chip, and the other end of the crystal oscillator Y1 is connected with the nineteenth pin of the single chip microcomputer chip.
5. The water temperature gauge fault detection device of claim 4, wherein the model of the single chip microcomputer chip is STC12C5A60S 2.
6. The water temperature instrument fault detection device as claimed in claim 4, characterized in that the program writing module circuit comprises a COM port and a level conversion chip, wherein a second port COM2 of the COM port is connected with a fourteenth pin of the level conversion chip through a resistor R11; a third port COM3 of the COM port is connected with a thirteenth pin of the level shift chip through a resistor R12; a first voltage stabilizing diode TVS1 and a second voltage stabilizing diode TVS2 are connected in series between the second port COM2 and the third port COM3 of the COM port; the intersection point M of the first and second zener diodes TVS1 and TVS2 is grounded;
a sixteenth pin of the level conversion chip is connected with a fortieth pin of the single chip microcomputer chip in the single chip microcomputer module circuit; a fifteenth pin of the level conversion chip is grounded; a capacitor C9 is connected between the sixteenth pin and the fifteenth pin of the level conversion chip;
a twelfth pin of the level conversion chip is connected with a tenth pin of the single chip microcomputer chip; the eleventh pin of the level conversion chip is connected with the eleventh pin of the single chip microcomputer chip; a tenth pin and a ninth pin of the level conversion chip are suspended;
the first pin of the level conversion chip is connected with a third pin after being connected with a capacitor C10;
a second pin of the level conversion chip is externally connected with a 5V working voltage after being connected with a capacitor C11;
a fourth pin of the level conversion chip is connected with a fifth pin after being connected with a capacitor C12;
a sixth pin of the level conversion chip is connected with a capacitor C13 and then grounded;
and a seventh pin and an eighth pin of the level conversion chip are suspended.
7. The water temperature gauge fault detection device of claim 6, wherein the model of the level shifting chip is MAX 3232.
8. The water temperature instrument fault detection device as claimed in claim 4 or 6, wherein said signal input/output module circuit comprises an interface chip and a binding post P485, a first pin of said interface chip is connected with a tenth pin of said single chip in said single chip module circuit;
the second pin and the third pin of the interface chip are connected with the twelfth pin of the single chip microcomputer chip after short circuit;
a fourth pin of the interface chip is connected with an eleventh pin of the single chip microcomputer chip;
the fifth pin of the interface chip is connected with the ninth pin of the singlechip chip through the resistor R10;
the sixth pin of the interface chip is connected with the third port P3 of the binding post P485 through a resistor R13;
the seventh pin of the interface chip is connected with the second port P2 of the binding post P485 through a resistor R14;
the eighth pin of the interface chip is connected with the fortieth pin of the singlechip chip;
a third zener diode TVS3 and a fourth zener diode TVS4 are connected in series between the third port P3 and the second port P2 of the post P485, and an intersection N of the third zener diode TVS3 and the fourth zener diode TVS4 is grounded;
a resistor R16 is connected between the seventh pin and the eighth pin of the interface chip;
the sixth pin of the interface chip is simultaneously connected with the fortieth pin of the singlechip chip through a resistor R15;
the seventh pin of the interface chip is grounded after being connected with a resistor R17 in series;
and the binding post P485 is connected with the RS485 interface.
9. The water temperature gauge fault detection device of claim 8, wherein the interface chip is a 485 interface chip.
Priority Applications (1)
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CN202020711934.7U CN211602234U (en) | 2020-04-30 | 2020-04-30 | Water temperature instrument fault detection device |
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CN202020711934.7U CN211602234U (en) | 2020-04-30 | 2020-04-30 | Water temperature instrument fault detection device |
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CN211602234U true CN211602234U (en) | 2020-09-29 |
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CN202020711934.7U Expired - Fee Related CN211602234U (en) | 2020-04-30 | 2020-04-30 | Water temperature instrument fault detection device |
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CN (1) | CN211602234U (en) |
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2020
- 2020-04-30 CN CN202020711934.7U patent/CN211602234U/en not_active Expired - Fee Related
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CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20200929 |