CN212111600U - One hundred mega Ethernet port EMC testing device - Google Patents
One hundred mega Ethernet port EMC testing device Download PDFInfo
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- CN212111600U CN212111600U CN201922105614.7U CN201922105614U CN212111600U CN 212111600 U CN212111600 U CN 212111600U CN 201922105614 U CN201922105614 U CN 201922105614U CN 212111600 U CN212111600 U CN 212111600U
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Abstract
The utility model provides a hundred mega Ethernet's EMC testing arrangement, keep apart vary voltage circuit, a BOB-Smith circuit, a LED lamp configuration circuit and a PHY chip circuit including an Ethernet mouth circuit, a suppression common mode interference circuit, a network, the Ethernet mouth circuit is connected with suppression common mode interference circuit and LED lamp configuration circuit respectively, the network keeps apart vary voltage circuit and is connected with suppression common mode interference circuit, BOB-Smith circuit and PHY chip circuit respectively, PHY chip circuit is connected to LED lamp configuration circuit. The utility model discloses realize under the prerequisite of not cutting land, solved the EMI problem of hundred mega Ethernet mouth from circuit schematic diagram design and PCB design aspect, compatible simultaneously hundred mega Ethernet mouth interface anti-static interference and lightning protection design.
Description
Technical Field
The utility model relates to a EMC tests technical field, especially relates to a hundred mega Ethernet's EMC testing arrangement.
Background
The EMC test is also called electromagnetic compatibility (EMC), refers to the comprehensive evaluation of the interference level (EMI) and the anti-interference capability (EMS) of electronic products in the aspect of electromagnetic field, and is one of the most important indexes of product quality, and the measurement of the EMC consists of a test site and a test instrument.
At present, the traditional EMC design scheme of the hundred-mega Ethernet port is mainly based on a land cutting design, namely, a mode of cutting cakes between the land of the Ethernet port and the land of a main board is completely distinguished, the design method enables the ground plane of the whole board to be incomplete, ground impedance is easily caused to high-frequency signals, high-frequency radiation interference is not favorably inhibited, and the scheme expansibility is not strong.
Disclosure of Invention
The to-be-solved technical problem of the utility model lies in providing an EMC testing arrangement of hundred mega Ethernet mouth, realizes under the prerequisite not cutting land, has solved the EMI problem of hundred mega Ethernet mouth from circuit schematic diagram design and PCB design aspect, has compatible hundred mega Ethernet mouth interface antistatic interference and lightning protection design simultaneously.
The utility model discloses a realize like this:
an EMC testing device of a hundred-mega Ethernet port comprises an Ethernet port circuit, a common mode interference suppression circuit, a network isolation transformation circuit, a BOB-Smith circuit, an LED lamp configuration circuit and a PHY chip circuit, wherein the Ethernet port circuit is respectively connected with the common mode interference suppression circuit and the LED lamp configuration circuit, the network isolation transformation circuit is respectively connected with the common mode interference suppression circuit, the BOB-Smith circuit and the PHY chip circuit, and the PHY chip circuit is connected to the LED lamp configuration circuit.
Furthermore, the system also comprises a GDT bleeder circuit which is connected with the network isolation transformer circuit.
Further, the ethernet port circuit includes an RJ45 port socket CN1, the first pin, the second pin, the third pin and the sixth pin of the RJ45 port socket CN1 are all connected to a common mode interference suppression circuit, the ninth pin, the tenth pin, the eleventh pin and the twelfth pin of the RJ45 port socket CN1 are all connected to an LED lamp configuration circuit, the G1 pin and the G2 pin of the RJ45 port socket CN1 are all grounded, and the fourth pin, the fifth pin, the seventh pin and the eighth pin of the RJ45 port socket CN1 are all floating.
Further, the common mode interference suppression circuit includes a common mode inductor L17 and a common mode inductor L18, a fourth pin of the common mode inductor L17 is connected to the first pin of the ethernet port circuit, a first pin of the common mode inductor L17 is connected to the second pin of the ethernet port circuit, a fourth pin of the common mode inductor L18 is connected to the third pin of the ethernet port circuit, and a first pin of the common mode inductor L18 is connected to the sixth pin of the ethernet port circuit; a third pin and a second pin of the common mode inductor L17 and a third pin and a second pin of the common mode inductor L18 are respectively connected with corresponding pins in the network isolation transformation circuit;
or the circuit for suppressing common mode interference includes a resistor R520, a resistor R521, a resistor R522, and a resistor R523, where one end of the resistor R520 is connected to the first pin of the ethernet port circuit, one end of the resistor R521 is connected to the second pin of the ethernet port circuit, one end of the resistor R522 is connected to the third pin of the ethernet port circuit, and one end of the resistor R523 is connected to the sixth pin of the ethernet port circuit; the other end of the resistor R520, the other end of the resistor R521, the other end of the resistor R522 and the other end of the resistor R523 are respectively connected with corresponding pins in the network isolation voltage transformation circuit;
or the common mode interference suppression circuit comprises a common mode inductor L17, a common mode inductor L18, a resistor R520, a resistor R521, a resistor R522 and a resistor R523, a fourth pin of the common mode inductor L17 is connected to a first pin of the ethernet port circuit, a first pin of the common mode inductor L17 is connected to a second pin of the ethernet port circuit, a fourth pin of the common mode inductor L18 is connected to a third pin of the ethernet port circuit, and a first pin of the common mode inductor L18 is connected to a sixth pin of the ethernet port circuit; the third pin of the common mode inductor L17, the second pin of the common mode inductor L17, the third pin of the common mode inductor L18, and the second pin of the common mode inductor L18 are respectively connected to one end of a resistor R520, one end of a resistor R521, one end of a resistor R522, and one end of a resistor R523, and the other end of the resistor R520, the other end of the resistor R521, the other end of the resistor R522, and the other end of the resistor R523 are respectively connected to corresponding pins in the network isolation transformer circuit.
Further, the network isolation transformation circuit includes a transformer U27, a capacitor C356, and a capacitor C357, where a sixteenth pin, a fourteenth pin, an eleventh pin, and a ninth pin of the transformer U27 are respectively connected to pins/ports corresponding to the common mode interference suppression circuit, a fifteenth pin and a tenth pin of the transformer U27 are both connected to the BOB-Smith circuit, a second pin of the transformer U27 is connected to one end of the capacitor C356, a seventh pin of the transformer U27 is connected to one end of the capacitor C357, the other ends of the capacitor C356 and the capacitor C357 are both grounded, a first pin, a third pin, a sixth pin, and an eighth pin of the transformer U27 are all connected to the PHY chip circuit, and a fourth pin, a fifth pin, a twelfth pin, and a thirteenth pin of the transformer U27 are all floating.
Further, the BOB-Smith circuit comprises a capacitor C359, a resistor R472 and a resistor R473, wherein one end of the resistor R472 is connected to the tenth pin of the network isolation transformer circuit, one end of the resistor R473 is connected to the fifteenth pin of the network isolation transformer circuit, the other end of the resistor R472 and the other end of the resistor R473 are both connected to one end of the capacitor C359, and the other end of the capacitor C359 is grounded.
Further, the GDT bleeder circuit comprises a gas discharge tube D33 and a resistor R471, one end of the gas discharge tube D33 and one end of the resistor R471 are both connected to the tenth pin of the network isolation transformer circuit, the other end of the resistor R471 is connected to the fifteenth pin of the network isolation transformer circuit, and the other end of the gas discharge tube D33 is grounded.
Further, the LED lamp configuring circuit includes a resistor R149, a resistor R151, a resistor R154, a resistor R156, a resistor R148, a resistor R150, a capacitor C160, and a capacitor C161, one end of the capacitor C160, one end of the resistor R149 and one end of the resistor R150 are connected to the tenth pin of the ethernet port circuit, one end of the resistor R151, one end of the capacitor C161 and one end of the resistor R148 are all connected to the eleventh pin of the ethernet port circuit, one end of the resistor R154 is connected to the ninth pin of the ethernet port circuit, one end of the resistor R156 is connected to the twelfth pin of the ethernet port circuit, the other end of the resistor R148 and the other end of the resistor R150 are both connected to the PHY chip circuit, the other end of the resistor R151 and the other end of the resistor R156 are connected to a power supply, and the other end of the resistor R149, the other end of the resistor R154, the other end of the capacitor C160 and the other end of the capacitor C161 are all grounded.
Further, the resistance values of the resistor R520, the resistor R521, the resistor R522 and the resistor R523 are not more than 10 ohms; the resistor R520, the resistor R521, the resistor R522, the resistor R523, the resistor R472, the resistor R473 and the resistor R471 are packaged in a 0603 packaging mode, a 0805 packaging mode or a 1206 packaging mode.
The printed circuit board further comprises a PCB, six layers of the PCB are arranged, and the TOP layer, the first GND layer, the VCC layer, the signal layer, the second GND layer and the BOTTOM layer are sequentially arranged from TOP to BOTTOM, the RJ45 gateway seat CN1, the resistor R520, the resistor R521, the resistor R522, the resistor R523, the transformer U27, the gas discharge tube D33, the resistor R149, the resistor R151, the resistor R154, the resistor R156, the resistor R148, the resistor R150, the capacitor C160, the capacitor C161, the common-mode inductor L17, the common-mode inductor L18 and the PHY chip circuit are arranged on the TOP layer, and the capacitor C359, the capacitor C356, the capacitor C357, the resistor R472, the resistor R473 and the resistor R471 are arranged on the BOTTOM layer; the ground pin of the gas discharge tube D33 and the ground pin of the capacitor C359 are directly connected to the ground pin of the RJ45 socket CN1, and the RJ45 socket CN1, the capacitor C356, the capacitor C357, the resistor R149, the resistor R154, the capacitor C160, the capacitor C161 and the ground pin of the PHY chip are all connected to the first GND layer and the second GND layer through via holes.
The utility model has the advantages that: the invention balances the board-level common-ground and cut-ground design, and research personnel can flexibly select different design schemes according to factors such as product market positioning, lightning protection level requirements, cost requirements and the like under the condition that the PCB structure is not changed; can compatible EMI and the anti-interference problem of solving hundred million net gapes through board level design, pass through the relevant standard requirement of EMC smoothly, saved material cost and cost of labor greatly, directly bring the cost benefit of enterprise, make the product more have market competition demand, promote the product lightning protection grade, expansibility is stronger.
Drawings
The invention will be further described with reference to the following examples with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of an EMC testing apparatus for a hundred-mega ethernet port of the present invention.
Fig. 2 is a schematic diagram of a specific circuit connection in the present invention.
Fig. 3a is a schematic structural diagram of an embodiment of a common mode interference suppression circuit according to the present invention.
Fig. 3b is a schematic structural diagram of a circuit for suppressing common mode interference according to the present invention.
Fig. 3c is a schematic diagram of a third structure of the common mode interference rejection circuit according to the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the present invention is not limited to the following examples.
Please refer to fig. 1, the utility model discloses a hundred mega ethernet's EMC testing arrangement, including an ethernet mouth circuit, a suppression common mode interference circuit, a network isolation vary voltage circuit, a BOB-Smith circuit, a GDT bleeder circuit, an LED lamp configuration circuit and a PHY chip circuit, ethernet mouth circuit respectively with suppress common mode interference circuit and LED lamp configuration circuit connection, network isolation vary voltage circuit respectively with suppression common mode interference circuit, BOB-Smith circuit, GDT bleeder circuit and PHY chip circuit connection, PHY chip circuit is connected to LED lamp configuration circuit.
Preferably, the concrete structure is: as shown in fig. 2 to 3 c:
the Ethernet port circuit comprises an RJ45 port seat CN1, a first pin, a second pin, a third pin and a sixth pin of the RJ45 port seat CN1 are all connected to a common mode interference suppression circuit, a ninth pin, a tenth pin, an eleventh pin and a twelfth pin of the RJ45 port seat CN1 are all connected to an LED lamp configuration circuit, a G1 pin and a G2 pin of the RJ45 port seat CN1 are all grounded, and a fourth pin, a fifth pin, a seventh pin and an eighth pin of the RJ45 port seat CN1 are all suspended;
the common mode interference suppression circuit has three different structural forms, which are respectively as follows:
as shown in fig. 3a, in the first embodiment: the common mode interference suppression circuit comprises a common mode inductor L17 and a common mode inductor L18, the fourth pin and the first pin of the common mode inductor L17 and the fourth pin and the first pin of the common mode inductor L18 are respectively connected with corresponding pins in the Ethernet port circuit, that is, the common mode interference suppression circuit comprises: a fourth pin of the common mode inductor L17 is connected to the first pin of the ethernet port circuit, a first pin of the common mode inductor L17 is connected to the second pin of the ethernet port circuit, a fourth pin of the common mode inductor L18 is connected to the third pin of the ethernet port circuit, and a first pin of the common mode inductor L18 is connected to the sixth pin of the ethernet port circuit; a third pin and a second pin of the common mode inductor L17 and a third pin and a second pin of the common mode inductor L18 are respectively connected with corresponding pins in the network isolation transformation circuit;
as shown in fig. 3b, the second embodiment: the circuit for suppressing common mode interference includes a resistor R520, a resistor R521, a resistor R522 and a resistor R523, wherein one end of the resistor R520, one end of the resistor R521, one end of the resistor R522 and one end of the resistor R523 are respectively connected to corresponding pins in the ethernet port circuit, that is, the circuit includes: one end of the resistor R520 is connected to the first pin of the ethernet port circuit, one end of the resistor R521 is connected to the second pin of the ethernet port circuit, one end of the resistor R522 is connected to the third pin of the ethernet port circuit, and one end of the resistor R523 is connected to the sixth pin of the ethernet port circuit; the other end of the resistor R520, the other end of the resistor R521, the other end of the resistor R522 and the other end of the resistor R523 are respectively connected with corresponding pins in the network isolation voltage transformation circuit;
as shown in fig. 3c, example three: the circuit for suppressing common mode interference includes a common mode inductor L17, a common mode inductor L18, a resistor R520, a resistor R521, a resistor R522, and a resistor R523, where the fourth pin and the first pin of the common mode inductor L17 and the fourth pin and the first pin of the common mode inductor L18 are respectively connected to corresponding pins in the ethernet port circuit, that is, the circuit includes: a fourth pin of the common mode inductor L17 is connected to the first pin of the ethernet port circuit, a first pin of the common mode inductor L17 is connected to the second pin of the ethernet port circuit, a fourth pin of the common mode inductor L18 is connected to the third pin of the ethernet port circuit, and a first pin of the common mode inductor L18 is connected to the sixth pin of the ethernet port circuit; the third pin of the common mode inductor L17, the second pin of the common mode inductor L17, the third pin of the common mode inductor L18 and the second pin of the common mode inductor L18 are respectively and correspondingly connected with one end of a resistor R520, one end of a resistor R521, one end of a resistor R522 and one end of a resistor R523, and the other end of the resistor R520, the other end of the resistor R521, the other end of the resistor R522 and the other end of the resistor R523 are respectively connected with corresponding pins in the network isolation transformer circuit;
the network isolation transformation circuit comprises a transformer U27, a capacitor C356 and a capacitor C357, wherein a sixteenth pin, a fourteenth pin, an eleventh pin and a ninth pin of the transformer U27 are respectively connected to pins/ports corresponding to a common mode interference suppression circuit, in the first embodiment, the sixteenth pin of the transformer U27 is connected to a third pin of the common mode inductor L17, the fourteenth pin of the transformer U27 is connected to a second pin of the common mode inductor L17, the eleventh pin of the transformer U27 is connected to a third pin of the common mode inductor L18, and the ninth pin of the transformer U27 is connected to a second pin of the common mode inductor L18; in the second embodiment and the third embodiment, the sixteenth pin of the transformer U27 is connected to the other end of the resistor R520, the fourteenth pin of the transformer U27 is connected to the other end of the resistor R521, the eleventh pin of the transformer U27 is connected to the other end of the resistor R522, and the ninth pin of the transformer U27 is connected to the other end of the resistor R523; a fifteenth pin and a tenth pin of the transformer U27 are both connected with a BOB-Smith circuit, and meanwhile, a fifteenth pin and a tenth pin of the transformer U27 are also connected with a GDT bleeder circuit; a second pin of the transformer U27 is connected with one end of a capacitor C356, a seventh pin of the transformer U27 is connected with one end of a capacitor C357, the other end of the capacitor C356 and the other end of the capacitor C357 are all grounded, a first pin, a third pin, a sixth pin and an eighth pin of the transformer U27 are all connected to the PHY chip circuit, and a fourth pin, a fifth pin, a twelfth pin and a thirteenth pin of the transformer U27 are all floating;
the BOB-Smith circuit comprises a capacitor C359, a resistor R472 and a resistor R473, wherein one end of the resistor R472 and one end of the resistor R473 are respectively connected with corresponding pins in the network isolation transformer circuit, that is, the BOB-Smith circuit comprises: one end of the resistor R472 is connected with a tenth pin of the network isolation transformation circuit, and one end of the resistor R473 is connected with a fifteenth pin of the network isolation transformation circuit; the other end of the resistor R472 and the other end of the resistor R473 are both connected to one end of a capacitor C359, and the other end of the capacitor C359 is grounded;
the GDT bleeder circuit comprises a gas discharge tube D33 and a resistor R471, one end of the gas discharge tube D33 and one end of the resistor R471 are both connected to the tenth pin of the network isolation transformer circuit, the other end of the resistor R471 is connected to the fifteenth pin of the network isolation transformer circuit, and the other end of the gas discharge tube D33 is grounded;
the LED lamp configuration circuit comprises a resistor R149, a resistor R151, a resistor R154, a resistor R156, a resistor R148, a resistor R150, a capacitor C160 and a capacitor C161, one end of the capacitor C160, one end of the resistor R149 and one end of the resistor R150 are connected to the tenth pin of the ethernet port circuit, one end of the resistor R151, one end of the capacitor C161 and one end of the resistor R148 are all connected to the eleventh pin of the ethernet port circuit, one end of the resistor R154 is connected to the ninth pin of the ethernet port circuit, one end of the resistor R156 is connected to the twelfth pin of the ethernet port circuit, the other end of the resistor R148 and the other end of the resistor R150 are both connected to the PHY chip circuit, the other end of the resistor R151 and the other end of the resistor R156 are connected to a power supply, and the other end of the resistor R149, the other end of the resistor R154, the other end of the capacitor C160 and the other end of the capacitor C161 are all grounded.
(1) The PCB is provided with six layers, namely a TOP layer (1 st layer), a first GND layer (2 nd layer), a VCC layer (3 rd layer), a signal layer (4 th layer), a second GND layer (5 th layer) and a BOTTOM layer (6 th layer) from TOP to BOTTOM, and the RJ45 net port seat CN1, a resistor R520, a resistor R521, a resistor R522, a resistor R523, a transformer U27, a gas discharge tube D33, a resistor R149, a resistor R151, a resistor R154, a resistor R156, a resistor R148, a resistor R150, a capacitor C160, a capacitor C161, a common-mode inductor L17, a common-mode inductor L18 and a PHY chip circuit are arranged on the TOP layer; the capacitor C359, the capacitor C356, the capacitor C357, the resistor R472, the resistor R473 and the resistor R471 are arranged on the BOTTOM layer; two groups of differential lines of the Ethernet port circuit are connected with the common mode interference suppression circuit and then are connected to a transformer U27 of the network isolation transformation circuit, and a primary center tap of a transformer U27 is connected to the BOB-Smith circuit and the GDT bleeder circuit through a via hole (the diameter of the via hole is not less than 20 mil).
(2) A ground pin of a gas discharge tube D33 in the GDT bleeder circuit and a ground pin of a capacitor C359 in the BOB-Smith circuit are directly connected to a ground pin of an RJ45 grid socket CN1 in the Ethernet port circuit, the ground pin of the RJ45 grid socket CN1 is connected to a first GND layer and a second GND layer through via holes (the diameter of the via holes is not less than 20mil), and the ground pins of the capacitor C356, the capacitor C357, the resistor R149, the resistor R154, the capacitor C160 and the capacitor C161 are connected to the first GND layer and the second GND layer through via holes; the ground pins of the two parts are not directly connected (isolated from the attribute for short) between the TOP layer and the BOTTOM layer, and are connected through the first GND layer and the second GND layer. This kind of mode can make the ethernet mouth when carrying out the ESD experiment for inside (PHY chip circuit) of mainboard can directly not got into to ESD interference current, preferentially releases the casing through peripheral interface and screw hole, reduces the interference to inside chip. Meanwhile, the first GND layer and the second GND layer keep complete ground planes, so that ground impedance is avoided, and the possibility of radiation problems caused by high-frequency signals is reduced.
(3) The ground pin of the RJ45 socket CN1 of the Ethernet port circuit is connected with the first GND layer and the second GND layer and cannot be divided by a power supply and the like; reducing the coupling of common mode interference to the power supply and then radiating out through the interface.
(4) The resistor R520, the resistor R521, the resistor R522, the resistor R523, the resistor R472, the resistor R473 and the resistor R471 are packaged in a 0603 packaging mode, a 0805 packaging mode or a 1206 packaging mode, and are in a packaging structure of at least 0603 and above, so that breakdown caused by surge pulse can be avoided.
(5) In the first and second embodiments, the package positions of the resistor R520, the resistor R521, the resistor R522, and the resistor R523 are compatible with the package positions of the common mode inductor L17 and the common mode inductor L18, and the replacement of the first and second embodiments is realized by replacing the corresponding positions, so that the operation is simple and convenient, and the mode of using the series resistors (R520, R521, R522, and R523) or the series common mode inductors (L17 and L18) to suppress interference can be selected and used autonomously according to the actual EMC test condition without changing the PCB structure and affecting the communication quality.
(6) The resistance values of the resistor R520, the resistor R521, the resistor R522 and the resistor R523 are not more than 10 ohms, and the communication quality of the network port is ensured.
(7) Under the condition that a PCB structure is not changed, if the anti-surge grade has higher grade requirements, a mode that a GDT bleeder circuit and a BOB-Smith circuit coexist can be selected to discharge surge energy, and if the cost has strict requirements and the anti-surge grade has low requirements, the BOB-Smith circuit can be selected to discharge the surge energy.
To sum up, the utility model has the advantages as follows:
the invention balances the board-level common-ground and cut-ground design, and research personnel can flexibly select different design schemes according to factors such as product market positioning, lightning protection level requirements, cost requirements and the like under the condition that the PCB structure is not changed; can compatible EMI and the anti-interference problem of solving hundred million net gapes through board level design, pass through the relevant standard requirement of EMC smoothly, saved material cost and cost of labor greatly, directly bring the cost benefit of enterprise, make the product more have market competition demand, promote the product lightning protection grade, expansibility is stronger.
Although specific embodiments of the present invention have been described, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, and that equivalent modifications and variations can be made by those skilled in the art without departing from the spirit of the invention, which is to be limited only by the claims appended hereto.
Claims (10)
1. An EMC testing arrangement of hundred mega Ethernet mouth which characterized in that: the LED lamp control circuit comprises an Ethernet port circuit, a common mode interference suppression circuit, a network isolation transformation circuit, a BOB-Smith circuit, an LED lamp configuration circuit and a PHY chip circuit, wherein the Ethernet port circuit is respectively connected with the common mode interference suppression circuit and the LED lamp configuration circuit, the network isolation transformation circuit is respectively connected with the common mode interference suppression circuit, the BOB-Smith circuit and the PHY chip circuit, and the PHY chip circuit is connected to the LED lamp configuration circuit.
2. The EMC test apparatus of a hundred mega ethernet port as claimed in claim 1, wherein: the device also comprises a GDT bleeder circuit, wherein the GDT bleeder circuit is connected with the network isolation transformer circuit.
3. The EMC test apparatus of a hundred mega ethernet port as claimed in claim 2, wherein: the Ethernet port circuit comprises an RJ45 port seat CN1, a first pin, a second pin, a third pin and a sixth pin of the RJ45 port seat CN1 are all connected to a common mode interference suppression circuit, a ninth pin, a tenth pin, an eleventh pin and a twelfth pin of the RJ45 port seat CN1 are all connected to an LED lamp configuration circuit, a G1 pin and a G2 pin of the RJ45 port seat CN1 are all grounded, and a fourth pin, a fifth pin, a seventh pin and an eighth pin of the RJ45 port seat CN1 are all suspended.
4. The EMC testing apparatus of a hundred mega Ethernet port as claimed in claim 3, wherein: the common mode interference suppression circuit comprises a common mode inductor L17 and a common mode inductor L18, a fourth pin of the common mode inductor L17 is connected with a first pin of the Ethernet port circuit, a first pin of the common mode inductor L17 is connected with a second pin of the Ethernet port circuit, a fourth pin of the common mode inductor L18 is connected with a third pin of the Ethernet port circuit, and a first pin of the common mode inductor L18 is connected with a sixth pin of the Ethernet port circuit; a third pin and a second pin of the common mode inductor L17 and a third pin and a second pin of the common mode inductor L18 are respectively connected with corresponding pins in the network isolation transformation circuit;
or the circuit for suppressing common mode interference includes a resistor R520, a resistor R521, a resistor R522, and a resistor R523, where one end of the resistor R520 is connected to the first pin of the ethernet port circuit, one end of the resistor R521 is connected to the second pin of the ethernet port circuit, one end of the resistor R522 is connected to the third pin of the ethernet port circuit, and one end of the resistor R523 is connected to the sixth pin of the ethernet port circuit; the other end of the resistor R520, the other end of the resistor R521, the other end of the resistor R522 and the other end of the resistor R523 are respectively connected with corresponding pins in the network isolation voltage transformation circuit;
or the common mode interference suppression circuit comprises a common mode inductor L17, a common mode inductor L18, a resistor R520, a resistor R521, a resistor R522 and a resistor R523, a fourth pin of the common mode inductor L17 is connected to a first pin of the ethernet port circuit, a first pin of the common mode inductor L17 is connected to a second pin of the ethernet port circuit, a fourth pin of the common mode inductor L18 is connected to a third pin of the ethernet port circuit, and a first pin of the common mode inductor L18 is connected to a sixth pin of the ethernet port circuit; the third pin of the common mode inductor L17, the second pin of the common mode inductor L17, the third pin of the common mode inductor L18, and the second pin of the common mode inductor L18 are respectively connected to one end of a resistor R520, one end of a resistor R521, one end of a resistor R522, and one end of a resistor R523, and the other end of the resistor R520, the other end of the resistor R521, the other end of the resistor R522, and the other end of the resistor R523 are respectively connected to corresponding pins in the network isolation transformer circuit.
5. The EMC testing apparatus of a hundred mega Ethernet port as claimed in claim 4, wherein: the network isolation transformation circuit comprises a transformer U27, a capacitor C356 and a capacitor C357, wherein a sixteenth pin, a fourteenth pin, an eleventh pin and a ninth pin of the transformer U27 are respectively connected with pins/ports corresponding to the common mode interference suppression circuit, a fifteenth pin and a tenth pin of the transformer U27 are both connected with a BOB-Smith circuit, a second pin of the transformer U27 is connected with one end of the capacitor C356, a seventh pin of the transformer U27 is connected with one end of the capacitor C357, the other end of the capacitor C356 and the other end of the capacitor C357 are both grounded, a first pin, a third pin, a sixth pin and an eighth pin of the transformer U27 are all connected to the PHY chip circuit, and a fourth pin, a fifth pin, a twelfth pin and a thirteenth pin of the transformer U27 are all suspended.
6. The EMC testing apparatus of a hundred mega Ethernet port as claimed in claim 5, wherein: the BOB-Smith circuit comprises a capacitor C359, a resistor R472 and a resistor R473, wherein one end of the resistor R472 is connected with the tenth pin of the network isolation transformation circuit, one end of the resistor R473 is connected with the fifteenth pin of the network isolation transformation circuit, the other end of the resistor R472 and the other end of the resistor R473 are both connected to one end of the capacitor C359, and the other end of the capacitor C359 is grounded.
7. The EMC testing apparatus of a hundred mega Ethernet port as claimed in claim 6, wherein: the GDT bleeder circuit comprises a gas discharge tube D33 and a resistor R471, one end of the gas discharge tube D33 and one end of the resistor R471 are both connected to the tenth pin of the network isolation transformer circuit, the other end of the resistor R471 is connected to the fifteenth pin of the network isolation transformer circuit, and the other end of the gas discharge tube D33 is grounded.
8. The EMC test apparatus of a hundred mega ethernet port as claimed in claim 7, wherein: the LED lamp configuration circuit comprises a resistor R149, a resistor R151, a resistor R154, a resistor R156, a resistor R148, a resistor R150, a capacitor C160 and a capacitor C161, one end of the capacitor C160, one end of the resistor R149 and one end of the resistor R150 are connected to the tenth pin of the ethernet port circuit, one end of the resistor R151, one end of the capacitor C161 and one end of the resistor R148 are all connected to the eleventh pin of the ethernet port circuit, one end of the resistor R154 is connected to the ninth pin of the ethernet port circuit, one end of the resistor R156 is connected to the twelfth pin of the ethernet port circuit, the other end of the resistor R148 and the other end of the resistor R150 are both connected to the PHY chip circuit, the other end of the resistor R151 and the other end of the resistor R156 are connected to a power supply, and the other end of the resistor R149, the other end of the resistor R154, the other end of the capacitor C160 and the other end of the capacitor C161 are all grounded.
9. The EMC test apparatus of a hundred mega ethernet port as claimed in claim 8, wherein: the resistance values of the resistor R520, the resistor R521, the resistor R522 and the resistor R523 are not more than 10 ohms; the resistor R520, the resistor R521, the resistor R522, the resistor R523, the resistor R472, the resistor R473 and the resistor R471 are packaged in a 0603 packaging mode, a 0805 packaging mode or a 1206 packaging mode.
10. The EMC test apparatus of a hundred mega ethernet port as claimed in claim 8, wherein: the PCB is provided with six layers, namely a TOP layer, a first GND layer, a VCC layer, a signal layer, a second GND layer and a BOTTOM layer from TOP to BOTTOM, the RJ45 gateway seat CN1, a resistor R520, a resistor R521, a resistor R522, a resistor R523, a transformer U27, a gas discharge tube D33, a resistor R149, a resistor R151, a resistor R154, a resistor R156, a resistor R148, a resistor R150, a capacitor C160, a capacitor C161, a common-mode inductor L17, a common-mode inductor L18 and a PHY chip circuit are arranged on the TOP layer, and the capacitor C359, the capacitor C356, the capacitor C357, the resistor R472, the resistor R473 and the resistor R471 are arranged on the BOTTOM layer; the ground pin of the gas discharge tube D33 and the ground pin of the capacitor C359 are directly connected to the ground pin of the RJ45 socket CN1, and the RJ45 socket CN1, the capacitor C356, the capacitor C357, the resistor R149, the resistor R154, the capacitor C160, the capacitor C161 and the ground pin of the PHY chip are all connected to the first GND layer and the second GND layer through via holes.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922105614.7U CN212111600U (en) | 2019-11-29 | 2019-11-29 | One hundred mega Ethernet port EMC testing device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922105614.7U CN212111600U (en) | 2019-11-29 | 2019-11-29 | One hundred mega Ethernet port EMC testing device |
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| CN212111600U true CN212111600U (en) | 2020-12-08 |
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| CN201922105614.7U Active CN212111600U (en) | 2019-11-29 | 2019-11-29 | One hundred mega Ethernet port EMC testing device |
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| CN (1) | CN212111600U (en) |
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