CN212084982U - Resistor device structure - Google Patents
Resistor device structure Download PDFInfo
- Publication number
- CN212084982U CN212084982U CN202021102854.8U CN202021102854U CN212084982U CN 212084982 U CN212084982 U CN 212084982U CN 202021102854 U CN202021102854 U CN 202021102854U CN 212084982 U CN212084982 U CN 212084982U
- Authority
- CN
- China
- Prior art keywords
- metal contact
- contact
- metal
- substrate
- trench isolation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The utility model provides a resistance device structure, include: the substrate, the substrate includes shallow trench isolation region, the polycrystalline silicon layer above the shallow trench isolation region to and at least one contact structure, contact structure includes: the first metal contact is positioned on the polycrystalline silicon layer, the second metal contact is positioned on the substrate, and the first metal contact is connected with the second metal contact. Therefore, the first metal contact is arranged on the polycrystalline silicon layer, the second metal contact is arranged on the substrate, and the first metal contact and the second metal contact are connected together, so that heat on the polycrystalline silicon layer is transferred to the substrate through the first metal contact and the second metal contact, the temperature of the polycrystalline silicon layer is reduced by utilizing the heat conductivity of the metal and the heat dissipation capacity of the substrate, and the stability of the resistance is improved.
Description
Technical Field
The utility model relates to the field of semiconductor technology, in particular to resistor device structure.
Background
The resistor is the most used electronic component in the electronic circuit, and the role of the resistor in the circuit is as follows: reduced voltage, distributed voltage, limited current, etc.
At present, a resistor which is commonly used is a polysilicon resistor, but the resistance value of the polysilicon resistor has instability under the action of high temperature, and particularly when the resistor is in a circuit with instantaneous large current, the instantaneous temperature of the resistor of the polysilicon layer can be increased under the instantaneous large current due to the joule heating effect, so that the resistance value of the resistor is increased and even burnt out.
SUMMERY OF THE UTILITY MODEL
In view of this, the present invention provides a resistor structure, which improves the resistance stability of the resistor during transient large current.
In order to achieve the above purpose, the utility model has the following technical proposal:
a resistive device structure, comprising:
the substrate comprises a shallow trench isolation region and a polycrystalline silicon layer above the shallow trench isolation region;
at least one of the following contact structures;
each of the contact structures includes a first metal contact and a second metal contact;
the first metal contact is located on the polycrystalline silicon layer, the second metal contact is located on the substrate, and the first metal contact is connected with the second metal contact.
Optionally, a reverse bias PN junction is connected between the second metal contact and the substrate.
Optionally, the number of the second metal contacts is at least two;
the second metal contact being located on the substrate comprises:
the two second metal contacts are respectively positioned on the substrate at the opposite sides of the shallow trench isolation region.
Optionally, the contact structure includes at least two of: a first contact structure and a second contact structure;
the first contact structure includes at least: one first metal contact and two second metal contacts, wherein the two second metal contacts are respectively positioned at the opposite sides of the shallow trench isolation region, and the one first metal contact is connected with the two second metal contacts;
the second contact structure includes at least: the first metal contact is connected with the second metal contact, the second metal contacts are respectively arranged on the opposite sides of the shallow trench isolation region, and the first metal contact is connected with the second metal contacts.
Optionally, the connecting the first metal contact and the second metal contact includes:
the first metal contact is connected with the second metal contact through a metal connecting line layer.
Optionally, the method further includes: a third metal contact and a fourth metal contact, the third metal contact and the fourth metal contact located on the polysilicon layer, the third metal contact connected to a first voltage, the fourth metal contact connected to a second voltage.
Optionally, the at least one contact structure is located between the third metal contact and the fourth metal contact.
Optionally, the first metal contact, the second metal contact, the third metal contact, and the fourth metal contact are made of the same material and have the same size.
Optionally, the area of the polysilicon layer is smaller than the area of the shallow trench isolation region.
Optionally, the shallow trench isolation region is a silicon dioxide layer.
The embodiment of the utility model provides a pair of resistance device structure, include: the substrate, the substrate includes shallow trench isolation region, the polycrystalline silicon layer above the shallow trench isolation region to and at least one contact structure, each contact structure all includes: the first metal contact is positioned on the polycrystalline silicon layer, the second metal contact is positioned on the substrate, and the first metal contact is connected with the second metal contact. Therefore, the first metal contact is arranged on the polycrystalline silicon layer, the second metal contact is arranged on the substrate, and the first metal contact and the second metal contact are connected together, so that heat on the polycrystalline silicon layer is transferred to the substrate through the first metal contact and the second metal contact, the temperature of the polycrystalline silicon layer is reduced by utilizing the heat conductivity of the metal and the heat dissipation capacity of the substrate, and the stability of the resistance is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 shows a schematic diagram of a resistor device structure according to an embodiment of the invention;
fig. 2 shows a schematic diagram of a resistor device structure according to an embodiment of the present invention.
Detailed Description
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be embodied in other specific forms other than those described herein, and it will be apparent to those skilled in the art that the present invention may be practiced without departing from the spirit and scope of the invention.
As described in the background art, the resistance of the polysilicon resistor is unstable at a high temperature, and especially in a circuit with a transient large current, due to the joule heat effect, the transient temperature of the resistor at the transient large current increases, which causes the resistance of the resistor to become large and even burn out.
To this end, an embodiment of the present application provides a resistance device structure, including: the substrate, the substrate includes shallow trench isolation region, the polycrystalline silicon layer above the shallow trench isolation region to and at least one contact structure, each contact structure all includes: the first metal contact is positioned on the polycrystalline silicon layer, the second metal contact is positioned on the substrate, and the first metal contact is connected with the second metal contact. Therefore, the first metal contact is arranged on the polycrystalline silicon layer, the second metal contact is arranged on the substrate, and the first metal contact and the second metal contact are connected together, so that heat on the polycrystalline silicon layer is transferred to the substrate through the first metal contact and the second metal contact, the temperature of the polycrystalline silicon layer is reduced by utilizing the heat conductivity of the metal and the heat dissipation capacity of the substrate, and the stability of the resistance is improved.
In order to facilitate understanding of the technical solutions and effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.
Referring to fig. 1 and 2, the resistive device structure includes:
a substrate 100, the substrate 100 including a shallow trench isolation region 110, a polysilicon layer 120 over the shallow trench isolation region 110;
at least one contact structure 130 of:
each contact structure 130 includes a first metal contact 131 and a second metal contact 132;
a first metal contact 131 is located on the polysilicon layer 120, a second metal contact 132 is located on the substrate 100, and the first metal contact 131 and the second metal contact 132 are connected.
In the embodiment of the present application, the substrate 100 may be a semiconductor substrate, and for example, may be a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or a GOI (Germanium On Insulator) or the like. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP, SiC, or the like, may also be a stacked structure, such as Si/SiGe, or the like, and may also be other epitaxial structures, such as SGOI (silicon germanium on insulator) or the like.
Shallow trench isolation regions 110 are formed in the substrate 100, and the area of the shallow trench isolation regions 110 is smaller than that of the substrate 100 to separate active regions in the substrate 100. For example, a trench may be formed in the substrate 100 and then filled with an isolation dielectric, which may be silicon dioxide. A polysilicon layer 120 is formed above the shallow trench isolation region 110, and the area of the polysilicon layer 120 is smaller than that of the shallow trench isolation region 110, but the resistance of the polysilicon layer 120 is unstable, and the higher the temperature is, the worse the resistance stability is. Particularly in a circuit with instantaneous large current, the instantaneous temperature of the polysilicon layer is increased due to joule heat effect, so that the resistance value of the resistor device is increased and even burnt out.
In the embodiment of the present application, in order to reduce joule heat of an instantaneous large current, lower the temperature of the polysilicon layer, and improve the stability of the device under the large current condition, a plurality of contact structures 130 are disposed in the resistor device structure, each contact structure 130 includes a first metal contact 131 and a second metal contact 132, the first metal contact 131 is located on the polysilicon layer 120, the second metal contact 132 is located on the substrate 100, and the first metal contact 131 is connected to the second metal contact 132. The heat on the polysilicon layer 120 is transferred to the substrate 100 through the first metal contact 131 and the second metal contact 132 electrically connected to the first metal contact 131, so that the heat transferred to the substrate 100 is quickly lost due to the strong heat dissipation capability of the substrate 100. And because the metal contact has good thermal conductivity, the heat on the polysilicon layer 120 can be transferred to the substrate 100 through the metal contact, so that the heat of the polysilicon layer 120 is effectively reduced, the temperature of the polysilicon layer 120 is reduced, and the resistance stability of the device is improved by utilizing the good electrical conductivity of the metal contact and the strong heat dissipation capacity of the substrate 100. In this embodiment, the first metal contact 131 and the second metal contact 132 may be connected through a metal wiring layer 133.
In this embodiment, a reverse biased PN junction 160 is connected between the second metal contact 132 and the substrate 100. When a plurality of contact structures are disposed in the resistor device, the second metal contact 132 of each contact structure may be connected to the same reverse biased PN junction, and the second metal contact 132 of each contact structure may also be connected to different reverse biased PN junctions. When the n-type semiconductor and the p-type semiconductor are contacted, holes in the p-type semiconductor flow to the n-type semiconductor, and electrons in the n-type semiconductor flow to the p-type semiconductor, so that a space charge region is formed at the p-n contact boundary. When the direction of the applied electric field is directed from the n-type semiconductor to the p-type semiconductor, the p-n is in a reverse off state, and the current of the polysilicon layer 120 is difficult to be transmitted into the substrate 100 through the second metal contact 132, and is in an off state. A reverse biased PN junction 160 may be formed in the substrate 100 region of the second metal contact 132. Specifically, if a positive voltage is applied to the resistor device during operation, the second metal contact 132 is connected to the n-type substrate, and if a negative voltage is applied to the resistor device during operation, the second metal contact 132 is connected to the p-type substrate, so that it can be ensured that a PN junction connected to the second metal contact 132 is in a reverse bias cut-off state during operation of the resistor device.
In this embodiment, the number of the second metal contacts 132 is at least two, each of the second metal contacts 132 is connected to the first metal contact 131, and heat on the polysilicon layer 120 is transferred to the substrate 100 through the plurality of second metal contacts 132, thereby improving the heat transfer efficiency. Taking the number of the second metal contacts 132 as two for example, the two second metal contacts 132 are respectively located on the substrate 100 at opposite sides of the shallow trench isolation region 110, that is, the two second metal contacts 132 are respectively located at two sides of the first metal contact 131, the two second metal contacts 132 may be located on the same straight line as the first metal contact 131, and the two first metal contacts 132 may also be located on different straight lines from the first metal contact 131.
In this embodiment, the contact structure 130 may include at least two of the following: a first contact structure and a second contact structure; the first contact structure includes at least: a first metal contact 131, two second metal contacts 132 respectively located at opposite sides of the shallow trench isolation region 110, the first metal contact 131 and the second metal contacts 132 being connected; the second contact structure includes at least: one first metal contact 131, two second metal contacts 132 respectively located at opposite sides of the shallow trench isolation region 110, and one first metal contact 131 and two second metal contacts 132 connected. The following detailed description describes the contact structure including a first contact structure and a second contact structure, the first contact structure and the second contact structure may be the same, the first contact structure includes a first metal contact 131 and two second metal contacts 132, the two second metal contacts 132 are respectively located at opposite sides of the shallow trench isolation 110, that is, the two second metal contacts 132 are located at two sides of the first metal contact 131, and the two second metal contacts 132 and the first metal contact 131 are electrically connected through a metal interconnect layer 133, so that heat in the polysilicon layer 120 can be transferred to the substrate 100 through the first metal contact 131 and the second metal contacts 132. The second contact structure includes a first metal contact 131 and two second metal contacts 132, the two second metal contacts 132 are respectively located at opposite sides of the shallow trench isolation region 110, that is, the two second metal contacts 132 are located at two sides of the first metal contact 131, and the two second metal contacts 132 and the first metal contact 131 are electrically connected through a metal interconnection line, so that heat in the polysilicon layer 120 is transferred into the substrate 100 through the first metal contact 131 and the second metal contacts 132. In this way, the heat in the polysilicon layer 120 may be transferred into the substrate through the first contact structure and the second contact structure, and when a plurality of contact structures are provided, the heat in the polysilicon layer 120 may be transferred into the substrate 100 through the plurality of contact structures, thereby improving the efficiency of heat transfer. In this embodiment, the second metal contacts 132 on the same side of the shallow trench isolation region 110 may be connected to the same reverse biased PN junction, or may be connected to different reverse biased PN junctions.
In this embodiment, a third metal contact 151 and a fourth metal contact 152 are disposed above the polysilicon layer 120, the third metal contact 151 may be electrically connected to contacts of other interconnects or other devices through a third metal interconnect 153, and the fourth metal contact 152 may be electrically connected to contacts of other interconnects or other devices through a fourth metal interconnect 154. The third metal contact 151 is connected to a first voltage and the fourth metal contact 152 is connected to a second voltage, thereby generating a current on the polysilicon layer 120.
In this embodiment, all the contact structures are located between the third metal contact 151 and the fourth metal contact 152, so that the contact structures are uniformly distributed on the polysilicon layer 120, and heat on the polysilicon layer 120 is uniformly transferred into the substrate 100. In a specific embodiment, the first metal contact 131, the second metal contact 132, the third metal contact 151, and the fourth metal contact 152 may have the same material and size, and the first metal contact 131, the second metal contact 132, the third metal contact 151, and the fourth metal contact 152 may be formed in the same process, so as to simplify the process and improve the process efficiency.
As described in detail above for the resistor device provided in the embodiment of the present application, the first metal contact is disposed on the polysilicon layer, the second metal contact is disposed on the substrate, and the first metal contact and the second metal contact are connected together, so that heat on the polysilicon layer is transferred to the substrate through the first metal contact and the second metal contact, and the temperature of the polysilicon layer is reduced and the stability of the resistor is improved by using the thermal conductivity of the metal and the heat dissipation capability of the substrate.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments.
The above description is only for the preferred embodiment of the present invention, and although the present invention has been disclosed in the preferred embodiments, it is not intended to limit the present invention. The invention is not limited to the embodiments described herein, but is capable of other embodiments according to the invention, and may be used in various other applications, including, but not limited to, industrial. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical substance of the present invention all fall within the protection scope of the technical solution of the present invention.
Claims (10)
1. A resistive device structure, comprising:
the substrate comprises a shallow trench isolation region and a polycrystalline silicon layer above the shallow trench isolation region;
at least one of the following contact structures;
each of the contact structures includes a first metal contact and a second metal contact;
the first metal contact is located on the polycrystalline silicon layer, the second metal contact is located on the substrate, and the first metal contact is connected with the second metal contact.
2. The structure of claim 1, wherein a reverse biased PN junction is connected between said second metal contact and said substrate.
3. The structure of claim 1, wherein the number of second metal contacts is at least two;
the second metal contact being located on the substrate comprises:
the two second metal contacts are respectively positioned on the substrate at the opposite sides of the shallow trench isolation region.
4. The structure of claim 1, wherein the contact structure comprises at least two of: a first contact structure and a second contact structure;
the first contact structure includes at least: one first metal contact and two second metal contacts, wherein the two second metal contacts are respectively positioned at the opposite sides of the shallow trench isolation region, and the one first metal contact is connected with the two second metal contacts;
the second contact structure includes at least: the first metal contact is connected with the second metal contact, the second metal contacts are respectively arranged on the opposite sides of the shallow trench isolation region, and the first metal contact is connected with the second metal contacts.
5. The structure of claim 1, wherein the first metal contact being connected to the second metal contact comprises:
the first metal contact is connected with the second metal contact through a metal connecting line layer.
6. The structure of any one of claims 1-5, further comprising: a third metal contact and a fourth metal contact, the third metal contact and the fourth metal contact located on the polysilicon layer, the third metal contact connected to a first voltage, the fourth metal contact connected to a second voltage.
7. The structure of claim 6, wherein the at least one contact structure is located between the third metal contact and the fourth metal contact.
8. The structure of claim 6, wherein the first metal contact, the second metal contact, the third metal contact, and the fourth metal contact are all the same in material and dimensions.
9. The structure of any of claims 1-5, wherein the area of the polysilicon layer is smaller than the area of the shallow trench isolation region.
10. The structure of any of claims 1-5, wherein the shallow trench isolation region is a silicon dioxide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021102854.8U CN212084982U (en) | 2020-06-15 | 2020-06-15 | Resistor device structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021102854.8U CN212084982U (en) | 2020-06-15 | 2020-06-15 | Resistor device structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212084982U true CN212084982U (en) | 2020-12-04 |
Family
ID=73557184
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021102854.8U Active CN212084982U (en) | 2020-06-15 | 2020-06-15 | Resistor device structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN212084982U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112951806A (en) * | 2021-02-23 | 2021-06-11 | 长江存储科技有限责任公司 | Semiconductor structure and method for determining step height of semiconductor structure |
| CN116053261A (en) * | 2023-01-28 | 2023-05-02 | 微龛(广州)半导体有限公司 | High-precision thin film resistor device and preparation method thereof |
-
2020
- 2020-06-15 CN CN202021102854.8U patent/CN212084982U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112951806A (en) * | 2021-02-23 | 2021-06-11 | 长江存储科技有限责任公司 | Semiconductor structure and method for determining step height of semiconductor structure |
| CN112951806B (en) * | 2021-02-23 | 2023-12-01 | 长江存储科技有限责任公司 | Semiconductor structure and method for determining step height of semiconductor structure |
| CN116053261A (en) * | 2023-01-28 | 2023-05-02 | 微龛(广州)半导体有限公司 | High-precision thin film resistor device and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103681866B (en) | Field-effect semiconductor device and manufacture method thereof | |
| US2721965A (en) | Power transistor | |
| CN102738245B (en) | Diodes with embedded dummy gate electrodes | |
| CN212084982U (en) | Resistor device structure | |
| CN103456790B (en) | Vertical power mosfet and forming method thereof | |
| CN103811484A (en) | ESD Devices Comprising Semiconductor Fins | |
| CN104253163A (en) | Schottky diode structure | |
| CN104217936A (en) | Method for Producing a Semiconductor Component | |
| CN107887431A (en) | Power semiconductor arrangement | |
| US2994018A (en) | Asymmetrically conductive device and method of making the same | |
| US3878553A (en) | Interdigitated mesa beam lead diode and series array thereof | |
| CN102456678B (en) | Igbt module and circuit | |
| US6448589B1 (en) | Single side contacts for a semiconductor device | |
| TWI485780B (en) | High breakdown voltage diode and method of forming same | |
| CN108630362B (en) | Resistance element with increased voltage and resistance value | |
| CN109065541B (en) | Bidirectional transient voltage suppressor and preparation method thereof | |
| WO2011048580A1 (en) | Surge protection device | |
| CN215955286U (en) | Semiconductor discharge tube and overvoltage protection device | |
| CN215955287U (en) | Semiconductor discharge tube and overvoltage protection device | |
| CN111916423A (en) | Anti-fuse memory cell and method of forming the same | |
| CN217239465U (en) | Integrated grid resistance structure | |
| KR102549143B1 (en) | semiconductor thermoelectric generator | |
| CN109638012B (en) | Bidirectional protection chip and preparation method thereof | |
| CN209785928U (en) | Anti-fuse memory cell | |
| JP2002094046A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |