CN212084128U

CN212084128U - Server redundant clock system capable of being maintained in hot mode

Info

Publication number: CN212084128U
Application number: CN201922443917.XU
Authority: CN
Inventors: 何业缘
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2019-12-30
Filing date: 2019-12-30
Publication date: 2020-12-04
Anticipated expiration: 2029-12-30

Abstract

The embodiment of the utility model discloses but redundant clock system of hot maintenance's server, including clock gating ware, clock buffer and a plurality of clock board, every clock board all includes clock generator and golden finger, a plurality of clock boards all are connected to on the mainboard through the connector, clock gating ware and clock buffer are connected gradually to the clock board. The utility model relates to a clock board is connected to the mainboard with the clock board through the connector on, only places the connector on the mainboard, two can satisfy the requirement during in-service use, reduce the area that the clock generator occupy mainboard PCB. And after the clock board fails, automatically switching to a new clock source to provide a clock signal for the system, so as to realize a fault self-recovery function. Only one clock board is electrified to work at a time, and the power consumption of the system can be reduced. In addition, theoretically, the fault clock board can be replaced for infinite times, and the stability of the system can be greatly improved.

Description

Server redundant clock system capable of being maintained in hot mode

Technical Field

The utility model belongs to the technical field of computer clock design technique and specifically relates to a but redundant clock system of server of hot maintenance.

Background

The clock signal is the basis of the server sequential logic, which determines when the state in the logic unit is updated, and is a semaphore with a fixed period. The clock system is an important component of the server and provides clock signals for a CPU, a PCH, PCIe and the like in the server. The stability of the clock system directly determines the stability of the server system, and once the clock system fails, serious failures such as downtime of the server system can be directly caused, and heavy loss is caused to users.

In order to improve the stability of the server clock system, a redundant clock design is usually adopted, i.e. a plurality of clock generators are placed on a server mainboard, and when a main clock generator fails, a standby clock generator is automatically switched to provide a clock signal for the system. But limited to PCB area, typically no more than 3 clock generators are placed simultaneously. Then, when all 3 clock generators fail, the server system cannot continue to operate normally. Meanwhile, since power needs to be supplied to each clock generator, energy waste may be caused.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides an in provide a but redundant clock system of server of hot maintenance to solve the problem that current redundant clock system scheme occupies that the PCB space is big, unable restoration, extravagant energy.

In order to solve the technical problem, the embodiment of the utility model discloses following technical scheme:

the utility model provides a but redundant clock system of server of hot maintenance, the system includes clock gating ware, clock buffer and a plurality of clock board, and every clock board all includes clock generator and golden finger, a plurality of clock boards all are connected to on the mainboard through the connector, clock gating ware and clock buffer are connected gradually to the clock board.

Further, the clock board comprises two clock boards which are redundant with each other.

Furthermore, the system also comprises a CPLD, wherein the CPLD is respectively connected with the clock gate and the power supply unit, and the power supply unit has the same number with the clock board and respectively supplies power to the clock board.

Furthermore, the power supply unit is connected with the golden finger and supplies power to the clock board through the golden finger.

Further, the system also comprises a BMC which is connected with the clock gate.

Further, the clock buffer is also connected with the CPU and the PCIE.

The effects provided in the contents of the present invention are only the effects of the embodiments, not all the effects of the present invention, and one of the above technical solutions has the following advantages or advantageous effects:

the design clock board, through the connector with clock board connection to the mainboard on, only place the connector on the mainboard, two can satisfy the requirement during in-service use, reduce the area that the clock generator occupies mainboard PCB. And after the clock board fails, automatically switching to a new clock source to provide a clock signal for the system, so as to realize a fault self-recovery function. Only one clock board is electrified to work at a time, and the power consumption of the system can be reduced. In addition, theoretically, the fault clock board can be replaced for infinite times, and the stability of the system can be greatly improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a clock board according to the present invention;

fig. 2 is a schematic diagram of the system of the present invention;

in the figure, 1 clock Generator CLK GEN, 11 clock board connector CLK Generator Conn 1, 12 clock board connector CLK Generator Conn2, 21 power supply chip VR1, 22 power supply chip VR2, 3 clock gate CLK Switch, 4CPLD, 5BMC, 6 clock Buffer CLK Buffer, 7CPU, 8PCIe, 9 Gold Finger.

Detailed Description

In order to clearly illustrate the technical features of the present invention, the present invention is explained in detail by the following embodiments in combination with the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. In order to simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and processes are omitted so as to not unnecessarily limit the invention.

As shown in fig. 1 and 2, the clock board comprises a clock generator CLK GEN1 and a Gold Finger 9. The Gold Finger9 supplies power to a clock generator CLK GEN1, and the clock generator CLK GEN1 outputs a clock signal to the Gold Finger 9.

As shown in fig. 2, the clock Generator CLK GEN is placed on the clock board, and two clock board connectors CLK Generator 111 and CLK Generator 212 are placed on the main board, and each connector may be equipped with one clock board, and the clock board and the connector are connected by gold fingers. The clock signals of the two clock boards are respectively connected to two input channels of the clock gate CLK Switch 3. The clock gate CLK Switch3 has the clock board mounted on the connector CLK Generator 111 as a default clock source and the clock board mounted on the CLK Generator 212 as a spare clock source. Meanwhile, two power supply chips VR 121 and VR 222 are needed to supply power to two clock boards respectively.

The

connectors CLK generators

1, 2 are two identical connectors, to which two identical clock boards can be fitted. Clock signals generated by clock generators on the two clock boards are connected to the main board through connectors and are respectively connected to the first and second input channels of the clock gate CLK Switch 3. The output channel of the clock gate CLK Switch3 is connected to a clock Buffer CLK Buffer 6.

The clock gate CLK Switch3 is coupled to the output channel with the clock signal of the first input channel as the default clock source. Meanwhile, the clock gate CLK Switch3 can monitor the quality of the input clock signal in real time. Once the clock signal quality of the first input channel is monitored to be unable to meet the system requirement, the clock gate CLK Switch3 switches the second input channel on the output channel and closes the link of the first input channel and the output channel, and informs the BMC5 and the CPLD 4.

The CPLD4 can receive the notification of the clock gate CLK Switch3 and count, and control the working state of the power supply chip VR 1/2. The BMC5 may accept the notification from the clock gate CLK Switch3 and count it while prompting the user to replace the clock board.

The utility model discloses but redundant clock system's of hot maintenance's server theory of operation does:

a Clock generator CLK GEN1 and a Gold Finger connector Gold Finger9 are arranged on a Clock board, a Clock Signal sent by the Clock generator is connected to the Gold Finger connector, and meanwhile, a power supply Signal power on the Gold Finger supplies power to the Clock generator.

Two clock board connectors

CLK generators con

1, 2 are provided on the server motherboard, and one clock board,

clock board

1, 2, is mounted on each. The clock board is connected with the connector through a golden finger. The clock board 1 is a default clock source, and the clock board 2 is a standby clock source.

A clock gate CLK Switch3 and a clock Buffer CLK Buffer6 are provided on the server motherboard. The first input channel and the second input channel of the clock gating device are respectively received and transmitted from the first clock board clock signal and the second clock board clock signal, the first input channel is connected to the output channel by default, and the output channel of the first input channel is connected to the clock buffer. The clock gating device can monitor the quality of the input clock signal in real time and automatically switch the output channel. The clock buffer receives the clock signal from the clock gate, and divides the clock signal into multiple paths to provide clock signals for the CPU7, the PCH, the PCIe8 device, and the like.

And a CPLD and a BMC are arranged on the mainboard. The CPLD receives and counts the notification signal from the clock gate and controls the power supply system of the clock board connectors

CLK generators con

1, 2. The BMC is used for receiving the notification signal sent by the clock gating device, counting and notifying a user to replace a fault clock board.

The motherboard is provided with first and second power supply chips VR1 and VR2 for supplying power to the clock board connectors

CLK generators con

1 and 2, respectively, and the opening and closing of the chips are controlled by the CPLD. Wherein the first power supply chip VR1 is turned on by default.

When the default clock source clock board 1 is in fault, the clock gating device detects that the input clock signal can not meet the system requirement, and the clock gating device informs the CPLD. And the CPLD counts 1 after receiving the notification, and turns on a power supply switch of the second power supply chip VR 2.

The clock board 2 starts to work after power supply from the VR2, and outputs a clock signal to a second input channel of the clock gating device.

And after the clock gating device detects that the second input channel has clock signals input, the link between the output channel and the second input channel is closed, the link between the output channel and the first input channel is closed at the same time, and the CPLD and the BMC are informed.

And after receiving the notice of the clock gating device, the CPLD counts 2 and cuts off the power supply output of the first power supply chip VR 1.

After receiving the notification from the clock gate, the BMC counts 1 and notifies the user to replace the first clock board.

And after receiving the notification of the BMC, the user replaces the first clock board. Since the power supply of the first clock board is cut off at this time, the replacement operation can be performed when the server is normally started up.

Similarly, if the second clock board fails, the first clock board becomes the system clock source again, and the user replaces the failed second clock board.

When one clock board is in fault, the system can be automatically switched to another clock board as a clock source to provide a clock signal for the system, and a user can perform hot replacement on the fault clock board.

The above description is only a preferred embodiment of the present invention, and it will be apparent to those skilled in the art that a plurality of modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations are also considered as the protection scope of the present invention.

Claims

1. A server redundant clock system capable of being maintained thermally is characterized by comprising a clock gating device, a clock buffer and a plurality of clock boards, wherein each clock board comprises a clock generator and a golden finger, the clock boards are connected to a main board through connectors, and the clock boards are sequentially connected with the clock gating device and the clock buffer.

2. The thermally serviceable server redundant clock system of claim 1 wherein the clock boards comprise two, redundant to each other.

3. The thermally maintainable server redundant clock system of claim 1 further comprising CPLDs, said CPLDs being connected to a clock gate and a power supply unit, said power supply unit being the same in number as the clock boards and supplying power to the clock boards, respectively.

4. The thermally maintainable server redundant clock system of claim 3 wherein the power supply unit is connected to a golden finger through which the clock board is powered.

5. The thermally maintainable server redundant clock system of claim 1 further comprising a BMC, said BMC coupled to a clock gate.

6. The thermally maintainable server redundant clock system of claim 1 wherein said clock buffer further couples a CPU and a PCIE.