CN212064199U - Integrated chip - Google Patents
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- CN212064199U CN212064199U CN202021333615.3U CN202021333615U CN212064199U CN 212064199 U CN212064199 U CN 212064199U CN 202021333615 U CN202021333615 U CN 202021333615U CN 212064199 U CN212064199 U CN 212064199U
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Abstract
The utility model provides an integrated chip, including video filtering drive module, video coaxial drive-by-wire decoding module and biasing circuit. Specifically, the video filtering driving module and the video coaxial line control decoding module are arranged on the same chip, and the two modules share the same bias circuit. Therefore, on the basis of realizing the functions of video filtering driving and video coaxial line control decoding, the integrated chip also saves the very large space of a Printed Circuit Board (PCB), reduces the cost and has a simple circuit structure.
Description
Technical Field
The utility model relates to a signal processing field especially relates to an integrated chip.
Background
When processing a video signal, the video signal needs to be subjected to video filtering driving and video coaxial line control decoding processing. However, in the prior art, the video filtering drive and the video coaxial line control decoding are respectively realized by two separate modules, and the two modules need to be wired with each other, so that the circuit structure is complex; it is also necessary to separately provide a bias Circuit for supplying a bias voltage thereto, which occupies a large area of a Printed Circuit Board (PCB), and also increases the cost.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing an integrated chip, this integrated chip still saved the very big space of PCB on the basis of the function of realizing video filtering drive and the coaxial drive-by-wire of video and decoding, the cost is reduced, and circuit structure is simple.
In order to solve the above technical problem, the utility model provides an integrated chip, include:
the bias circuit is used for outputting a first bias voltage to the video filtering driving module and outputting a second bias voltage to the video coaxial line control decoding module;
the video filtering driving module is connected with the bias circuit and is used for filtering and gain amplifying the received first video signal under the action of the first bias voltage to obtain a second video signal;
and the video coaxial line control decoding module is connected with the bias circuit and used for extracting a coaxial vector control signal from a mixed signal of the coaxial vector control signal and the second video signal based on a reference voltage under the action of the second bias voltage.
Preferably, the video filtering driving module includes:
the clamping circuit is used for clamping the low voltage of the received first video signal at a fixed voltage under the action of the first bias voltage to obtain an intermediate video signal, and the fixed voltage is greater than the low voltage;
the input end of the first filter is connected with the output end of the clamping circuit and is used for performing first low-pass filtering on the intermediate video signal when a preset level is received to obtain a filtered first intermediate video signal;
the input end of the second filter is connected with the output end of the clamping circuit and is used for carrying out second low-pass filtering on the intermediate video signal when the preset level is received so as to obtain a second filtered intermediate video signal;
the cut-off frequencies of the first filter and the second filter are different;
and the driving module is used for performing gain amplification on the first intermediate video signal or the second intermediate video signal to obtain the second video signal.
Preferably, the video filtering driving module further includes:
and the input end of the NOT gate is connected with the control end of the second filter, and the output end of the NOT gate is connected with the control end of the first filter, and the NOT gate is used for receiving a control level.
Preferably, the first filter and the second filter are both 10 th order filters.
Preferably, the first filter is a filter with a cutoff frequency of 35 MHz.
Preferably, the second filter is a filter with a cut-off frequency of 55 MHz.
Preferably, the driving module is a 6dB driving module.
Preferably, the video coaxial line control decoding module is a comparator formed based on an analog circuit.
Preferably, the bias circuit includes:
the self-starting circuit is used for starting the bias current generating circuit after the self-starting circuit is electrified;
the bias current generating circuit is connected with the output end of the self-starting circuit at a control end and is used for generating initial bias current after starting;
the input end of the first current mirror is connected with the output end of the bias current generating circuit, and the output end of the first current mirror is connected with the video filtering driving module and is used for carrying out first mirroring on the initial bias current to obtain a first bias voltage;
and the second current mirror is used for carrying out second mirror image on the initial bias current to obtain a second bias voltage.
The utility model provides an integrated chip, including video filtering drive module, video coaxial drive-by-wire decoding module and biasing circuit. Specifically, the video filtering driving module and the video coaxial line control decoding module are arranged on the same chip, and the two modules share the same bias circuit. Therefore, on the basis of realizing the functions of video filtering driving and video coaxial line control decoding, the integrated chip also saves the large space of the PCB, reduces the cost and has a simple circuit structure.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required in the prior art and the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an integrated chip according to the present invention;
fig. 2 is a schematic structural diagram of an integrated chip according to the present invention;
fig. 3 is a schematic structural diagram of a clamping circuit in an ic according to the present invention;
fig. 4 is a schematic structural diagram of a bias circuit in an integrated chip according to the present invention.
Detailed Description
The core of the utility model is to provide an integrated chip, this integrated chip still saved the very big space of PCB on the basis of the function of realizing video filtering drive and the coaxial drive-by-wire of video and decoding, the cost is reduced, and circuit structure is simple.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
The utility model provides an integrated chip please refer to fig. 1, fig. 1 is the utility model provides a pair of integrated chip's schematic structure.
The integrated chip includes:
the bias circuit 3 is used for outputting a first bias voltage to the video filtering driving module 1 and outputting a second bias voltage to the video coaxial line control decoding module 2;
the video filtering driving module 1 is connected with the bias circuit 3 and used for filtering and gain amplifying the received first video signal under the action of the first bias voltage to obtain a second video signal;
and the video coaxial line control decoding module 2 is connected with the bias circuit 3 and is used for extracting the coaxial vector control signal from a mixed signal of the coaxial vector control signal and the second video signal based on the reference voltage under the action of the second bias voltage.
It should be noted that, in practical applications, in order to save cost, the second video signal and the coaxial vector control signal are usually mixed and then output through one line, and when the coaxial vector control signal needs to be used separately subsequently, the coaxial vector control signal needs to be extracted from the mixed signal through the video coaxial line-control decoding module 2 under the action of the second bias voltage based on the reference voltage. In addition, the video filtering driving module 1 processes the received first video signal under the action of the first bias voltage to obtain a second video signal.
In the prior art, a video filtering driving module 1 and a video coaxial line control decoding module 2 are respectively arranged on two separate chips, and the two chips need to be wired with each other; in addition, in order to obtain the first bias voltage and the second bias voltage, a bias circuit needs to be respectively arranged on two separate chips to provide the bias voltages, which occupies a large area of the PCB and increases the cost.
In order to solve the above problems, in the present application, the video filtering driving module 1 and the video coaxial line-control decoding module 2 are integrated into one chip, and are connected to the video filtering driving module 1 and the video coaxial line-control decoding module 2 by using a bias circuit 3, wherein the bias circuit 3 provides a first bias voltage for the video filtering driving module 1 and a second bias voltage for the video coaxial line-control decoding module 2, and values of the first bias voltage and the second bias voltage are determined according to actual requirements of the video filtering driving module 1 and the video coaxial line-control decoding module 2. The first bias voltage ensures the normal work of the video filtering driving module 1, and the second bias voltage ensures the normal work of the video coaxial line control decoding module 2. The video filtering driving module 1 carries out filtering and gain amplification processing on a received first video signal under the action of a first bias voltage to obtain a second video signal; the video coaxial line-control decoding module 2 extracts the coaxial vector control signal from the mixed signal of the coaxial vector control signal and the second video signal based on the reference voltage under the action of the second bias voltage.
In conclusion, the integrated chip saves a large space of a PCB (printed Circuit Board) on the basis of realizing the functions of video filtering driving and video coaxial line control decoding, reduces the cost and has a simple circuit structure.
On the basis of the above-described embodiment:
referring to fig. 2, fig. 2 is a schematic diagram of a specific structure of an integrated chip according to the present invention.
As a preferred embodiment, the video filter driving module 1 includes:
the clamp circuit 11 is configured to clamp a low voltage of the received first video signal at a fixed voltage under the action of the first bias voltage to obtain an intermediate video signal, where the fixed voltage is greater than the low voltage;
the first filter 12, the input end of which is connected to the output end of the clamping circuit 11, is configured to perform a first low-pass filtering on the intermediate video signal when receiving a preset level, so as to obtain a filtered first intermediate video signal;
the second filter 13, the input end of which is connected to the output end of the clamping circuit 11, is configured to perform a second low-pass filtering on the intermediate video signal when receiving a preset level, so as to obtain a filtered second intermediate video signal;
the cut-off frequencies of the first filter 12 and the second filter 13 are different;
and the driving module 14, an input end of which is connected to the output ends of the first filter 12 and the second filter 13, is configured to gain amplify the first intermediate video signal or the second intermediate video signal to obtain a second video signal.
In this embodiment, considering that the luminance information of the first video signal is lost when the low voltage of the first video signal is too low, in order to prevent the luminance information of the first video signal from being lost, in this application, the video filter driving module 1 is provided with the clamping circuit 11, and the clamping circuit 11 can clamp the low voltage of the first video signal to a fixed voltage higher than the low voltage, so that the luminance information of the first video signal is not lost, and the dc current to the load is also reduced. The fixed voltage may be, but is not limited to, 97 mV.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a clamping circuit in an ic according to the present invention.
Specifically, the clamp circuit 11 always clamps the low voltage of the input first video signal at 97mV regardless of the magnitude of the low voltage of the first video signal, and when the chip itself is powered on, the clamp circuit 11 IN fig. 3 is turned on, and the resistor R1 IN the clamp circuit 11 provides a voltage drop voltage to the point a of the circuit IN fig. 3, and the voltage drop voltage is transmitted to the input terminal IN through the two small resistors R2 and R3, so as to clamp the low voltage of the first video signal. When the low voltage of the first video signal received by the input end is less than 97mV, the circuit above the point A is conducted, and the circuit below the point A is cut off; when the low voltage of the first video signal received by the input end is more than 97mV, the circuit above the point A is cut off, and the circuit below the point A is conducted.
In addition, in order to obtain video signals with different definitions, in the present application, the video filtering driving module 1 further includes a first filter 12 and a second filter 13 with different cut-off frequencies, where the first filter 12 and the second filter 13 may determine whether to perform low-pass filtering on the intermediate video signal according to whether a preset level is received. When the first filter 12 or the second filter 13 receives a preset level, it performs low-pass filtering on the intermediate video signal and outputs a first intermediate video signal or a second intermediate video signal accordingly; while the filter that does not receive the preset level does not low-pass filter the intermediate video signal. However, since the cutoff frequencies of the first filter 12 and the second filter 13 are different, video signals of different frequencies can be output.
In addition, after the first filter 12 outputs the first intermediate video signal or the second filter 13 outputs the second intermediate video signal, in order to realize driving of the dc or ac load, the video filtering driving module 1 further includes a driving module 14 for performing gain amplification on the first intermediate video signal or the second intermediate video signal, so as to obtain the second video signal.
In summary, the video filtering driving module 1 can realize filtering and gain amplification of the first video signal to drive a dc or ac load, and in addition, can output second video signals with different definitions.
As a preferred embodiment, the video filtering driver module 1 further includes:
and the not gate 4 with an input end connected with the control end of the second filter 13 and an output end connected with the control end of the first filter 12 is used for receiving the control level.
In this embodiment, it is considered that the first filter 12 and the second filter 13 can output intermediate video signals with different frequencies, and normally only one intermediate video signal needs to be output at the same time, that is, only one of the first filter 12 and the second filter 13 is normally operated at the same time.
In order to achieve the above purpose, the present application provides a not gate 4 at the control terminals of the first filter 12 and the second filter 13, wherein the input terminal of the not gate 4 is connected to the control terminal of the second filter 13, and the output terminal of the not gate 4 is connected to the control terminal of the first filter 12. When the control level received by the input end of the not gate 4 is a preset level, the control end of the second filter 13 receives the preset level, and the first filter 12 receives a level obtained by inverting the received control level by the not gate 4, at this time, the second filter 13 works, and the first filter 12 does not work; when the control level received by the input terminal of the not gate 4 is a level opposite to the preset level, the control terminal of the second filter 13 receives a level opposite to the preset level, and the control terminal of the first filter 12 receives a level obtained by inverting the received control level by the not gate 4, that is, the preset level, at this time, the second filter 13 does not work, and the first filter 12 works. In summary, the integrated chip can control the operating states of the two filters according to the received control level, so as to output the video signal required by the user.
As a preferred embodiment, the first filter 12 and the second filter 13 are each a 10 th order filter.
In order to avoid interference to the useful video signal while filtering the intermediate video signal, in this embodiment, the first filter 12 or the second filter 13 is a 10 th order filter, and the attenuation strength of the 10 th order filter is very large, so that the useful video signal is not interfered.
In addition, the first filter 12 or the second filter 13 is not limited to be a 10-order filter, and the filter with several orders is not limited herein.
As a preferred embodiment, the first filter 12 is a filter with a cutoff frequency of 35 MHz.
In this application, the first filter 12 is a filter with a cutoff frequency of 35MHz, and the first intermediate video signal output after the first filter 12 filters the intermediate video signal is an HD (High Definition) video signal, which meets common requirements of users, wherein the frequency band of the HD video signal is 35MHz with a-3 dB bandwidth.
As a preferred embodiment, the second filter 13 is a filter with a cut-off frequency of 55 MHz.
In this application, the second filter 13 is a filter with a cut-off frequency of 55MHz, and the second intermediate video signal output after the second filter 13 filters the intermediate video signal is an FHD (Full High Definition) video signal, which meets common requirements of users, where the frequency band of the FHD video signal is-3 dB bandwidth of 55 MHz.
As a preferred embodiment, the driver module 14 is a 6dB driver module.
In this embodiment, in order to drive a dc or ac coupled single load or a dual load, in this application, the driving module 14 is a 6dB driving module. The 6dB driving module can simultaneously drive a dc or ac coupled load after amplifying the gain of the first intermediate video signal or the second intermediate video signal by 6dB, wherein the ac coupled load can be divided into a single (150 Ω) load or a dual (75 Ω) load.
In addition, the driving module 14 in the present application is not limited to select a 6dB driving module, and which device is selected as the driving module 14 is not limited.
As a preferred embodiment, the video coaxial line-control decoding module 2 is a comparator formed based on an analog circuit.
In this embodiment, the comparator configured based on the analog circuit may extract the on-axis vector control signal from a mixed signal of the on-axis vector control signal and the second video signal under the effect of the first bias voltage based on the reference voltage.
The comparator formed based on the analog circuit also has the advantages of high speed, small rising delay and falling delay, short rising time and falling time, high precision and low offset.
Of course, the video coaxial line-control decoding module 2 in the present application is not limited to a comparator formed by an analog circuit, and which device is selected as the video coaxial line-control decoding module 2 is not limited.
As a preferred embodiment, the bias circuit 3 includes:
a self-starting circuit 31 for starting the bias current generating circuit 32 after self-power-on;
a bias current generating circuit 32 having a control terminal connected to the output terminal of the self-starting circuit 31, for generating an initial bias current after starting;
the first current mirror 33 is used for carrying out first mirror image on the initial bias current to obtain a first bias voltage, and the input end of the first current mirror is connected with the output end of the bias current generating circuit 32, and the output end of the first current mirror is connected with the video filtering driving module 1;
and the second current mirror 34, the input end of which is connected with the output end of the bias current generating circuit 32 and the output end of which is connected with the video coaxial line control decoding module 2, is used for carrying out second mirroring on the initial bias current to obtain a second bias voltage.
In this embodiment, the bias circuit 3 is divided into three parts, which are a self-start circuit 31, a bias current generation circuit 32, and a current mirror. Specifically, the self-starting circuit 31 can start the bias current generating circuit 32 after the chip itself is powered on; after the bias current generating circuit 32 is started, an initial bias current is generated; and then, according to the specific requirements of the video filtering driving module 1 and the video coaxial line-control decoding module 2 on the bias voltage, the current mirror mirrors the initial bias current.
In the application, the bias circuit 3 needs to provide a first bias voltage and a second bias voltage for the video filtering driving module 1 and the video coaxial line-control decoding module 2, so that the current mirror is divided into the first current mirror 33 and the second current mirror 34, and bias voltages are provided for the video filtering driving module 1 and the video coaxial line-control decoding module 2 respectively, so that the two generated bias voltages are not influenced by each other.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a bias circuit in an integrated chip according to the present invention.
Specifically, the self-starting circuit 31 is composed of a plurality of BJTs (Bipolar Junction transistors), and it is considered that after the chip is powered on, along with the rise of voltage, the gate of the BJT in the bias circuit 3 may be set to the power supply voltage due to uncertain starting state, and the self-starting circuit 31 may turn on the switching tube to pull down the gate of the BJT to start the bias current generating circuit 32, and when the bias current generating circuit 32 is started, the self-starting circuit 31 is turned off.
The bias current generating circuit 32 is composed of a plurality of BJTs and amplifiers, wherein the bias currents of the BJTs are proportional to the absolute temperature, so that the initial bias currents generated can increase with the temperature, and specifically, the initial bias currents can be increasedBy the formula
Is given byrefFor the initial bias current, k is the boltzmann constant, T is the ambient temperature value, Q is the number of electronic charges, is a constant, equal to 1.6 × 10e-19, n is the ratio of the number of two BJTs, i.e., the ratio of the number of Q2 to the number of Q1, and R is the resistance of resistor R4. It can be seen that the initial bias current is proportional to absolute temperature. The initial bias current in the present application may be 20 μ a, among others.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. An integrated chip, comprising:
the bias circuit is used for outputting a first bias voltage to the video filtering driving module and outputting a second bias voltage to the video coaxial line control decoding module;
the video filtering driving module is connected with the bias circuit and is used for filtering and gain amplifying the received first video signal under the action of the first bias voltage to obtain a second video signal;
and the video coaxial line control decoding module is connected with the bias circuit and used for extracting a coaxial vector control signal from a mixed signal of the coaxial vector control signal and the second video signal based on a reference voltage under the action of the second bias voltage.
2. The integrated chip of claim 1, wherein the video filter driving module comprises:
the clamping circuit is used for clamping the low voltage of the received first video signal at a fixed voltage under the action of the first bias voltage to obtain an intermediate video signal, and the fixed voltage is greater than the low voltage;
the input end of the first filter is connected with the output end of the clamping circuit and is used for performing first low-pass filtering on the intermediate video signal when a preset level is received to obtain a filtered first intermediate video signal;
the input end of the second filter is connected with the output end of the clamping circuit and is used for carrying out second low-pass filtering on the intermediate video signal when the preset level is received so as to obtain a second filtered intermediate video signal;
the cut-off frequencies of the first filter and the second filter are different;
and the driving module is used for performing gain amplification on the first intermediate video signal or the second intermediate video signal to obtain the second video signal.
3. The integrated chip of claim 2, wherein the video filter driving module further comprises:
and the input end of the NOT gate is connected with the control end of the second filter, and the output end of the NOT gate is connected with the control end of the first filter, and the NOT gate is used for receiving a control level.
4. The integrated chip of claim 2, wherein the first filter and the second filter are each 10 th order filters.
5. The integrated chip of claim 2, wherein the first filter is a filter with a cutoff frequency of 35 MHz.
6. The integrated chip of claim 2, wherein the second filter is a filter with a cutoff frequency of 55 MHz.
7. The integrated chip of claim 2, wherein the driver module is a 6dB driver module.
8. The integrated chip of any one of claims 1 to 7, wherein the video-over-coax decoding module is a comparator formed based on an analog circuit.
9. The integrated chip of claim 8, wherein the bias circuit comprises:
the self-starting circuit is used for starting the bias current generating circuit after the self-starting circuit is electrified;
the bias current generating circuit is connected with the output end of the self-starting circuit at a control end and is used for generating initial bias current after starting;
the input end of the first current mirror is connected with the output end of the bias current generating circuit, and the output end of the first current mirror is connected with the video filtering driving module and is used for carrying out first mirroring on the initial bias current to obtain a first bias voltage;
and the second current mirror is used for carrying out second mirror image on the initial bias current to obtain a second bias voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202021333615.3U CN212064199U (en) | 2020-07-08 | 2020-07-08 | Integrated chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021333615.3U CN212064199U (en) | 2020-07-08 | 2020-07-08 | Integrated chip |
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| CN212064199U true CN212064199U (en) | 2020-12-01 |
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| CN202021333615.3U Active CN212064199U (en) | 2020-07-08 | 2020-07-08 | Integrated chip |
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Address after: 310000 room 701, building 9, No. 1, Weiye Road, Puyan street, Binjiang District, Hangzhou City, Zhejiang Province Patentee after: Hangzhou ruimeng Technology Co.,Ltd. Address before: 310051 room 701, building 9, No.1 Weiye Road, Puyan street, Binjiang District, Hangzhou City, Zhejiang Province Patentee before: HANGZHOU RUIMENG TECHNOLOGY Co.,Ltd. |