CN212060495U

CN212060495U - Fault test vector generating circuit

Info

Publication number: CN212060495U
Application number: CN201922240389.8U
Authority: CN
Inventors: 江威; 周杰; 郭思铭; 陈之射; 戴文君
Original assignee: Wuhan Jiaqilai Technology Co ltd
Current assignee: Wuhan Jiaqilai Technology Co ltd
Priority date: 2019-12-14
Filing date: 2019-12-14
Publication date: 2020-12-01
Anticipated expiration: 2029-12-14

Abstract

The utility model provides a fault test vector generating circuit, which comprises an SPWM generator, a singlechip, a voltage acquisition sub-circuit and a current acquisition sub-circuit, wherein the UART port of the singlechip is electrically connected with the input end of the SPWM generator; the output end of the SPWM generator is electrically connected with the input end of the voltage acquisition sub-circuit and the input end of the current acquisition sub-circuit respectively, the output end of the voltage acquisition sub-circuit is electrically connected with the feedback input end of the SPWM generator, and the output end of the current acquisition sub-circuit is electrically connected with the I/O port of the single chip microcomputer. The utility model discloses a set up voltage acquisition sub-circuit and electric current acquisition sub-circuit alone, give SPWM generator with voltage feedback, give singlechip and SPWM generator with the current feedback, independently form voltage feedback return circuit and current feedback return circuit, realize the electric current high accuracy control to the test vector.

Description

Fault test vector generating circuit

Technical Field

The utility model relates to a fault indicator equipment technical field especially relates to a fault test vector generating circuit for fault indicator.

Background

When a circuit is tested, the vector applied to each input of the circuit is called a test vector, and the normal circuit output vector of the circuit under test corresponding to the test vector is called a non-fault output vector. With the development of the process, the circuit is more and more complex, and reliable test has close relation to the quality and the time to market of the product. Therefore, generating reliable test vectors is an important factor for guaranteeing the product quality.

The test vector of the circuit is usually used for verifying whether the circuit can complete the work or function expected by design, simulating the actual working state of the circuit, inputting a series of ordered or random test signals at the speed specified by the circuit, and then detecting whether the output signal conforms to the expected data at the output end of the circuit so as to judge whether the circuit functions normally; generally, the test vectors are divided into ac parametric tests and dc parametric tests: the alternating current parameter test is to verify the parameters of the circuit related to time by taking time as a unit, and the direct current parameter test is to determine the steady state test of the device parameters based on ohm's law. The existing circuit fault test equipment lacks the anti-interference capability, so that the input of test vectors is unstable, and the reliability and the accuracy of circuit test cannot be ensured.

SUMMERY OF THE UTILITY MODEL

In view of this, the utility model provides a can carry out the fault test vector generating circuit of feedback control to circuit test vector.

The technical scheme of the utility model is realized like this: the utility model provides a fault test vector generating circuit, which comprises an SPWM generator (1) and a single chip microcomputer (2), wherein the UART port of the single chip microcomputer (2) is electrically connected with the input end of the SPWM generator (1); the SPWM controller is characterized by further comprising a voltage acquisition sub-circuit (3) and a current acquisition sub-circuit (4), wherein the output end of the SPWM generator (1) is respectively electrically connected with the input end of the voltage acquisition sub-circuit (3) and the input end of the current acquisition sub-circuit (4), the output end of the voltage acquisition sub-circuit (3) is electrically connected with the feedback input end of the SPWM generator (1), and the output end of the current acquisition sub-circuit (4) is electrically connected with an I/O port of the single chip microcomputer (2).

On the basis of the above technical solution, preferably, the voltage acquisition sub-circuit (3) includes voltage dividing resistors R17, R18, R19, R20 and R21, one end of the voltage dividing resistor R17 is connected in parallel to the output end of the SPWM generator (1), the other end of the voltage dividing resistor R17 is connected in parallel to one ends of resistors R18, R19 and R20, and the other ends of the resistors R18, R19 and R20 are connected in parallel and then grounded; the non-grounded end of the resistor R20 is also connected in series with one end of the resistor R21, and the other end of the resistor R21 is electrically connected with the feedback voltage input end of the SPWM generator (1).

Further preferably, the current collecting sub-circuit (4) comprises a first operational amplifier A1 and a sampling resistor R11; the non-inverting input end of the first operational amplifier A1 is electrically connected with a power supply after voltage division through resistors R13 and R14, one end of the sampling resistor R11 is electrically connected with the output end of the SPWM generator (1), the inverting input end of the first operational amplifier A1 and the feedback current input end of the SPWM generator (1), and the other end of the sampling resistor R11 is grounded; the output terminal of the first operational amplifier A1 is also electrically connected with the enable output terminal of the SPWM generator (1).

Still further preferably, the single chip microcomputer (2) is an STM32F0 single chip microcomputer, and the inverting input terminal of the first operational amplifier a1 is electrically connected to the ADC port of the single chip microcomputer (2).

More preferably, the SPWM generator (1) includes an SPWM chip U2, a pin 4 and a pin 5 of the U2 are electrically connected to the UART port of the single chip microcomputer (2), and a pin 3 and a pin 5 of the U2 are grounded after being connected in parallel; pin 8, pin 17 and pin 26 of U2 are all electrically connected to a power supply; the pin 9, the pin 12, the pin 16, the pin 19, the pin 20, the pin 23 and the pin 32 of the U2 are all grounded, the pin 10 and the pin 11 are respectively connected with the capacitors C1 and C2 in series and then grounded, and a crystal oscillator Y1 is connected between the pin 10 and the pin 11 in parallel.

Still further preferably, the SPWM generator (1) further includes an amplifying sub-circuit (5), an input terminal of the amplifying sub-circuit (5) is electrically connected to the SPWM output terminal of the SPWM chip U2, and an input terminal of the sampling resistor R11 is electrically connected to an output terminal of the amplifying sub-circuit (5).

Further preferably, the amplifier sub-circuit (5) includes a transistor Q1, a base of the transistor Q1 is electrically connected to an output terminal of the SPWM chip U2, and an emitter of the transistor Q1 is electrically connected to another output terminal of the SPWM chip U2 or a power supply.

Further preferably, the amplifier sub-circuit (5) further includes a MOS transistor driving circuit U1 and a plurality of MOS transistors, an input terminal of the MOS transistor driving circuit U1 is electrically connected to a collector of the transistor Q1, and an output terminal of the MOS transistor driving circuit U1 is electrically connected to an input terminal of the MOS transistor.

Further preferably, the electronic device further comprises a temperature control sub-circuit (6), the temperature control sub-circuit (6) comprises an NTC resistor, a fan F1 and a triode Q5, one end of the NTC resistor is respectively connected in parallel with one end of a capacitor C16 and a pin 15 of the SPWM chip U2, the other end of the NTC resistor is electrically connected with a power supply, and the other end of the capacitor C16 is grounded; the NTC resistor is attached to the MOS tube; pin 7 of the SPWM chip U2 is electrically connected to the base of the transistor Q5, the collector of the transistor Q5 is electrically connected to the fan F1, and the emitter of the transistor Q5 is grounded.

The utility model provides a pair of fault test vector generating circuit for prior art, has following beneficial effect:

(1) the utility model discloses a set up voltage acquisition sub-circuit and electric current acquisition sub-circuit alone, feed back the SPWM generator with voltage, feed back singlechip and SPWM generator with the electric current, independently form voltage feedback return circuit and current feedback return circuit, realize the electric current high accuracy control to the test vector;

(2) the amplification sub-circuit can amplify the output of the SPWM chip and then output the amplified output to the outside;

(3) the MOS tube driving circuit and the MOS tube can further drive a larger load;

(4) the NTC thermistor of the temperature control sub-circuit can monitor the temperature of the MOS tube, and the fan can cool the MOS tube to prevent the MOS tube from being damaged due to overhigh temperature.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a block diagram of a fault test vector generation circuit according to the present invention;

fig. 2 is a wiring diagram of the SPWM generator, the voltage acquisition sub-circuit, the current acquisition sub-circuit, and the amplification sub-circuit of the fault test vector generation circuit of the present invention;

fig. 3 is a wiring diagram of a MOS transistor driving circuit and a MOS transistor of a fault test vector generation circuit according to the present invention;

fig. 4 is a wiring diagram of the temperature control sub-circuit of the fault test vector generation circuit of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work all belong to the protection scope of the present invention.

As shown in fig. 1, the utility model provides a fault test vector generating circuit, which comprises an SPWM generator 1, a single chip microcomputer 2, a voltage collecting sub-circuit 3 and a current collecting sub-circuit 4, wherein the UART port of the single chip microcomputer 2 is electrically connected with the input end of the SPWM generator 1; the output end of the SPWM generator 1 is electrically connected with the input end of the voltage acquisition sub-circuit 3 and the input end of the current acquisition sub-circuit 4 respectively, the output end of the voltage acquisition sub-circuit 3 is electrically connected with the feedback input end of the SPWM generator 1, and the output end of the current acquisition sub-circuit 4 is electrically connected with the I/O port of the singlechip 2. As can be seen from fig. 1, the output end of the SPWM generator 1 is respectively provided with a signal input voltage acquisition sub-circuit 3 and a current acquisition sub-circuit 4, feedback signals in the voltage acquisition sub-circuit 3 and the current acquisition sub-circuit 4 are input into the SPWM generator 1 and the single chip microcomputer 2, and input signal adjustment is realized through two closed loops, so that the current precision of the output test vector is improved. The output signal of the SPWM generator 1 can be amplified and inverted to be converted into alternating current output meeting the requirement.

As shown in fig. 2, the voltage collecting sub-circuit 3 includes voltage dividing resistors R17, R18, R19, R20, R21, and capacitors C9, C10, and C11, the voltage dividing resistor R17 is connected in series with the capacitor C9, the other end of the capacitor C9 is connected in parallel to the output end of the SPWM generator 1, the other end of the voltage dividing resistor R17 is connected in parallel to one ends of the resistors R18, R19, and R20, and the other ends of the resistors R18, R19, and R20 are connected in parallel and then grounded; the non-grounded end of the resistor R20 is also connected in series with one end of the resistor R21, the other end of the resistor R21 is electrically connected with the feedback voltage input end of the SPWM generator 1, and two ends of the resistor R21 are connected in parallel with capacitors C10 and C11. After multi-stage voltage reduction, the adopted voltage signal is input into the feedback voltage input end of the SPWM generator 1, and then the output voltage of the output end of the SPWM generator 1 is adjusted. The resistor R18 may be an adjustable resistor to accommodate different ranges of sampled voltage signals.

As shown in fig. 2, the current collecting sub-circuit 4 includes a first operational amplifier a1 and a sampling resistor R11; the non-inverting input end of the first operational amplifier A1 is electrically connected with a power supply after voltage division through resistors R13 and R14, one end of the sampling resistor R11 is electrically connected with the output end of the SPWM generator 1, the inverting input end of the first operational amplifier A1 and the feedback current input end of the SPWM generator 1 respectively, and the other end of the sampling resistor R11 is grounded; the output terminal of the first operational amplifier a1 is also electrically connected to the enable output terminal of the SPWM generator 1. In the figure, the stable voltage obtained by dividing the +5V power supply by the resistors R13 and R14 is about 0.65V, the two ends of R14 are also connected in parallel with the filter capacitor C7 as the non-inverting input of the first transport amplifier a1, and the current sampled from the SPWM generator 1 is filtered by the capacitor C6 and then is used as the inverting input of the first transport amplifier a 1; on the other hand, the current sampled from the SPWM generator 1 is fed to the feedback current input of the SPWM generator 1 through a resistor R12.

The output of the first transport amplifier a1 is connected to the enable output of the SPWM generator 1, and since the non-inverting input remains unchanged, the SPWM generator 1 is always on. In order to keep the output of the first transport amplifier a1 always at a high level, a pull-up resistor R10 and a capacitor C5 are connected in parallel at the output terminal of the first transport amplifier a1, the other terminal of the pull-up resistor R10 is also electrically connected to a +5V power supply, and the other terminal of the capacitor C5 is grounded.

The utility model provides a singlechip 2 is STM32F0 singlechip, the inverting input of first operational amplifier A1 still with singlechip 2's ADC port electric connection, the electric current of sampling resistance R11 department flows into singlechip 2 and as the current feedback input, singlechip 2 can adjust the UART output according to sampling current to realize the electric current closed loop control.

As shown in fig. 2, the SPWM generator 1 of the present invention includes an SPWM chip U2, a pin 4 and a pin 5 of U2 are electrically connected to the UART port of the single chip microcomputer 2, and a pin 3 and a pin 5 of U2 are connected in parallel and then grounded; pin 8, pin 17 and pin 26 of U2 are all electrically connected to a power supply; the pin 9, the pin 12, the pin 16, the pin 19, the pin 20, the pin 23 and the pin 32 of the U2 are all grounded, the pin 10 and the pin 11 are respectively connected with the capacitors C1 and C2 in series and then grounded, and a crystal oscillator Y1 is connected between the pin 10 and the pin 11 in parallel. Pin 8 of the SPWM chip U2 is an operating state indication, and the light emitting diode D1 on the pin is normally on during normal operation. To adjust the output mode or operating state of U2, a jumper may be set on its pin. For example, jumper wires are arranged on the pin 1 and the pin 2 to adjust the dead time of the internal MOS tube; pin 9 is a PWM output type selection; pin 18 and pin 19 are frequency mode selections; the pin 20 is selected by a polarity modulation mode; pin 21 is a soft start function enable input; decoupling capacitors C3 and C4 are connected in parallel to each pin connected to the power supply. The pin 27, the pin 28, the pin 29 and the pin 30 of the SPWM chip U2 are four-way outputs, and the jumper wires JP1 to JP8 can be selected according to actual needs to change the operating state of each pin.

Preferably, the SPWM chip U2 of the present invention can be an EG8010 chip from high stand crystal microelectronics limited.

As the utility model discloses further improvement, SPWM generator 1 still includes amplifier sub-circuit 5, amplifier sub-circuit 5's input and SPWM chip U2's SPWM output electric connection, sampling resistor R11's input and amplifier sub-circuit 5's output electric connection.

Specifically, as a special case of the present invention, the amplifier sub-circuit 5 includes four triodes Q1, Q2, Q3 and Q4, bases of the triodes Q1 and Q2 are electrically connected to the pin 29 of the SPWM chip U2, and emitters of the triodes Q1 and Q2 are electrically connected to the pin 30 of the SPWM chip U2; and other output ends of the SPWM chip U2 or the power supply are electrically connected. Base resistors R2, R3, R4 and R5 are respectively arranged at the bases of the triodes Q1, Q2, Q3 and Q4, and grounding resistors R6, R7, R8 and R9 are respectively connected in parallel at the emitters. In this case, a sampled voltage or current may also be drawn from the emitters of transistors Q1, Q2, Q3, and Q4.

As shown in fig. 3, the amplifying sub-circuit 5 further includes a MOS transistor driving circuit U1 and a plurality of MOS transistors, an input terminal of the MOS transistor driving circuit U1 is electrically connected to a collector of the transistor Q1, and an output terminal of the MOS transistor driving circuit U1 is electrically connected to an input terminal of the MOS transistor.

As an embodiment of the present invention, fig. 3 adopts 2 MOS transistor driving circuits U1 and U3, and correspondingly sets 4 MOS transistors V1, V2, V3 and V4, pin 12 of MOS transistor driving circuit U1 is electrically connected to the emitter of Q2, and pin 14 is electrically connected to the emitter of Q1; a pin 12 of the MOS tube driving circuit U3 is electrically connected with an emitter of Q4, and a pin 14 is electrically connected with an emitter of Q3; pins 11 of the MOS tube driving circuits U1 and U3 are both electrically connected with a +5V power supply, and pin 2 and pin 15 are both grounded. Pins 8 of the MOS tube driving circuits U1 and U3 are electrically connected with gates of the MOS tube V1 and the MOS tube V2 respectively, and pins 1 of the MOS tube driving circuits U1 and U3 are electrically connected with gates of the MOS tube V3 and the MOS tube V4 respectively; the collectors of the MOS transistor V1 and the MOS transistor V2 are both electrically connected with a +400V power supply, and the emitter of the MOS transistor V1 is connected in parallel with the collector of the MOS transistor V3 and a pin 6 of the MOS transistor drive circuit U1 and then led out to serve as a first output end P of the amplifier sub-circuit 5; a filter capacitor C14 and a filter capacitor C15 are connected between the first output end and the +400V power supply in parallel; an emitter of the MOS transistor V2 is connected in parallel with a collector of the MOS transistor V4 and a pin 6 of the MOS transistor drive circuit U3, and then a second output end N serving as an amplifier sub-circuit 5 is led out; a pin 3 of the MOS tube driving circuit U1 is electrically connected with a +12V power supply, a diode D2 is connected between the pin 3 and a pin 7 in parallel, and the pin 7 is connected with a pin 6 in parallel through a capacitor C12; a pin 3 of the MOS tube driving circuit U3 is electrically connected with a +12V power supply, a diode D3 is connected between the pin 3 and a pin 7 in parallel, and the pin 7 is connected with a pin 6 in parallel through a capacitor C13; the emitters of the MOS transistor V3 and the MOS transistor V4 are connected in parallel and then electrically connected with one end of the resistor R30, and the other end of the resistor R30 is grounded. As shown in the figure, each MOS tube grid is provided with a grid resistor, diodes are reversely connected in parallel at two ends of the grid resistor, and resistors are connected in parallel between each MOS tube grid and the emitter. To avoid abrupt changes in the output voltage, an inductor L1 may be connected in series with the output P of the amplifier sub-circuit 5. In such an embodiment, the capacitor R30 can be used as a current sampling resistor made of constantan wire as a direct acquisition means of sampling current. The 4 MOS tubes in the figure form an H-bridge circuit which can drive a larger load. Of course, other combinations are possible.

In the above embodiment, the MOS transistor may generate heat during operation, and in order to protect the MOS transistor, the temperature control sub-circuit 6 is provided. The temperature control sub-circuit 6 comprises an NTC resistor, a fan F1 and a triode Q5, wherein one end of the NTC resistor is respectively connected with one end of a capacitor C16 and a pin 15 of the SPWM chip U2 in parallel, the other end of the NTC resistor is electrically connected with a power supply, and the other end of the capacitor C16 is grounded; the NTC resistor is attached to the MOS tube; pin 7 of the SPWM chip U2 is electrically connected to the base of the transistor Q5, the collector of the transistor Q5 is electrically connected to the fan F1, and the emitter of the transistor Q5 is grounded. When the NTC thermistor is heated, the resistance value of the NTC thermistor is reduced, so that the pin 15 of the SPWM chip U2 obtains an input signal, the pin 7 is driven to send a trigger signal, the Q5 is turned on, and the fan F1 operates to cool the MOS transistor.

In addition, in order to prevent the output from overflowing the adverse effect that brings, the utility model discloses still have the overcurrent protection function, realize through current sampling circuit and second operational amplifier A2 during overcurrent protection. As shown in fig. 2 and 3, the non-inverting input of the first transport amplifier a1 is connected in parallel with the non-inverting input of the second operational amplifier a2, and the inverting input of the second operational amplifier a2 is connected in parallel with the inverting input of the first transport amplifier a 1; the output end of the second operational amplifier A2 is electrically connected with the pins 13 of the 2 MOS tube driving circuits U1 and U3 respectively; when the feedback current led out by the output of the SPWM generator 1 or the amplification sub-circuit 5 is large, the output end of the second operational amplifier a2 outputs a high level, and the MOS transistor driving circuits U1 and U3 close the output, thereby protecting the MOS transistors and preventing damage caused by overcurrent. The output end of the second operational amplifier A2 can be further externally connected with a pull-up resistor R16, one end of the pull-up resistor R16 is connected with the output end of the second operational amplifier A2 in parallel with one end of a capacitor C8, the other end of the pull-up resistor R16 is electrically connected with a power supply, and the other end of the capacitor C8 is grounded; the first transport amplifier a1 and the second operational amplifier a2 can be integrated in one operational amplifier chip, which can save circuit board space.

The utility model provides a MOS manages drive circuit U1 and U3 can adopt IRS2113SPBF product of IRF company.

The utility model discloses a power can adopt chargeable 12V lithium cell to realize, converts voltage into 5V, 6V or 3.3V through chips such as steady voltage chip LM7805, LM7806 or ASM1117-3.3 and supplies each sub-circuit to use. Rechargeable lithium cell can make the utility model discloses can produce great electric current, realize the field test demand under the multiple scene, and the fault test equipment need not dispose external power supply, and the equipment of being convenient for is miniaturized and carries.

The above description is only a preferred embodiment of the present invention, and should not be taken as limiting the invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A fault test vector generation circuit comprises an SPWM generator (1) and a single chip microcomputer (2), wherein a UART port of the single chip microcomputer (2) is electrically connected with an input end of the SPWM generator (1); the method is characterized in that: the SPWM controller is characterized by further comprising a voltage acquisition sub-circuit (3) and a current acquisition sub-circuit (4), wherein the output end of the SPWM generator (1) is respectively electrically connected with the input end of the voltage acquisition sub-circuit (3) and the input end of the current acquisition sub-circuit (4), the output end of the voltage acquisition sub-circuit (3) is electrically connected with the feedback input end of the SPWM generator (1), and the output end of the current acquisition sub-circuit (4) is electrically connected with an I/O port of the single chip microcomputer (2).

2. A fault test vector generation circuit as claimed in claim 1, wherein: the voltage acquisition sub-circuit (3) comprises voltage division resistors R17, R18, R19, R20 and R21, one end of the voltage division resistor R17 is connected to the output end of the SPWM generator (1) in parallel, the other end of the voltage division resistor R17 is connected with one ends of resistors R18, R19 and R20 in parallel, and the other ends of the resistors R18, R19 and R20 are connected with the ground after being connected with the resistors in parallel; the non-grounded end of the resistor R20 is also connected in series with one end of the resistor R21, and the other end of the resistor R21 is electrically connected with the feedback voltage input end of the SPWM generator (1).

3. A fault test vector generation circuit as claimed in claim 2, wherein: the current acquisition sub-circuit (4) comprises a first operational amplifier A1 and a sampling resistor R11; the non-inverting input end of the first operational amplifier A1 is electrically connected with a power supply after voltage division through resistors R13 and R14, one end of the sampling resistor R11 is electrically connected with the output end of the SPWM generator (1), the inverting input end of the first operational amplifier A1 and the feedback current input end of the SPWM generator (1), and the other end of the sampling resistor R11 is grounded; the output terminal of the first operational amplifier A1 is also electrically connected with the enable output terminal of the SPWM generator (1).

4. A fault test vector generation circuit according to claim 3, wherein: the single chip microcomputer (2) is an STM32F0 single chip microcomputer, and the inverting input end of the first operational amplifier A1 is electrically connected with the ADC port of the single chip microcomputer (2).

5. A fault test vector generation circuit according to claim 3, wherein: the SPWM generator (1) comprises an SPWM chip U2, a pin 4 and a pin 5 of a U2 are electrically connected with a UART port of the singlechip (2), and a pin 3 and a pin 5 of a U2 are connected in parallel and then grounded; pin 8, pin 17 and pin 26 of U2 are all electrically connected to a power supply; the pin 9, the pin 12, the pin 16, the pin 19, the pin 20, the pin 23 and the pin 32 of the U2 are all grounded, the pin 10 and the pin 11 are respectively connected with the capacitors C1 and C2 in series and then grounded, and a crystal oscillator Y1 is connected between the pin 10 and the pin 11 in parallel.

6. The fault test vector generation circuit of claim 5, wherein: SPWM generator (1) still includes amplifier sub-circuit (5), the SPWM output electric connection of the input of amplifier sub-circuit (5) and SPWM chip U2, sampling resistance R11's input and amplifier sub-circuit (5) output electric connection.

7. The fault test vector generation circuit of claim 6, wherein: the amplifying sub-circuit (5) comprises a triode Q1, the base of the triode Q1 is electrically connected with one output end of the SPWM chip U2, and the emitter of the triode Q1 is electrically connected with other output ends of the SPWM chip U2 or a power supply.

8. The fault test vector generation circuit of claim 7, wherein: the amplifying sub-circuit (5) further comprises an MOS tube driving circuit U1 and a plurality of MOS tubes, the input end of the MOS tube driving circuit U1 is electrically connected with the collector of the triode Q1, and the output end of the MOS tube driving circuit U1 is electrically connected with the input ends of the MOS tubes.

9. The fault test vector generation circuit of claim 8, wherein: the temperature control sub-circuit (6) comprises an NTC resistor, a fan F1 and a triode Q5, wherein one end of the NTC resistor is connected with one end of a capacitor C16 and a pin 15 of an SPWM chip U2 in parallel, the other end of the NTC resistor is electrically connected with a power supply, and the other end of the capacitor C16 is grounded; the NTC resistor is attached to the MOS tube; pin 7 of the SPWM chip U2 is electrically connected to the base of the transistor Q5, the collector of the transistor Q5 is electrically connected to the fan F1, and the emitter of the transistor Q5 is grounded.